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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-31 07:56:36 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-31 07:56:36 +0200 |
| commit | b47da302862e0e5510bb5ef285fa807574042f43 (patch) | |
| tree | 1b5772375253ba6e9391273b9d40ba0f9e8a3dbe | |
| parent | 6625c5c1b2d7188546e1f34449f87adaa58e9699 (diff) | |
| download | ghdl-yosys-plugin-b47da302862e0e5510bb5ef285fa807574042f43.tar.gz ghdl-yosys-plugin-b47da302862e0e5510bb5ef285fa807574042f43.tar.bz2 ghdl-yosys-plugin-b47da302862e0e5510bb5ef285fa807574042f43.zip | |
Add regression test for versa_ecp5
| -rwxr-xr-x | testsuite/examples/test-ecp5_versa/testsuite.sh | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/examples/test-ecp5_versa/testsuite.sh b/testsuite/examples/test-ecp5_versa/testsuite.sh new file mode 100755 index 0000000..44dac88 --- /dev/null +++ b/testsuite/examples/test-ecp5_versa/testsuite.sh @@ -0,0 +1,25 @@ +#!/bin/sh + +topdir=../.. +. $topdir/testenv.sh + +top=../../.. +src=$top/examples/ecp5_versa + +VHDL_SYN_FILES="$src/versa_ecp5_top.vhdl \ + $src/pll_mac.vhd \ + $src/soc_iomap_pkg.vhdl \ + $src/uart.vhdl \ + $src/uart_tx.vhdl \ + $src/uart_rx.vhdl \ + $src/fifobuf.vhdl" + +VERILOG_FILES="\ + $top/library/wrapper/primitives.v \ + $top/library/wrapper/wrapper.v \ + $top/library/wrapper/bram.v +" + +FREQ=25000000 + +run_yosys -p "ghdl -gCLK_FREQUENCY=$FREQ --work=ecp5um $top/library/ecp5u/components.vhdl --work=work $VHDL_SYN_FILES -e; read_verilog $VERILOG_FILES; synth_ecp5 -top versa_ecp5_top -json top_ecp5_top.json" -l report.txt -q |