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author | Anton Blanchard <anton@ozlabs.org> | 2019-10-14 15:21:40 +1100 |
---|---|---|
committer | tgingold <tgingold@users.noreply.github.com> | 2019-10-14 06:21:40 +0200 |
commit | 62dd7c9e0f60d436c843bc7a654b9c60ef5871cc (patch) | |
tree | ee686a9157e86b7126dec6cf5dc4f2098667b6e1 | |
parent | 9a8c8162b869479017ccb6f642fadce717685fa3 (diff) | |
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Fix a couple of compiler warnings (#62)
I see a few compiler warnings on gcc 9.2:
src/ghdl.cc: In function ‘Yosys::RTLIL::SigSpec get_src(std::vector<Yosys::RTLIL::Wire*>&, GhdlSynth::Net)’:
src/ghdl.cc:123:43: warning: ‘valzx’ may be used uninitialized in this function [-Wmaybe-uninitialized]
123 | switch(((val01 >> i)&1)+((valzx >> i)&1)*2)
| ~~~~~~~^~~~~
src/ghdl.cc:123:26: warning: ‘val01’ may be used uninitialized in this function [-Wmaybe-uninitialized]
123 | switch(((val01 >> i)&1)+((valzx >> i)&1)*2)
| ~~~~~~~^~~~~
src/ghdl.cc:99:26: warning: ‘val’ may be used uninitialized in this function [-Wmaybe-uninitialized]
99 | bits[i] = (val >> i) & 1 ? RTLIL::State::S1 : RTLIL::State::S0;
| ~~~~~^~~~~
These both appear to be spurious, but initialize them to 0 to avoid the
warning.
-rw-r--r-- | src/ghdl.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index 83b76d0..1d26ded 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -92,7 +92,7 @@ static RTLIL::SigSpec get_src(std::vector<RTLIL::Wire *> &net_map, Net n) { const unsigned wd = get_width(n); std::vector<RTLIL::State> bits(wd); - unsigned int val; + unsigned int val = 0; for (unsigned i = 0; i < wd; i++) { if (i % 32 == 0) val = get_param_uns32(inst, i / 32); @@ -113,8 +113,8 @@ static RTLIL::SigSpec get_src(std::vector<RTLIL::Wire *> &net_map, Net n) { const unsigned wd = get_width(n); std::vector<RTLIL::State> bits(wd); - unsigned int val01; - unsigned int valzx; + unsigned int val01 = 0; + unsigned int valzx = 0; for (unsigned i = 0; i < wd; i++) { if (i % 32 == 0) { val01 = get_param_uns32(inst, 2*(i / 32)); |