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| author | Tristan Gingold <tgingold@free.fr> | 2020-04-23 17:41:35 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-04-23 17:42:42 +0200 |
| commit | 3507458eea01664173a86ab8aab6a53f561791b1 (patch) | |
| tree | af93b5a90698a3e4ddeb8eb2a4f9ec73ef5454b7 | |
| parent | 0a8a2e95454bde1888edbca50c3894cac5057c23 (diff) | |
| download | ghdl-yosys-plugin-3507458eea01664173a86ab8aab6a53f561791b1.tar.gz ghdl-yosys-plugin-3507458eea01664173a86ab8aab6a53f561791b1.tar.bz2 ghdl-yosys-plugin-3507458eea01664173a86ab8aab6a53f561791b1.zip | |
handle Id_Tri and Id_Resolver
| -rw-r--r-- | src/ghdl.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index 54fa7e9..bdf40f8 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -664,6 +664,8 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Anyseq: case Id_Mem_Rd: case Id_Mem_Rd_Sync: + case Id_Tri: + case Id_Resolver: case Id_User_None: case Id_User_Parameters: for (Port_Idx idx = 0; idx < get_nbr_outputs(im); idx++) { @@ -997,6 +999,13 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Anyseq: add_formal_input(module, net_map, inst, "$anyseq"); break; + case Id_Tri: + module->addTribuf(to_str(iname), IN(1), IN(0), OUT(0)); + break; + case Id_Resolver: + module->connect(OUT(0), IN(0)); + module->connect(OUT(0), IN(1)); + break; case Id_Memory: case Id_Memory_Init: // Will be handled later. |