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| author | Tristan Gingold <tgingold@free.fr> | 2021-03-27 08:44:24 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-03-27 08:44:24 +0100 |
| commit | 266028e098b53b41e381fb982b6fef35c8aabe02 (patch) | |
| tree | 9c6bb95f27618807045f98cfada14f0949741e88 | |
| parent | d908b3be7a30010aa698b8856fff9e8c9825a90c (diff) | |
| download | ghdl-yosys-plugin-266028e098b53b41e381fb982b6fef35c8aabe02.tar.gz ghdl-yosys-plugin-266028e098b53b41e381fb982b6fef35c8aabe02.tar.bz2 ghdl-yosys-plugin-266028e098b53b41e381fb982b6fef35c8aabe02.zip | |
ghdl.cc: remove unused/extra memory module. Fix #1699
| -rw-r--r-- | src/ghdl.cc | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index d013667..c107d78 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -420,13 +420,6 @@ static void import_memory(RTLIL::Module *module, std::vector<RTLIL::Wire *> &net // Memories appear only once. log_assert(!is_set(net_map, mem_o)); - // Create memory. - RTLIL::Memory *memory = new RTLIL::Memory; - memory->name = "$mem$" + mem_str; - - // Add it to module. - module->memories[memory->name] = memory; - // Count number of read and write ports. // Extract width, size, abits. unsigned nbr_rd = 0; @@ -479,9 +472,6 @@ static void import_memory(RTLIL::Module *module, std::vector<RTLIL::Wire *> &net log_warning("memory %s has read ports after and before write ports", mem_str.c_str()); unsigned size = get_width(mem_o) / width; - memory->width = width; - memory->size = size; - memory->start_offset = 0; // Create the memory. Cell *mem = module->addCell(mem_str, "$mem"); |