index : iCE40/flashrom	master
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path: root/pm49fl00x.c

	Commit message (Expand)	Author	Age	Files	Lines
*	Add struct flashctx * parameter to all functions accessing flash chips	Carl-Daniel Hailfinger	2011-12-18	1	-5/+9
*	Use struct flashctx instead of struct flashchip for flash chip access	Carl-Daniel Hailfinger	2011-12-14	1	-2/+2
*	Unsignify lengths and addresses in chip functions and structs	Stefan Tauner	2011-11-23	1	-3/+3
*	Remove unneeded inclusions of chipdrivers.h	Stefan Tauner	2011-08-16	1	-1/+0
*	Kill global variables, constants and functions if local scope suffices	Carl-Daniel Hailfinger	2010-07-03	1	-1/+1
*	Kill dead pm49fl00x.c functions	Sean Nelson	2010-03-16	1	-69/+0
*	Convert the remaining references to *_49fl00x	Sean Nelson	2010-02-27	1	-0/+6
*	Split spi.c into programmer and chip code Remove chipdriver.h include from fl...	Sean Nelson	2010-02-26	1	-0/+1
*	Here's a very quick patch to fix the missing unlock code	Sean Nelson	2010-02-19	1	-0/+6
*	Use the register mapping feature bit	Carl-Daniel Hailfinger	2010-01-09	1	-10/+0
*	Generify jedec functions by introducing an address mask	Sean Nelson	2010-01-04	1	-2/+2
*	Kill obsolete exclude range feature	Carl-Daniel Hailfinger	2009-06-19	1	-8/+0
*	Flashrom only checks for very few chips if the erase worked	Carl-Daniel Hailfinger	2009-06-15	1	-3/+8
*	Drop unused/duplicated #includes and some dead code	Uwe Hermann	2009-05-16	1	-1/+0
*	Introduce a type "chipaddr" to abstract the offsets within flash regions	Carl-Daniel Hailfinger	2009-05-16	1	-3/+3
*	FreeBSD definitions of (read|write)[bwl] collide with our own	Carl-Daniel Hailfinger	2009-03-06	1	-1/+1
*	Use helper functions to access flash chips	Carl-Daniel Hailfinger	2009-03-05	1	-1/+1
*	Coding-style fixes for flashrom, partly indent-aided	Uwe Hermann	2008-10-18	1	-10/+16
*	Support Pm49FL004/2 Block Locking Registers	Nikolay Petukhov	2008-05-17	1	-0/+114

generated by cgit v1.2.3 (git 2.25.1) at 2025-04-10 07:59:50 +0000

/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 *  
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *  
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#ifndef MODTOOLS_H
#define MODTOOLS_H

#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include "kernel/celltypes.h"

YOSYS_NAMESPACE_BEGIN

struct ModIndex : public RTLIL::Monitor
{
	struct PortInfo {
		RTLIL::Cell* cell;
		RTLIL::IdString port;
		int offset;

		PortInfo() : cell(), port(), offset() { }
		PortInfo(RTLIL::Cell* _c, RTLIL::IdString _p, int _o) : cell(_c), port(_p), offset(_o) { }

		bool operator<(const PortInfo &other) const {
			if (cell != other.cell)
				return cell < other.cell;
			if (offset != other.offset)
				return offset < other.offset;
			return port < other.port;
		}

		bool operator==(const PortInfo &other) const {
			return cell == other.cell && port == other.port && offset == other.offset;
		}

		unsigned int hash() const {
			return mkhash_add(mkhash(cell->name.hash(), port.hash()), offset);
		}
	};

	struct SigBitInfo
	{
		bool is_input, is_output;
		pool<PortInfo> ports;

		SigBitInfo() : is_input(false), is_output(false) { }

		bool operator==(const SigBitInfo &other) const {
			return is_input == other.is_input && is_output == other.is_output && ports == other.ports;
		}

		void merge(const SigBitInfo &other)
		{
			is_input = is_input || other.is_input;
			is_output = is_output || other.is_output;
			ports.insert(other.ports.begin(), other.ports.end());
		}
	};

	SigMap sigmap;
	RTLIL::Module *module;
	std::map<RTLIL::SigBit, SigBitInfo> database;
	int auto_reload_counter;
	bool auto_reload_module;

	void port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
	{
		for (int i = 0; i < GetSize(sig); i++) {
			RTLIL::SigBit bit = sigmap(sig[i]);
			if (bit.wire)
				database[bit].ports.insert(PortInfo(cell, port, i));
		}
	}

	void port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
	{
		for (int i = 0; i < GetSize(sig); i++) {
			RTLIL::SigBit bit = sigmap(sig[i]);
			if (bit.wire)
				database[bit].ports.erase(PortInfo(cell, port, i));
		}
	}

	const SigBitInfo &info(RTLIL::SigBit bit)
	{
		return database[sigmap(bit)];
	}

	void reload_module(bool reset_sigmap = true)
	{
		if (reset_sigmap) {
			sigmap.clear();
			sigmap.set(module);
		}

		database.clear();
		for (auto wire : module->wires())
			if (wire->port_input || wire->port_output)
				for (int i = 0; i < GetSize(wire); i++) {
					RTLIL::SigBit bit = sigmap(RTLIL::SigBit(wire, i));
					if (bit.wire && wire->port_input)
						database[bit].is_input = true;
					if (bit.wire && wire->port_output)
						database[bit].is_output = true;
				}
		for (auto cell : module->cells())
			for (auto &conn : cell->connections())
				port_add(cell, conn.first, conn.second);

		if (auto_reload_module) {
			if (++auto_reload_counter > 2)
				log_warning("Auto-reload in ModIndex -- possible performance bug!\n");
			auto_reload_module = false;
		}
	}

	void check()
	{
#ifndef NDEBUG
		if (auto_reload_module)
			return;

		for (auto it : database)
			log_assert(it.first == sigmap(it.first));

		auto database_bak = std::move(database);