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* sb600spi: Add spireadmodeRob Barnes2020-03-032-44/+99
| | | | | | | | | | | | | | | | | | Added spireadmode for >= Bolton. Do not override speed or read mode for >= Bolton if parameter not specified. Minor cleanup of sb600spi.c code. TEST=Manual: deploy on tremblye read flash using various parameters BUG=b:147665085,b:147666328 BRANCH=master Change-Id: Id7fec7eb87ff811148217dc56a86dca3fef122ff Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* raiden_debug: Upstream ChromiumOS servo debug board progEdward O'Callaghan2020-03-036-0/+489
| | | | | | | | | | | | | | | | | | Initial check-in of the Raiden debugger programmer. Squash in, raiden_debug: Add missing .write_aai cb fn raiden_debug: greatly improve protocol documentation BUG=b:143389556 BRANCH=none TEST=builds Change-Id: Ifad273a708acea4de797a0808be58960635a8864 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* raiden_debug: Upstream ChromiumOS usb_device helpersEdward O'Callaghan2020-03-024-1/+559
| | | | | | | | | | | | | | | These are helpful usb device accessors and helpers that are later used for the so-called Raiden debugger programmer. BUG=b:143389556 BRANCH=none TEST=builds Change-Id: Ic928220fc919fe4958c8150e61e11470dac88f13 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* util/flashrom_tester: Upstream E2E testing frameworkEdward O'Callaghan2020-02-2416-0/+2680
| | | | | | | | | | | | | | | | | | | The following is a E2E tester for a specific chip/chipset combo. The tester itself is completely self-contained and allows the user to specify which tests they wish to preform. Supported tests include: - chip-name - read - write - erase - wp-locking Change-Id: Ic2905a76cad90b1546b9328d668bf8abbf8aed44 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* ubertest: Add blackbox test uber-scriptDavid Hendricks2020-02-238-0/+2086
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This modifies CB:23025 further to work with upstream as it is now, without the syntax changes in the patch chain. I also gave it a new name since this script is, well, uber. Since flashrom currently only supports reading/writing ROM-sized files we can't easily determine a targeted region offset and size except when a layout file is used. Therefore, some extra arithmetic is needed in the partial write test and the only modes allowed are clobber mode and layout mode. A few other changes: - Update paths and script name - Remove write-protect testing support - Use ROM-sized files only, no region-sized files - Return error if flashmap or ifd mode are used Documentation is ported from https://goo.gl/3jNoL7 into a markdown file and accompanying SVGs. Minor changes were made for clarity and formatting, and references to write protect testing have been removed for the time being. Tested using a Raspberry Pi with a W25Q16 Change-Id: I1af55d5088c54ee33853009797adbd535a506b49 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Add Spansion S25FL512SBernhard Urban-Forster2020-02-091-0/+33
| | | | | | | | | | | | | | | As found on the Tesla AP2.5 board. Based on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html Tested with: flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 -r content.bin Signed-off-by: Bernhard Urban-Forster <lewurm@gmail.com> Change-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c Reviewed-on: https://review.coreboot.org/c/flashrom/+/38596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* chipset_enable.c: Add Ice Lake U to known and tested systemsJohanna Schander2020-02-091-0/+1
| | | | | | | | | | | | | | | | | Intel Ice Lake systems use an 495 Series Chipset that behaves compatible to pch300 chips but chip names are undocumented at this point. This change was tested in read/write/erase on the Razer Blade Stealth (late 2019) with intel 1065G7 CPU and "Ice Lake U Premium PCH". Change-Id: I6227d32f4476420cf1aeec37ebd4b7648e0b3d15 Signed-off-by: Johanna Schander <git@mimoja.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/37987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christoph Pomaska <github@slrie.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Fix building with meson, againAngel Pons2020-02-011-0/+1
| | | | | | | | | | | Change-Id: Iea40da587729f3975a8901d3933e7567805242c5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* chipset_enable: Add Kaby Lake U Prem. to known and tested systemsWim Vervoorn2020-01-221-1/+1
| | | | | | | | | | | | | | | | | Intel Kaby Lake U (with the 9d4e device id) support is available but marked not tested. Tested reading, writing and erasing both internal flash chips on the Facebook Monolith system with the Intel i3 7100U SoC. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Change-Id: Ie35cc896e29baffa63fe9e37c14770001b54e7ec Reviewed-on: https://review.coreboot.org/c/flashrom/+/38481 Tested-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Fix typosCarl-Daniel Hailfinger2020-01-202-2/+2
| | | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Change-Id: Ia5ed00c488b0719b2bdd6c8f304900511684f445 Reviewed-on: https://review.coreboot.org/c/flashrom/+/38477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Revert "pcidev.c: Factor out pcidev_validate() into pure fn"Nico Huber2020-01-191-29/+24
| | | | | | | | | | | | | | This reverts commit e28d75ed7204d7fac2c0fac13978098530b0574e. This is broken in multiple ways, e.g. pcidev_init() can only return NULL. Change-Id: I06242147ba9d3a062d442f645eb0800ef51af19f Signed-off-by: Nico Huber <nico.h@gmx.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Reported-by: Michael Bishop <cleverca22@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38319 Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* stlinkv3_spi: Move a declaration out of for-loop headNico Huber2020-01-021-1/+2
| | | | | | | | | | | | GCC 4.8 wants an explicit `-std=c99` or something for this to work. It seems easier to keep the common declaration style. Change-Id: Ic0819f82169df4d66cc949494229b0749c06e8f6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Miklós Márton <martonmiklosqdev@gmail.com>
* Add support for STLINK V3 debugger/programmer via its SPI bridgeMiklós Márton2019-12-316-0/+590
| | | | | | | | Change-Id: Icffab87ac8f2c570187ed753ec70f054541873a4 Signed-off-by: Miklós Márton <martonmiklosqdev@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable.c: Mark Intel HM76 as DEPAngel Pons2019-12-211-1/+1
| | | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using a Samsung NP530U3C laptop with an Intel HM76 PCH. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: I1097c5fcf782e7ecf52f05c571ad188456307d00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/37803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* mysteries_intel: Add a section about SMM_BWPDavid Hendricks2019-12-141-0/+21
| | | | | | | | | | Something to point users to when SMM_BWP might be causing problems. Change-Id: I394c033e8d4ff96433162f86aefb428d8acf6349 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashrom: Add support for ARC platformRosen Penev2019-12-143-2/+16
| | | | | | | | | Signed-off-by: Rosen Penev <rosenp@gmail.com> Change-Id: I88cbe74b716d5fab16133fbf2ce9c35b74c25f32 Reviewed-on: https://review.coreboot.org/c/flashrom/+/35831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add AT25SF321darkarnium2019-12-142-0/+39
| | | | | | | | | | | | | | | This commit adds support for the Adesto AT25SF321 SPI flash chip. Probe and read operations have been tested via FT2232H interface, but writes have not been verified. Datasheet is available at the following URL: https://www.adestotech.com/wp-content/uploads/DS-AT25SF321_047.pdf Change-Id: I7410815e063ffe154a97d7ea5881c8eb82025f56 Signed-off-by: Peter Adkins <pete@kernelpicnic.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* nicintel_eeprom: Reduce usage of is_i210()Nico Huber2019-12-101-44/+50
| | | | | | | | | | | | | Don't entagle the code paths for the two NIC classes if it's not necessary. Only compile tested. Change-Id: I59164ccf54afbbd64a0598282d13e80ff7fd6fa4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Revert "print.c: Dedup 'test_state_to_text()' logic"Nico Huber2019-12-061-1/+8
| | | | | | | | | | | | | | | | This reverts commit 61e16e549a52194ac80ef40504f2dc661d1ff99c. Obviously throws alignment in the table off and changes output class from `general` to `programmer` for no visible reason. Change-Id: I864044b9fac6af9cf6a89c053eccdcb36f17c7bd Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ft2232_spi: Add support for Tin Can Tools Flyswatter/Flyswatter 2Russ Dill2019-12-012-1/+8
| | | | | | | | | | | | | | | | The Tin Can Tools Flyswatter and Flyswatter 2 have a FT2232H with a JTAG interface wired to port A. The buffers that drive the JTAG pins need to be enabled with an nOE signal from the FT2232H ADBUS6 and ADBUS7 pins. Flyswatter has an ARM-14 JTAG interface and Flyswatter 2 has an ARM-20 JTAG interface. Change-Id: I56b1fb76dcda32bb02980cd54a2853506bfc9dfd Signed-off-by: Russ Dill <Russ.Dill@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* pcidev.c: Factor out pcidev_validate() into pure fnEdward O'Callaghan2019-11-281-24/+29
| | | | | | | | | | This makes writing unit-tests easier. Change-Id: Ia2718f1f40851d3122741cd0e50b0c2b647b727a Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/37264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cbtable.c: Factor out lb_table_validation logicEdward O'Callaghan2019-11-281-10/+18
| | | | | | | | | | | Write a pure function for the table validation logic, it is easier to unit-test. Change-Id: I07b0f95ec0443fa6a8f54eb93f4a7ea1875cccad Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/37239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* cbtable.c: Factor out lb_header_validation logicEdward O'Callaghan2019-11-281-12/+20
| | | | | | | | | | | | Write a pure function for the header validation logic, it is easier to unit-test. Change-Id: Ia288bcbc5c371329952a6efba30ccf0e18965a3d Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/37238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* print.c: Dedup 'test_state_to_text()' logicEdward O'Callaghan2019-11-171-8/+1
| | | | | | | | Change-Id: I72164323d7ff98fc50cb0c47b69741a4f047e098 Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* dediprog.c: Add id parameter to dediprog programmerRyan O'Leary2019-11-151-21/+132
| | | | | | | | | | | | | | | | | | | | | | | | When multiple dediprog programmers are connected, the 'id' parameter allows you to specify which one to use. The id is a string like SF012345 or DP012345. The value is printed on a sticker on the back of the dediprog. This is an improvement over the 'device' parameter which is based on enumeration order and changes when you plug/unplug devices or reboot the machine. To find the id without the sticker, run flashrom with the -V option. This prints the ids as they are enumerated. Alternatively, with dpcmd, you can use the --list-device-id and --fix-device commands to list and write device ids respectively. Note this only supports SF100 at the moment, but SF600 support is possible with more work. Change-Id: I4281213ab02131feb5d47bf66118a001cec0d219 Signed-off-by: Ryan O'Leary <ryanoleary@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix building with GCC 4.9Evgeny Zinoviev2019-11-144-4/+4
| | | | | | | | | | It doesn't like empty initializers. Change-Id: If2988e60401155f87ee3369c77f00ccf9332012c Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* sb600spi.c: Generalise determin_generation() after YangtzeEdward O'Callaghan2019-11-141-21/+9
| | | | | | | | | | Drop dead USE_YANGTZE_HEURISTICS code and add Promontory support. Change-Id: I5aa7370025f5c1af56c6cb96194b6f3007d0ede7 Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* sb600spi.c: Fold up debug logic into determine_generation()Edward O'Callaghan2019-11-141-9/+12
| | | | | | | | | Change-Id: I6c722e29b321285bf20fb5ee30c912dcdd83411b Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* sb600spi.c: Consolidate smbus dev revision derivationEdward O'Callaghan2019-11-141-13/+17
| | | | | | | | | | | V.2: Rename 'find_smbus_dev()' -> 'find_smbus_dev_rev()'. Change-Id: I766b29cc1c7d01aa0bcf6cb9ff5ab73fa1995dcd Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36420 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: Nico Huber <nico.h@gmx.de>
* Add support for National Instruments USB-845x devicesMiklós Márton2019-11-145-1/+792
| | | | | | | | Change-Id: I9477b6f0193bfdf20bbe63421a7fb97b597ec549 Signed-off-by: Miklós Márton <martonmiklosqdev@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/25683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add W25Q128JW_DTRPeichao Wang2019-11-132-0/+39
| | | | | | | | | | | | | Port the code from chromeos flashrom BUG=b:144297264 TEST=Tested using W25Q128JWDTR in SPI mode Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ifc28878b17dc10da2cfd8f82fffbd57adb22799e Reviewed-on: https://review.coreboot.org/c/flashrom/+/36717 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add missing N25Q/MT25Q variantsJacob Creedon2019-11-112-10/+535
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds missing voltage and capacity variants for N25Q and MT25Q series devices. This also fixes a typo in some model numbers where the last letter should have been a G instead of an E. Added devices include: N25Q256..1E N25Q512..1G N25Q00A..1G N25Q00A..3G MT25QU128 MT25QL128 MT25QU256 MT25QU512 tested by Jacob Creedon <jcreedon@google.com> MT25QL01G tested by Konstantin Grudnev <grudnevkv@gmail.com> MT25QU01G MT25QL02G MT25QU02G Two have been tested as indicated, all other variants added are marked untested. Signed-off-by: Jacob Creedon <jcreedon@google.com> Change-Id: I85630e4f6c0aa3b261f9871b7d363dad278b997e Reviewed-on: https://review.coreboot.org/c/flashrom/+/34491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* util/getversion,meson: Add script to allow version info with MesonNico Huber2019-11-062-1/+72
| | | | | | | | | | | | | | | | | | | Add `util/getversion.sh` that retrieves version information from a `versioninfo.inc` (what we use for releases) if present or uses `util/getrevision.sh` if not. Let Meson use it for flashrom's version. It seems Meson doesn't generate the manual page at all, so the `--man-date` command is currently unused. Change-Id: I401e5638509c4a573bc0cb17ebc5fa76df9700b5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/35561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Limonciello <superm1@gmail.com> Reviewed-by: Richard Hughes <hughsient@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* usbdev.c: Add missing <inttypes.h> includeEdward O'Callaghan2019-10-221-0/+1
| | | | | | | | Change-Id: Ie23612226a48d6732750f51547642da0a6257dd8 Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* cli_classic: Tidy up some repeated handling patterns into funcsEdward O'Callaghan2019-10-171-131/+64
| | | | | | | | | | | | | | | | | | | | Introduce cli_classic_single_operation() to consolidate the repeating pattern of multiple CLI operations at once. Also modify cli_classic_abort_usage() to take an optional error abort string and print it to stderr, this allows for trimming a few more lines off the cli implementation. V.2: A few fixes upon review: - Trim off some unnecessary braces for single line branches. - Pass 'operation_specified' by reference. - Rename a function. V.3: Fix print order of cli_classic_abort_usage(). Change-Id: I54598efdaee2b95cb278b0f2aac05f48bbd95bef Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/35611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* cli_classic: Fix first line of --help to match manpageEdward O'Callaghan2019-10-171-3/+6
| | | | | | | | | | | | Make the first line of --help in usage to align with the format of the man page, including fixing any missing options. V.2: Add an extra space. Change-Id: I44f82c6a54fddb54bf268fe6eb22e50acb6025cf Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/35793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Correct the pkgconfig generated file namingMario Limonciello2019-10-161-3/+3
| | | | | | | | | | | | The typical convention is to not use the `lib` prefix (ie `libfoo`) but instead to just use foo. Change-Id: I5ab46418e2a1708d5c11970f1e56250f2adb7d70 Signed-off-by: Mario Limonciello <mario.limonciello@dell.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Hughes <richard@hughsie.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* meson.build: Sanitize the version stringMario Limonciello2019-10-161-1/+10
| | | | | | | | | | | Match strictly the library version, and remove all starting letters. Change-Id: I25587ed2ad7fbcffdf14eb758c1f0d6ab2aea545 Signed-off-by: Mario Limonciello <mario.limonciello@dell.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/35566 Tested-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Richard Hughes <richard@hughsie.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* linux_spi: reorder includes for linux <4.14Fabrice Fontaine2019-10-161-2/+7
| | | | | | | | | | | | | | This works around a missing header in spidev.h present in older versions of Linux. Patch is ported from: https://git.buildroot.net/buildroot/tree/package/flashrom/0001-spi.patch Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com> Signed-off-by: David Hendricks <david.hendricks@gmail.com> Change-Id: Ieab60f59bc63aca0dc4867f31699dab4167da05b Reviewed-on: https://review.coreboot.org/c/flashrom/+/35830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* util/git-hooks: Check for Signed-off-by lineDavid Hendricks2019-10-141-0/+11
| | | | | | | | | | | Enforce the DCO. The logic comes from coreboot's commit-msg hook, and I've added a pointer to flashrom's development guidelines. Change-Id: Iea49a06c2d4824be073eff98c8aae1cbc5b145e4 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/35295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix compilation if CONFIG_INTERNAL=noJonathan Liu2019-10-082-0/+10
| | | | | | | | | Change-Id: Id9e07332003832465a0eccf1d89e73d15abb35c0 Signed-off-by: Jonathan Liu <net147@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/35808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable.c: Mark Intel Q75 as DEPAngel Pons2019-10-081-1/+1
| | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using an HP Pro 6300 SFF mainboard with an Intel Q75 PCH. However, since ME-enabled chipsets are marked as DEP instead of OK, this one shall also be. Change-Id: I273af0eb33e74b31bc4fdc95362527bba080c5a0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/35826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Makefile,meson.build: Enable/assume -WextraNico Huber2019-10-052-3/+1
| | | | | | | | | | | | Enable all -Wextra warnings but -Wunused-parameter. Nobody seems to miss warnings about unused parameters and we have a lot unavoidable occurrences in flashrom because of common interfaces. Change-Id: Id2ece264c2d483e34019985dd3a7631c4889abe6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
* flashchips: Add missing block erasers for GD25Q256DNico Huber2019-10-051-0/+9
| | | | | | | | Change-Id: I7e49e468c7f1eaf0ddd5fc08d6cc6569274faf94 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/35798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* board_enable: Work around -Wtype-limits issueNico Huber2019-10-051-1/+1
| | | | | | | | | | | | | In case of an empty `board_matches` list (i.e. on non-x86), we checked if the `unsigned i` is smaller 0. Shuffling the computation avoids that problem. Change-Id: I636d73c920a7b7e7507eafe444bab8236d7acb67 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/35801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Fix more sign-compare issuesNico Huber2019-10-054-4/+4
| | | | | | | | | | | | | The one in the `dummyflasher` is a little peculiar. We actually never knew the type of the `st_size` field in `struct stat`. It happens to be `signed` in some systems (e.g. DJGPP). Change-Id: If36ba22606021400b385ea6083eacc7b360c20c5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/35800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* meson: Correct license to GPL-2.0Nico Huber2019-10-051-1/+1
| | | | | | | | | | | Parts of flashrom are 2.0+ but some are not. As Meson's purpose is to link these together, it should advertise only GPL-2.0 for the whole. Change-Id: Iab99c74f5f9d54dac56085ecc7475b14be00a310 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/35584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* meson: Add spi95.c to fix the buildDavid Hendricks2019-10-051-0/+1
| | | | | | | | | | Reported in issue #105 on github. Change-Id: Ibe484b4ef60533135fa1e96eb203bb55985d1f8e Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/35819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Add support for M95M02-A125Konstantin Grudnev2019-10-046-1/+111
| | | | | | | | | | | | Automotive 2 Mbit (256KiB) serial SPI bus EEPROM PREW tested successfully with use of ch341a programmer on Linux host 5.2.0-1-MANJARO x86_64 Signed-off-by: Konstantin Grudnev <grudnevkv@gmail.com> Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b Reviewed-on: https://review.coreboot.org/c/flashrom/+/34496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* tree: Enable -Wwrite-stringsJacob Garber2019-10-047-7/+8
| | | | | | | | | | | | | | | | When compiling, this warning gives string literals the type const char[] to help catch accidental modification (which is undefined behaviour). There currently aren't any instances of this in flashrom, so let's enable this warning to keep it that way. This requires adding const qualifiers to the declarations of several variables that work with string literals. Change-Id: I62d9bc194938a0c9a0e4cdff7ced8ea2e14cc1bc Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-20 06:44:41 +0000