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Diffstat (limited to 'flashrom.8.tmpl')
| -rw-r--r-- | flashrom.8.tmpl | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 0f7bc974..58f5ec0c 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -820,6 +820,21 @@ is a hexadecimal value of up to 24 bits. For example, 0x332211 assigns 0x11 to SR1, 0x22 to SR2 and 0x33 to SR3. Shorter value is padded to 24 bits with zeroes on the left. See datasheet for chosen chip for details about the registers content. +.sp +.TP +.B Write protection +.sp +Chips with emulated WP: W25Q128FV. +.sp +You can simulate state of hardware protection pin (WP) with the +.sp +.B " flashrom -p dummy:hwwp=state" +.sp +syntax where +.B state +is "yes" or "no" (default value). "yes" means active state of the pin implies +that chip is write-protected (on real hardware the pin is usually negated, but +not here). .SS .BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ |