diff options
Diffstat (limited to 'chipset_enable.c')
| -rw-r--r-- | chipset_enable.c | 484 |
1 files changed, 309 insertions, 175 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 84e4b6b5..9d3df5f8 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -26,6 +26,7 @@ #define _LARGEFILE64_SOURCE +#include <stdbool.h> #include <stdlib.h> #include <string.h> #include <unistd.h> @@ -33,13 +34,17 @@ #include <errno.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" +#include "hwaccess_physmap.h" +#include "platform/pci.h" #define NOT_DONE_YET 1 #if defined(__i386__) || defined(__x86_64__) -static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) +#include "hwaccess_x86_io.h" +#include "hwaccess_x86_msr.h" + +static int enable_flash_ali_m1533(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { uint8_t tmp; @@ -54,7 +59,7 @@ static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) return 0; } -static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name) +static int enable_flash_rdc_r8610(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { uint8_t tmp; @@ -80,7 +85,7 @@ static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name) return 0; } -static int enable_flash_sis85c496(struct pci_dev *dev, const char *name) +static int enable_flash_sis85c496(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { uint8_t tmp; @@ -91,7 +96,7 @@ static int enable_flash_sis85c496(struct pci_dev *dev, const char *name) return 0; } -static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name) +static int enable_flash_sis_mapping(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { #define SIS_MAPREG 0x40 uint8_t new, newer; @@ -116,11 +121,11 @@ static struct pci_dev *find_southbridge(uint16_t vendor, const char *name) { struct pci_dev *sbdev; - sbdev = pci_dev_find_vendorclass(vendor, 0x0601); + sbdev = pcidev_find_vendorclass(vendor, 0x0601); if (!sbdev) - sbdev = pci_dev_find_vendorclass(vendor, 0x0680); + sbdev = pcidev_find_vendorclass(vendor, 0x0680); if (!sbdev) - sbdev = pci_dev_find_vendorclass(vendor, 0x0000); + sbdev = pcidev_find_vendorclass(vendor, 0x0000); if (!sbdev) msg_perr("No southbridge found for %s!\n", name); if (sbdev) @@ -130,7 +135,7 @@ static struct pci_dev *find_southbridge(uint16_t vendor, const char *name) return sbdev; } -static int enable_flash_sis501(struct pci_dev *dev, const char *name) +static int enable_flash_sis501(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { uint8_t tmp; int ret = 0; @@ -140,7 +145,7 @@ static int enable_flash_sis501(struct pci_dev *dev, const char *name) if (!sbdev) return -1; - ret = enable_flash_sis_mapping(sbdev, name); + ret = enable_flash_sis_mapping(cfg, sbdev, name); tmp = sio_read(0x22, 0x80); tmp &= (~0x20); @@ -155,7 +160,7 @@ static int enable_flash_sis501(struct pci_dev *dev, const char *name) return ret; } -static int enable_flash_sis5511(struct pci_dev *dev, const char *name) +static int enable_flash_sis5511(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { uint8_t tmp; int ret = 0; @@ -165,7 +170,7 @@ static int enable_flash_sis5511(struct pci_dev *dev, const char *name) if (!sbdev) return -1; - ret = enable_flash_sis_mapping(sbdev, name); + ret = enable_flash_sis_mapping(cfg, sbdev, name); tmp = sio_read(0x22, 0x50); tmp &= (~0x20); @@ -175,7 +180,7 @@ static int enable_flash_sis5511(struct pci_dev *dev, const char *name) return ret; } -static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t dis_mask, uint8_t en_mask) +static int enable_flash_sis5x0(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, uint8_t dis_mask, uint8_t en_mask) { #define SIS_REG 0x45 uint8_t new, newer; @@ -186,7 +191,7 @@ static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t di if (!sbdev) return -1; - ret = enable_flash_sis_mapping(sbdev, name); + ret = enable_flash_sis_mapping(cfg, sbdev, name); new = pci_read_byte(sbdev, SIS_REG); new &= (~dis_mask); @@ -202,14 +207,14 @@ static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t di return ret; } -static int enable_flash_sis530(struct pci_dev *dev, const char *name) +static int enable_flash_sis530(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_sis5x0(dev, name, 0x20, 0x04); + return enable_flash_sis5x0(cfg, dev, name, 0x20, 0x04); } -static int enable_flash_sis540(struct pci_dev *dev, const char *name) +static int enable_flash_sis540(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_sis5x0(dev, name, 0x80, 0x40); + return enable_flash_sis5x0(cfg, dev, name, 0x80, 0x40); } /* Datasheet: @@ -218,7 +223,7 @@ static int enable_flash_sis540(struct pci_dev *dev, const char *name) * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf * - Order Number: 290562-001 */ -static int enable_flash_piix4(struct pci_dev *dev, const char *name) +static int enable_flash_piix4(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { uint16_t old, new; uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ @@ -270,7 +275,7 @@ static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, vo switch (ich_generation) { case CHIPSET_ICH_UNKNOWN: - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; /* Non-SPI-capable */ case CHIPSET_ICH: case CHIPSET_ICH2345: @@ -354,7 +359,7 @@ static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, vo msg_pwarn("Warning: BIOS region SMM protection is enabled!\n"); if (new != wanted) - msg_pwarn("Warning: Setting Bios Control at 0x%x from 0x%02x to 0x%02x failed.\n" + msg_pwarn("Warning: Setting BIOS Control at 0x%x from 0x%02x to 0x%02x failed.\n" "New value is 0x%02x.\n", bios_cntl, old, wanted, new); /* Return an error if we could not set the write enable only. */ @@ -375,7 +380,7 @@ static int enable_flash_ich_bios_cntl_memmapped(enum ich_chipset ich_generation, return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0); } -static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich_generation) +static int enable_flash_ich_fwh_decode(const struct programmer_cfg *cfg, struct pci_dev *dev, enum ich_chipset ich_generation) { uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */ bool implemented = 0; @@ -404,7 +409,7 @@ static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */ if (ilb_base == 0) { msg_perr("Error: Invalid ILB_BASE_ADDRESS\n"); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } ilb = rphysmap("BYT IBASE", ilb_base, 512); fwh_sel1 = 0x18; @@ -424,7 +429,7 @@ static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich break; } - char *idsel = extract_programmer_param("fwh_idsel"); + char *idsel = extract_programmer_param_str(cfg, "fwh_idsel"); if (idsel && strlen(idsel)) { if (!implemented) { msg_perr("Error: fwh_idsel= specified, but (yet) unsupported on this chipset.\n"); @@ -463,7 +468,7 @@ static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich msg_perr("Error: fwh_idsel= specified, but no value given.\n"); idsel_garbage_out: free(idsel); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } free(idsel); @@ -545,41 +550,41 @@ idsel_garbage_out: } } max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); - msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh); + msg_pdbg("Maximum FWH chip size: 0x%"PRIx32" bytes\n", max_rom_decode.fwh); return 0; } -static int enable_flash_ich_fwh(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) +static int enable_flash_ich_fwh(const struct programmer_cfg *cfg, struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) { int err; /* Configure FWH IDSEL decoder maps. */ - if ((err = enable_flash_ich_fwh_decode(dev, ich_generation)) != 0) + if ((err = enable_flash_ich_fwh_decode(cfg, dev, ich_generation)) != 0) return err; internal_buses_supported &= BUS_FWH; return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl); } -static int enable_flash_ich0(struct pci_dev *dev, const char *name) +static int enable_flash_ich0(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_fwh(dev, CHIPSET_ICH, 0x4e); + return enable_flash_ich_fwh(cfg, dev, CHIPSET_ICH, 0x4e); } -static int enable_flash_ich2345(struct pci_dev *dev, const char *name) +static int enable_flash_ich2345(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_fwh(dev, CHIPSET_ICH2345, 0x4e); + return enable_flash_ich_fwh(cfg, dev, CHIPSET_ICH2345, 0x4e); } -static int enable_flash_ich6(struct pci_dev *dev, const char *name) +static int enable_flash_ich6(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_fwh(dev, CHIPSET_ICH6, 0xdc); + return enable_flash_ich_fwh(cfg, dev, CHIPSET_ICH6, 0xdc); } -static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) +static int enable_flash_poulsbo(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8); + return enable_flash_ich_fwh(cfg, dev, CHIPSET_POULSBO, 0xd8); } static enum chipbustype enable_flash_ich_report_gcs( @@ -599,7 +604,14 @@ static enum chipbustype enable_flash_ich_report_gcs( case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: + case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: + case CHIPSET_ELKHART_LAKE: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: reg_name = "BIOS_SPI_BC"; gcs = pci_read_long(dev, 0xdc); bild = (gcs >> 7) & 1; @@ -613,7 +625,7 @@ static enum chipbustype enable_flash_ich_report_gcs( break; } - msg_pdbg("%s = 0x%x: ", reg_name, gcs); + msg_pdbg("%s = 0x%"PRIx32": ", reg_name, gcs); msg_pdbg("BIOS Interface Lock-Down: %sabled, ", bild ? "en" : "dis"); struct boot_straps { @@ -651,6 +663,9 @@ static enum chipbustype enable_flash_ich_report_gcs( static const struct boot_straps boot_straps_pch8_lp[] = { { "SPI", BUS_SPI }, { "LPC", BUS_LPC | BUS_FWH } }; + static const struct boot_straps boot_straps_pch500[] = + { { "SPI", BUS_SPI }, + { "eSPI", BUS_NONE } }; static const struct boot_straps boot_straps_apl[] = { { "SPI", BUS_SPI }, { "reserved", BUS_NONE } }; @@ -694,9 +709,18 @@ static enum chipbustype enable_flash_ich_report_gcs( case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: boot_straps = boot_straps_pch8_lp; break; + case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: + boot_straps = boot_straps_pch500; + break; case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: + case CHIPSET_ELKHART_LAKE: boot_straps = boot_straps_apl; break; case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet @@ -722,7 +746,14 @@ static enum chipbustype enable_flash_ich_report_gcs( case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: + case CHIPSET_500_SERIES_TIGER_POINT: + case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: + case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: + case CHIPSET_ELKHART_LAKE: bbs = (gcs >> 6) & 0x1; break; default: @@ -739,30 +770,38 @@ static enum chipbustype enable_flash_ich_report_gcs( return boot_straps[bbs].bus; } -static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) +static int enable_flash_ich_spi(const struct programmer_cfg *cfg, struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) { /* Get physical address of Root Complex Register Block */ uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000; - msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra); + msg_pdbg("Root Complex Register Block address = 0x%"PRIx32"\n", rcra); /* Map RCBA to virtual memory */ void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000); if (rcrb == ERROR_PTR) - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb); /* Handle FWH-related parameters and initialization */ - int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl); - if (ret_fwh == ERROR_FATAL) + int ret_fwh = enable_flash_ich_fwh(cfg, dev, ich_generation, bios_cntl); + if (ret_fwh == ERROR_FLASHROM_FATAL) return ret_fwh; + /* + * It seems that the ICH7 does not support SPI and LPC chips at the same time. When booted + * from LPC, the SCIP bit will never clear, which causes long delays and many error messages. + * To avoid this, we will not enable SPI on ICH7 when the southbridge is strapped to LPC. + */ + if (ich_generation == CHIPSET_ICH7 && (boot_buses & BUS_LPC)) + return 0; + /* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */ uint16_t spibar_offset; switch (ich_generation) { case CHIPSET_BAYTRAIL: case CHIPSET_ICH_UNKNOWN: - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; case CHIPSET_ICH7: case CHIPSET_ICH8: case CHIPSET_TUNNEL_CREEK: @@ -778,96 +817,96 @@ static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_genera void *spibar = rcrb + spibar_offset; /* This adds BUS_SPI */ - int ret_spi = ich_init_spi(spibar, ich_generation); - if (ret_spi == ERROR_FATAL) + int ret_spi = ich_init_spi(cfg, spibar, ich_generation); + if (ret_spi == ERROR_FLASHROM_FATAL) return ret_spi; if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi)) - return ERROR_NONFATAL; + return ERROR_FLASHROM_NONFATAL; /* Suppress unknown laptop warning if we booted from SPI. */ if (boot_buses & BUS_SPI) - laptop_ok = 1; + cfg->bcfg->laptop_ok = true; return 0; } -static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name) +static int enable_flash_tunnelcreek(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_spi(dev, CHIPSET_TUNNEL_CREEK, 0xd8); + return enable_flash_ich_spi(cfg, dev, CHIPSET_TUNNEL_CREEK, 0xd8); } -static int enable_flash_s12x0(struct pci_dev *dev, const char *name) +static int enable_flash_s12x0(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_spi(dev, CHIPSET_CENTERTON, 0xd8); + return enable_flash_ich_spi(cfg, dev, CHIPSET_CENTERTON, 0xd8); } -static int enable_flash_ich7(struct pci_dev *dev, const char *name) +static int enable_flash_ich7(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_spi(dev, CHIPSET_ICH7, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH7, 0xdc); } -static int enable_flash_ich8(struct pci_dev *dev, const char *name) +static int enable_flash_ich8(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_spi(dev, CHIPSET_ICH8, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH8, 0xdc); } -static int enable_flash_ich9(struct pci_dev *dev, const char *name) +static int enable_flash_ich9(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_spi(dev, CHIPSET_ICH9, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH9, 0xdc); } -static int enable_flash_ich10(struct pci_dev *dev, const char *name) +static int enable_flash_ich10(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_spi(dev, CHIPSET_ICH10, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH10, 0xdc); } /* Ibex Peak aka. 5 series & 3400 series */ -static int enable_flash_pch5(struct pci_dev *dev, const char *name) +static int enable_flash_pch5(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_spi(dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc); } /* Cougar Point aka. 6 series & c200 series */ -static int enable_flash_pch6(struct pci_dev *dev, const char *name) +static int enable_flash_pch6(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_spi(dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc); } /* Panther Point aka. 7 series */ -static int enable_flash_pch7(struct pci_dev *dev, const char *name) +static int enable_flash_pch7(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_spi(dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc); } /* Lynx Point aka. 8 series */ -static int enable_flash_pch8(struct pci_dev *dev, const char *name) +static int enable_flash_pch8(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc); } /* Lynx Point LP aka. 8 series low-power */ -static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name) +static int enable_flash_pch8_lp(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc); } /* Wellsburg (for Haswell-EP Xeons) */ -static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name) +static int enable_flash_pch8_wb(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc); } /* Wildcat Point */ -static int enable_flash_pch9(struct pci_dev *dev, const char *name) +static int enable_flash_pch9(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc); } /* Wildcat Point LP */ -static int enable_flash_pch9_lp(struct pci_dev *dev, const char *name) +static int enable_flash_pch9_lp(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc); } /* Sunrise Point */ @@ -877,11 +916,11 @@ static int enable_flash_pch100_shutdown(void *const pci_acc) return 0; } -static int enable_flash_pch100_or_c620( +static int enable_flash_pch100_or_c620(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, const int slot, const int func, const enum ich_chipset pch_generation) { - int ret = ERROR_FATAL; + int ret = ERROR_FLASHROM_FATAL; /* * The SPI PCI device is usually hidden (by hiding PCI vendor @@ -912,27 +951,27 @@ static int enable_flash_pch100_or_c620( const enum chipbustype boot_buses = enable_flash_ich_report_gcs(spi_dev, pch_generation, NULL); const int ret_bc = enable_flash_ich_bios_cntl_config_space(spi_dev, pch_generation, 0xdc); - if (ret_bc == ERROR_FATAL) + if (ret_bc == ERROR_FLASHROM_FATAL) goto _freepci_ret; const uint32_t phys_spibar = pci_read_long(spi_dev, PCI_BASE_ADDRESS_0) & 0xfffff000; void *const spibar = rphysmap("SPIBAR", phys_spibar, 0x1000); if (spibar == ERROR_PTR) goto _freepci_ret; - msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " (phys = 0x%08x)\n", PRIxPTR_WIDTH, (uintptr_t)spibar, phys_spibar); + msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " (phys = 0x%08"PRIx32")\n", PRIxPTR_WIDTH, (uintptr_t)spibar, phys_spibar); /* This adds BUS_SPI */ - const int ret_spi = ich_init_spi(spibar, pch_generation); - if (ret_spi != ERROR_FATAL) { + const int ret_spi = ich_init_spi(cfg, spibar, pch_generation); + if (ret_spi != ERROR_FLASHROM_FATAL) { if (ret_bc || ret_spi) - ret = ERROR_NONFATAL; + ret = ERROR_FLASHROM_NONFATAL; else ret = 0; } /* Suppress unknown laptop warning if we booted from SPI. */ if (!ret && (boot_buses & BUS_SPI)) - laptop_ok = 1; + cfg->bcfg->laptop_ok = true; _freepci_ret: pci_free_dev(spi_dev); @@ -940,24 +979,59 @@ _freepci_ret: return ret; } -static int enable_flash_pch100(struct pci_dev *const dev, const char *const name) +static int enable_flash_pch100(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_100_SERIES_SUNRISE_POINT); +} + +static int enable_flash_c620(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG); +} + +static int enable_flash_pch300(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT); +} + +static int enable_flash_pch400(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_400_SERIES_COMET_POINT); +} + +static int enable_flash_pch500(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) { - return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_100_SERIES_SUNRISE_POINT); + return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_500_SERIES_TIGER_POINT); } -static int enable_flash_c620(struct pci_dev *const dev, const char *const name) +static int enable_flash_pch600(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) { - return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG); + return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_600_SERIES_ALDER_POINT); } -static int enable_flash_pch300(struct pci_dev *const dev, const char *const name) +static int enable_flash_mtl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) { - return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT); + return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_METEOR_LAKE); } -static int enable_flash_apl(struct pci_dev *const dev, const char *const name) +static int enable_flash_mcc(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) { - return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); + return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE); +} + +static int enable_flash_jsl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_JASPER_LAKE); +} + +static int enable_flash_apl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(cfg, dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); +} + +static int enable_flash_glk(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(cfg, dev, name, 0x0d, 2, CHIPSET_GEMINI_LAKE); } /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. @@ -970,51 +1044,55 @@ static int enable_flash_apl(struct pci_dev *const dev, const char *const name) * - SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800). * - BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC). */ -static int enable_flash_silvermont(struct pci_dev *dev, const char *name) +static int enable_flash_silvermont(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { enum ich_chipset ich_generation = CHIPSET_BAYTRAIL; /* Get physical address of Root Complex Register Block */ uint32_t rcba = pci_read_long(dev, 0xf0) & 0xfffffc00; - msg_pdbg("Root Complex Register Block address = 0x%x\n", rcba); + msg_pdbg("Root Complex Register Block address = 0x%"PRIx32"\n", rcba); /* Handle GCS (in RCRB) */ void *rcrb = physmap("BYT RCRB", rcba, 4); + if (rcrb == ERROR_PTR) + return ERROR_FLASHROM_FATAL; const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb); physunmap(rcrb, 4); /* Handle fwh_idsel parameter */ - int ret_fwh = enable_flash_ich_fwh_decode(dev, ich_generation); - if (ret_fwh == ERROR_FATAL) + int ret_fwh = enable_flash_ich_fwh_decode(cfg, dev, ich_generation); + if (ret_fwh == ERROR_FLASHROM_FATAL) return ret_fwh; internal_buses_supported &= BUS_FWH; /* Get physical address of SPI Base Address and map it */ uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00; - msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase); + msg_pdbg("SPI_BASE_ADDRESS = 0x%"PRIx32"\n", sbase); void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */ + if (spibar == ERROR_PTR) + return ERROR_FLASHROM_FATAL; /* Enable Flash Writes. * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C). */ enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC); - int ret_spi = ich_init_spi(spibar, ich_generation); - if (ret_spi == ERROR_FATAL) + int ret_spi = ich_init_spi(cfg, spibar, ich_generation); + if (ret_spi == ERROR_FLASHROM_FATAL) return ret_spi; if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi)) - return ERROR_NONFATAL; + return ERROR_FLASHROM_NONFATAL; /* Suppress unknown laptop warning if we booted from SPI. */ if (boot_buses & BUS_SPI) - laptop_ok = 1; + cfg->bcfg->laptop_ok = true; return 0; } -static int via_no_byte_merge(struct pci_dev *dev, const char *name) +static int via_no_byte_merge(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { uint8_t val; @@ -1027,7 +1105,7 @@ static int via_no_byte_merge(struct pci_dev *dev, const char *name) return NOT_DONE_YET; /* need to find south bridge, too */ } -static int enable_flash_vt823x(struct pci_dev *dev, const char *name) +static int enable_flash_vt823x(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { uint8_t val; @@ -1054,18 +1132,18 @@ static int enable_flash_vt823x(struct pci_dev *dev, const char *name) return 0; } -static int enable_flash_vt_vx(struct pci_dev *dev, const char *name) +static int enable_flash_vt_vx(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { - struct pci_dev *south_north = pci_dev_find(0x1106, 0xa353); + struct pci_dev *south_north = pcidev_find(0x1106, 0xa353); if (south_north == NULL) { msg_perr("Could not find South-North Module Interface Control device!\n"); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } msg_pdbg("Strapped to "); if ((pci_read_byte(south_north, 0x56) & 0x01) == 0) { msg_pdbg("LPC.\n"); - return enable_flash_vt823x(dev, name); + return enable_flash_vt823x(cfg, dev, name); } msg_pdbg("SPI.\n"); @@ -1079,7 +1157,7 @@ static int enable_flash_vt_vx(struct pci_dev *dev, const char *name) spi0_mm_base = pci_read_long(dev, 0xbc) << 8; if (spi0_mm_base == 0x0) { msg_pdbg ("MMIO not enabled!\n"); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } break; case 0x8409: /* VX855/VX875 */ @@ -1087,18 +1165,18 @@ static int enable_flash_vt_vx(struct pci_dev *dev, const char *name) mmio_base = pci_read_long(dev, 0xbc) << 8; if (mmio_base == 0x0) { msg_pdbg ("MMIO not enabled!\n"); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN); if (mmio_base_physmapped == ERROR_PTR) - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; /* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */ spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00; if ((spi_cntl & 0x01) == 0) { msg_pdbg ("SPI Bus0 disabled!\n"); physunmap(mmio_base_physmapped, SPI_CNTL_LEN); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } /* Offset 1-3 has SPI Bus Memory Map Base Address: */ spi0_mm_base = spi_cntl & 0xFFFFFF00; @@ -1112,18 +1190,18 @@ static int enable_flash_vt_vx(struct pci_dev *dev, const char *name) break; default: msg_perr("%s: Unsupported chipset %x:%x!\n", __func__, dev->vendor_id, dev->device_id); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } return via_init_spi(spi0_mm_base); } -static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) +static int enable_flash_vt8237s_spi(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { return via_init_spi(pci_read_long(dev, 0xbc) << 8); } -static int enable_flash_cs5530(struct pci_dev *dev, const char *name) +static int enable_flash_cs5530(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { uint8_t reg8; @@ -1187,7 +1265,7 @@ static int enable_flash_cs5530(struct pci_dev *dev, const char *name) * To enable write to NOR Boot flash for the benefit of systems that have such * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select). */ -static int enable_flash_cs5536(struct pci_dev *dev, const char *name) +static int enable_flash_cs5536(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { #define MSR_RCONF_DEFAULT 0x1808 #define MSR_NORF_CTL 0x51400018 @@ -1195,28 +1273,28 @@ static int enable_flash_cs5536(struct pci_dev *dev, const char *name) msr_t msr; /* Geode only has a single core */ - if (setup_cpu_msr(0)) + if (msr_setup(0)) return -1; - msr = rdmsr(MSR_RCONF_DEFAULT); + msr = msr_read(MSR_RCONF_DEFAULT); if ((msr.hi >> 24) != 0x22) { msr.hi &= 0xfbffffff; - wrmsr(MSR_RCONF_DEFAULT, msr); + msr_write(MSR_RCONF_DEFAULT, msr); } - msr = rdmsr(MSR_NORF_CTL); + msr = msr_read(MSR_NORF_CTL); /* Raise WE_CS3 bit. */ msr.lo |= 0x08; - wrmsr(MSR_NORF_CTL, msr); + msr_write(MSR_NORF_CTL, msr); - cleanup_cpu_msr(); + msr_cleanup(); #undef MSR_RCONF_DEFAULT #undef MSR_NORF_CTL return 0; } -static int enable_flash_sc1100(struct pci_dev *dev, const char *name) +static int enable_flash_sc1100(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { #define SC_REG 0x52 uint8_t new; @@ -1241,7 +1319,7 @@ static int enable_flash_sc1100(struct pci_dev *dev, const char *name) * 6 FFB0_0000h–FFBF_FFFFh <- FFF80000h-FFFDFFFFh <- <- * 5 00E8... <- <- FFF00000h-FFF7FFFFh <- */ -static int enable_flash_amd_via(struct pci_dev *dev, const char *name, uint8_t decode_val) +static int enable_flash_amd_via(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, uint8_t decode_val) { #define AMD_MAPREG 0x43 #define AMD_ENREG 0x40 @@ -1268,36 +1346,36 @@ static int enable_flash_amd_via(struct pci_dev *dev, const char *name, uint8_t d if (pci_read_byte(dev, AMD_ENREG) != new) { msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", AMD_ENREG, new, name); - return ERROR_NONFATAL; + return ERROR_FLASHROM_NONFATAL; } msg_pdbg2("Set ROM enable bit successfully.\n"); return 0; } -static int enable_flash_amd_768_8111(struct pci_dev *dev, const char *name) +static int enable_flash_amd_768_8111(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { /* Enable decoding of 0xFFB00000 to 0xFFFFFFFF (5 MB). */ max_rom_decode.lpc = 5 * 1024 * 1024; - return enable_flash_amd_via(dev, name, 0xC0); + return enable_flash_amd_via(cfg, dev, name, 0xC0); } -static int enable_flash_vt82c586(struct pci_dev *dev, const char *name) +static int enable_flash_vt82c586(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { /* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (512 kB) */ max_rom_decode.parallel = 512 * 1024; - return enable_flash_amd_via(dev, name, 0xC0); + return enable_flash_amd_via(cfg, dev, name, 0xC0); } /* Works for VT82C686A/B too. */ -static int enable_flash_vt82c596(struct pci_dev *dev, const char *name) +static int enable_flash_vt82c596(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { /* Enable decoding of 0xFFF00000 to 0xFFFFFFFF. (1 MB) */ max_rom_decode.parallel = 1024 * 1024; - return enable_flash_amd_via(dev, name, 0xE0); + return enable_flash_amd_via(cfg, dev, name, 0xE0); } -static int enable_flash_sb600(struct pci_dev *dev, const char *name) +static int enable_flash_sb600(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { uint32_t prot; uint8_t reg; @@ -1309,7 +1387,7 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) /* No protection flags for this region?*/ if ((prot & 0x3) == 0) continue; - msg_pdbg("Chipset %s%sprotected flash from 0x%08x to 0x%08x, unlocking...", + msg_pdbg("Chipset %s%sprotected flash from 0x%08"PRIx32" to 0x%08"PRIx32", unlocking...", (prot & 0x2) ? "read " : "", (prot & 0x1) ? "write " : "", (prot & 0xfffff800), @@ -1318,7 +1396,7 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) rpci_write_byte(dev, reg, prot); prot = pci_read_long(dev, reg); if ((prot & 0x3) != 0) { - msg_perr("Disabling %s%sprotection of flash addresses from 0x%08x to 0x%08x failed.\n", + msg_perr("Disabling %s%sprotection of flash addresses from 0x%08"PRIx32" to 0x%08"PRIx32" failed.\n", (prot & 0x2) ? "read " : "", (prot & 0x1) ? "write " : "", (prot & 0xfffff800), @@ -1330,7 +1408,7 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) internal_buses_supported &= BUS_LPC | BUS_FWH; - ret = sb600_probe_spi(dev); + ret = sb600_probe_spi(cfg, dev); /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); @@ -1371,7 +1449,7 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) } /* sets bit 0 in 0x6d */ -static int enable_flash_nvidia_common(struct pci_dev *dev, const char *name) +static int enable_flash_nvidia_common(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { uint8_t old, new; @@ -1388,16 +1466,16 @@ static int enable_flash_nvidia_common(struct pci_dev *dev, const char *name) return 0; } -static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) +static int enable_flash_nvidia_nforce2(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { rpci_write_byte(dev, 0x92, 0); - if (enable_flash_nvidia_common(dev, name)) - return ERROR_NONFATAL; + if (enable_flash_nvidia_common(cfg, dev, name)) + return ERROR_FLASHROM_NONFATAL; else return 0; } -static int enable_flash_ck804(struct pci_dev *dev, const char *name) +static int enable_flash_ck804(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { uint32_t segctrl; uint8_t reg, old, new; @@ -1416,7 +1494,7 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name) segctrl = pci_read_byte(dev, reg); if ((segctrl & 0x3) != 0x0) { - msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%x).\n", + msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%"PRIx32").\n", reg, segctrl); err++; } else @@ -1440,7 +1518,7 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name) segctrl = pci_read_long(dev, reg); if ((segctrl & 0x33333333) != 0x00000000) { - msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%08x).\n", + msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%08"PRIx32").\n", reg, segctrl); err++; } else @@ -1449,7 +1527,7 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name) if (err > 0) { msg_pinfo("%d locks could not be disabled, disabling writes (reads may also fail).\n", err); - programmer_may_write = 0; + programmer_may_write = false; } reg = 0x88; @@ -1463,16 +1541,16 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name) } } - if (enable_flash_nvidia_common(dev, name)) + if (enable_flash_nvidia_common(cfg, dev, name)) err++; if (err > 0) - return ERROR_NONFATAL; + return ERROR_FLASHROM_NONFATAL; else return 0; } -static int enable_flash_osb4(struct pci_dev *dev, const char *name) +static int enable_flash_osb4(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { uint8_t tmp; @@ -1490,17 +1568,17 @@ static int enable_flash_osb4(struct pci_dev *dev, const char *name) } /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ -static int enable_flash_sb400(struct pci_dev *dev, const char *name) +static int enable_flash_sb400(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { uint8_t tmp; struct pci_dev *smbusdev; /* Look for the SMBus device. */ - smbusdev = pci_dev_find(0x1002, 0x4372); + smbusdev = pcidev_find(0x1002, 0x4372); if (!smbusdev) { msg_perr("ERROR: SMBus device not found. Aborting.\n"); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } /* Enable some SMBus stuff. */ @@ -1525,7 +1603,7 @@ static int enable_flash_sb400(struct pci_dev *dev, const char *name) return 0; } -static int enable_flash_mcp55(struct pci_dev *dev, const char *name) +static int enable_flash_mcp55(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { uint8_t val; uint16_t wordval; @@ -1541,8 +1619,8 @@ static int enable_flash_mcp55(struct pci_dev *dev, const char *name) wordval |= 0x7fff; /* 16M */ rpci_write_word(dev, 0x90, wordval); - if (enable_flash_nvidia_common(dev, name)) - return ERROR_NONFATAL; + if (enable_flash_nvidia_common(cfg, dev, name)) + return ERROR_FLASHROM_NONFATAL; else return 0; } @@ -1552,7 +1630,7 @@ static int enable_flash_mcp55(struct pci_dev *dev, const char *name) * It is assumed that LPC chips need the MCP55 code and SPI chips need the * code provided in enable_flash_mcp6x_7x_common. */ -static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name) +static int enable_flash_mcp6x_7x(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { int ret = 0, want_spi = 0; uint8_t val; @@ -1564,7 +1642,7 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name) switch ((val >> 5) & 0x3) { case 0x0: - ret = enable_flash_mcp55(dev, name); + ret = enable_flash_mcp55(cfg, dev, name); internal_buses_supported &= BUS_LPC; msg_pdbg("Flash bus type is LPC\n"); break; @@ -1583,7 +1661,7 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name) msg_pinfo("Please send the log files created by \"flashrom -p internal -o logfile\" to\n" "flashrom@flashrom.org with \"your board name: flashrom -V\" as the subject to\n" "help us finish support for your chipset. Thanks.\n"); - return ERROR_NONFATAL; + return ERROR_FLASHROM_NONFATAL; } /* Force enable SPI and disable LPC? Not a good idea. */ @@ -1598,12 +1676,12 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name) /* Suppress unknown laptop warning if we booted from SPI. */ if (!ret && want_spi) - laptop_ok = 1; + cfg->bcfg->laptop_ok = true; return ret; } -static int enable_flash_ht1000(struct pci_dev *dev, const char *name) +static int enable_flash_ht1000(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { uint8_t val; @@ -1626,7 +1704,7 @@ static int enable_flash_ht1000(struct pci_dev *dev, const char *name) * complete flash is mapped somewhere below 1G. The position can be determined * by the BOOTCS PAR register. */ -static int get_flashbase_sc520(struct pci_dev *dev, const char *name) +static int get_flashbase_sc520(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) { int i, bootcs_found = 0; uint32_t parx = 0; @@ -1635,7 +1713,7 @@ static int get_flashbase_sc520(struct pci_dev *dev, const char *name) /* 1. Map MMCR */ mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize()); if (mmcr == ERROR_PTR) - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for * BOOTCS region (PARx[31:29] = 100b)e @@ -1810,8 +1888,8 @@ const struct penable chipset_enables[] = { {0x8086, 0x1c4a, B_FS, DEP, "Intel", "H67", enable_flash_pch6}, {0x8086, 0x1c4b, B_FS, NT, "Intel", "HM67", enable_flash_pch6}, {0x8086, 0x1c4c, B_FS, NT, "Intel", "Q65", enable_flash_pch6}, - {0x8086, 0x1c4d, B_FS, NT, "Intel", "QS67", enable_flash_pch6}, - {0x8086, 0x1c4e, B_FS, NT, "Intel", "Q67", enable_flash_pch6}, + {0x8086, 0x1c4d, B_FS, DEP, "Intel", "QS67", enable_flash_pch6}, + {0x8086, 0x1c4e, B_FS, DEP, "Intel", "Q67", enable_flash_pch6}, {0x8086, 0x1c4f, B_FS, DEP, "Intel", "QM67", enable_flash_pch6}, {0x8086, 0x1c50, B_FS, NT, "Intel", "B65", enable_flash_pch6}, {0x8086, 0x1c52, B_FS, NT, "Intel", "C202", enable_flash_pch6}, @@ -1820,19 +1898,22 @@ const struct penable chipset_enables[] = { {0x8086, 0x1c5c, B_FS, DEP, "Intel", "H61", enable_flash_pch6}, {0x8086, 0x1d40, B_FS, DEP, "Intel", "C60x/X79", enable_flash_pch6}, {0x8086, 0x1d41, B_FS, DEP, "Intel", "C60x/X79", enable_flash_pch6}, + {0x8086, 0x1e41, B_FS, DEP, "Intel", "Desktop Sample", enable_flash_pch7}, + {0x8086, 0x1e42, B_FS, DEP, "Intel", "Mobile Sample", enable_flash_pch7}, + {0x8086, 0x1e43, B_FS, DEP, "Intel", "SFF Sample", enable_flash_pch7}, {0x8086, 0x1e44, B_FS, DEP, "Intel", "Z77", enable_flash_pch7}, {0x8086, 0x1e46, B_FS, NT, "Intel", "Z75", enable_flash_pch7}, - {0x8086, 0x1e47, B_FS, NT, "Intel", "Q77", enable_flash_pch7}, + {0x8086, 0x1e47, B_FS, DEP, "Intel", "Q77", enable_flash_pch7}, {0x8086, 0x1e48, B_FS, DEP, "Intel", "Q75", enable_flash_pch7}, {0x8086, 0x1e49, B_FS, DEP, "Intel", "B75", enable_flash_pch7}, {0x8086, 0x1e4a, B_FS, DEP, "Intel", "H77", enable_flash_pch7}, - {0x8086, 0x1e53, B_FS, NT, "Intel", "C216", enable_flash_pch7}, + {0x8086, 0x1e53, B_FS, DEP, "Intel", "C216", enable_flash_pch7}, {0x8086, 0x1e55, B_FS, DEP, "Intel", "QM77", enable_flash_pch7}, {0x8086, 0x1e56, B_FS, DEP, "Intel", "QS77", enable_flash_pch7}, {0x8086, 0x1e57, B_FS, DEP, "Intel", "HM77", enable_flash_pch7}, {0x8086, 0x1e58, B_FS, NT, "Intel", "UM77", enable_flash_pch7}, {0x8086, 0x1e59, B_FS, DEP, "Intel", "HM76", enable_flash_pch7}, - {0x8086, 0x1e5d, B_FS, NT, "Intel", "HM75", enable_flash_pch7}, + {0x8086, 0x1e5d, B_FS, DEP, "Intel", "HM75", enable_flash_pch7}, {0x8086, 0x1e5e, B_FS, NT, "Intel", "HM70", enable_flash_pch7}, {0x8086, 0x1e5f, B_FS, DEP, "Intel", "NM70", enable_flash_pch7}, {0x8086, 0x1f38, B_FS, DEP, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, @@ -1938,8 +2019,8 @@ const struct penable chipset_enables[] = { {0x8086, 0x8cc1, B_FS, NT, "Intel", "9 Series", enable_flash_pch9}, {0x8086, 0x8cc2, B_FS, NT, "Intel", "9 Series Engineering Sample", enable_flash_pch9}, {0x8086, 0x8cc3, B_FS, NT, "Intel", "9 Series", enable_flash_pch9}, - {0x8086, 0x8cc4, B_FS, NT, "Intel", "Z97", enable_flash_pch9}, - {0x8086, 0x8cc6, B_FS, NT, "Intel", "H97", enable_flash_pch9}, + {0x8086, 0x8cc4, B_FS, DEP, "Intel", "Z97", enable_flash_pch9}, + {0x8086, 0x8cc6, B_FS, DEP, "Intel", "H97", enable_flash_pch9}, {0x8086, 0x8d40, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, {0x8086, 0x8d41, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, {0x8086, 0x8d42, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, @@ -1979,7 +2060,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x9cc1, B_FS, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc2, B_FS, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc3, B_FS, DEP, "Intel", "Broadwell U Premium", enable_flash_pch9_lp}, - {0x8086, 0x9cc5, B_FS, NT, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, + {0x8086, 0x9cc5, B_FS, DEP, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, {0x8086, 0x9cc6, B_FS, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc7, B_FS, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, {0x8086, 0x9cc9, B_FS, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp}, @@ -1987,7 +2068,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x9d41, B_S, NT, "Intel", "Skylake / Kaby Lake Sample", enable_flash_pch100}, {0x8086, 0x9d43, B_S, NT, "Intel", "Skylake U Base", enable_flash_pch100}, {0x8086, 0x9d46, B_S, NT, "Intel", "Skylake Y Premium", enable_flash_pch100}, - {0x8086, 0x9d48, B_S, NT, "Intel", "Skylake U Premium", enable_flash_pch100}, + {0x8086, 0x9d48, B_S, DEP, "Intel", "Skylake U Premium", enable_flash_pch100}, {0x8086, 0x9d4b, B_S, NT, "Intel", "Kaby Lake Y w/ iHDCP2.2 Prem.", enable_flash_pch100}, {0x8086, 0x9d4e, B_S, DEP, "Intel", "Kaby Lake U w/ iHDCP2.2 Prem.", enable_flash_pch100}, {0x8086, 0x9d50, B_S, NT, "Intel", "Kaby Lake U w/ iHDCP2.2 Base", enable_flash_pch100}, @@ -1996,9 +2077,13 @@ const struct penable chipset_enables[] = { {0x8086, 0x9d56, B_S, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100}, {0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100}, {0x8086, 0x9d84, B_S, DEP, "Intel", "Cannon Lake U Premium", enable_flash_pch300}, + {0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400}, + {0x8086, 0x0285, B_S, DEP, "Intel", "Comet Lake U Base", enable_flash_pch400}, + {0x8086, 0xa082, B_S, DEP, "Intel", "Tiger Lake U Premium", enable_flash_pch500}, + {0x8086, 0xa088, B_S, DEP, "Intel", "Tiger Lake UP3", enable_flash_pch500}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, - {0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100}, + {0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100}, {0x8086, 0xa144, B_S, NT, "Intel", "H170", enable_flash_pch100}, {0x8086, 0xa145, B_S, NT, "Intel", "Z170", enable_flash_pch100}, {0x8086, 0xa146, B_S, NT, "Intel", "Q170", enable_flash_pch100}, @@ -2015,6 +2100,8 @@ const struct penable chipset_enables[] = { {0x8086, 0xa153, B_S, NT, "Intel", "QM175", enable_flash_pch100}, {0x8086, 0xa154, B_S, NT, "Intel", "CM238", enable_flash_pch100}, {0x8086, 0xa155, B_S, NT, "Intel", "QMU185", enable_flash_pch100}, + {0x8086, 0xa1a4, B_S, DEP, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1c0, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c1, B_S, NT, "Intel", "C621 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c2, B_S, NT, "Intel", "C622 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c3, B_S, NT, "Intel", "C624 Series Chipset (QS/PRQ)", enable_flash_c620}, @@ -2022,36 +2109,83 @@ const struct penable chipset_enables[] = { {0x8086, 0xa1c5, B_S, NT, "Intel", "C626 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c6, B_S, NT, "Intel", "C627 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c7, B_S, NT, "Intel", "C628 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1c8, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1c9, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1ca, B_S, NT, "Intel", "C629 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1cb, B_S, NT, "Intel", "C621A Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1cc, B_S, NT, "Intel", "C627A Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1cd, B_S, NT, "Intel", "C629A Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa240, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, + {0x8086, 0xa241, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa242, B_S, NT, "Intel", "C624 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa243, B_S, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa244, B_S, NT, "Intel", "C621 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa245, B_S, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa246, B_S, NT, "Intel", "C628 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa247, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, + {0x8086, 0xa248, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, + {0x8086, 0xa249, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, + {0x8086, 0x1bca, B_S, NT, "Intel", "Emmitsburg Chipset SKU", enable_flash_c620}, {0x8086, 0xa2c4, B_S, NT, "Intel", "H270", enable_flash_pch100}, {0x8086, 0xa2c5, B_S, NT, "Intel", "Z270", enable_flash_pch100}, {0x8086, 0xa2c6, B_S, NT, "Intel", "Q270", enable_flash_pch100}, {0x8086, 0xa2c7, B_S, NT, "Intel", "Q250", enable_flash_pch100}, {0x8086, 0xa2c8, B_S, NT, "Intel", "B250", enable_flash_pch100}, {0x8086, 0xa2c9, B_S, NT, "Intel", "Z370", enable_flash_pch100}, + {0x8086, 0xa2ca, B_S, DEP, "Intel", "H310C", enable_flash_pch100}, + {0x8086, 0xa2cc, B_S, DEP, "Intel", "B365", enable_flash_pch100}, {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100}, {0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, + {0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, + {0x8086, 0x3197, B_S, NT, "Intel", "Gemini Lake", enable_flash_glk}, + {0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk}, + {0x8086, 0x4da4, B_S, DEP, "Intel", "Jasper Lake", enable_flash_jsl}, + {0x8086, 0x4b24, B_S, DEP, "Intel", "Elkhart Lake", enable_flash_mcc}, {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, - {0x8086, 0xa305, B_S, NT, "Intel", "Z390", enable_flash_pch300}, + {0x8086, 0xa305, B_S, DEP, "Intel", "Z390", enable_flash_pch300}, {0x8086, 0xa306, B_S, NT, "Intel", "Q370", enable_flash_pch300}, {0x8086, 0xa308, B_S, NT, "Intel", "B360", enable_flash_pch300}, - {0x8086, 0xa309, B_S, NT, "Intel", "C246", enable_flash_pch300}, + {0x8086, 0xa309, B_S, DEP, "Intel", "C246", enable_flash_pch300}, {0x8086, 0xa30a, B_S, NT, "Intel", "C242", enable_flash_pch300}, {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300}, {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, {0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300}, {0x8086, 0x3482, B_S, DEP, "Intel", "Ice Lake U Premium", enable_flash_pch300}, + {0x8086, 0xa3c8, B_S, OK, "Intel", "B460", enable_flash_pch400}, + {0x8086, 0x0684, B_S, NT, "Intel", "H470", enable_flash_pch400}, + {0x8086, 0x0685, B_S, NT, "Intel", "Z490", enable_flash_pch400}, + {0x8086, 0x0687, B_S, NT, "Intel", "Q470", enable_flash_pch400}, + {0x8086, 0x068c, B_S, NT, "Intel", "QM480", enable_flash_pch400}, + {0x8086, 0x068d, B_S, NT, "Intel", "HM470", enable_flash_pch400}, + {0x8086, 0x068e, B_S, NT, "Intel", "WM490", enable_flash_pch400}, + {0x8086, 0x0697, B_S, NT, "Intel", "W480", enable_flash_pch400}, + {0x8086, 0x4384, B_S, NT, "Intel", "Q570", enable_flash_pch500}, + {0x8086, 0x4385, B_S, NT, "Intel", "Z590", enable_flash_pch500}, + {0x8086, 0x4386, B_S, NT, "Intel", "H570", enable_flash_pch500}, + {0x8086, 0x4387, B_S, NT, "Intel", "B560", enable_flash_pch500}, + {0x8086, 0x4388, B_S, NT, "Intel", "H510", enable_flash_pch500}, + {0x8086, 0x438f, B_S, NT, "Intel", "W580", enable_flash_pch500}, + {0x8086, 0x4389, B_S, NT, "Intel", "WM590", enable_flash_pch500}, + {0x8086, 0x438a, B_S, NT, "Intel", "QM580", enable_flash_pch500}, + {0x8086, 0x438b, B_S, DEP, "Intel", "HM570", enable_flash_pch500}, + {0x8086, 0x54a4, B_S, DEP, "Intel", "Alder Lake-N", enable_flash_pch600}, + {0x8086, 0x51a4, B_S, DEP, "Intel", "Alder Lake-P", enable_flash_pch600}, + {0x8086, 0x7a87, B_S, NT, "Intel", "H610", enable_flash_pch600}, + {0x8086, 0x7a86, B_S, NT, "Intel", "B660", enable_flash_pch600}, + {0x8086, 0x7a85, B_S, NT, "Intel", "H670", enable_flash_pch600}, + {0x8086, 0x7a83, B_S, NT, "Intel", "Q670", enable_flash_pch600}, + {0x8086, 0x7a84, B_S, DEP, "Intel", "Z690", enable_flash_pch600}, + {0x8086, 0x7a88, B_S, NT, "Intel", "W680", enable_flash_pch600}, + {0x8086, 0x7a8a, B_S, NT, "Intel", "W685", enable_flash_pch600}, + {0x8086, 0x7a8d, B_S, NT, "Intel", "WM690", enable_flash_pch600}, + {0x8086, 0x7a8c, B_S, NT, "Intel", "HM670", enable_flash_pch600}, + {0x8086, 0x7e23, B_S, DEP, "Intel", "Meteor Lake-P/M", enable_flash_mtl}, #endif {0}, }; -int chipset_flash_enable(void) +int chipset_flash_enable(const struct programmer_cfg *cfg) { struct pci_dev *dev = NULL; int ret = -2; /* Nothing! */ @@ -2059,7 +2193,7 @@ int chipset_flash_enable(void) /* Now let's try to find the chipset we have... */ for (i = 0; chipset_enables[i].vendor_name != NULL; i++) { - dev = pci_dev_find(chipset_enables[i].vendor_id, + dev = pcidev_find(chipset_enables[i].vendor_id, chipset_enables[i].device_id); if (!dev) continue; @@ -2084,7 +2218,7 @@ int chipset_flash_enable(void) if (chipset_enables[i].status == BAD) { msg_perr("ERROR: This chipset is not supported yet.\n"); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } if (chipset_enables[i].status == NT) { msg_pinfo("This chipset is marked as untested. If " @@ -2100,7 +2234,7 @@ int chipset_flash_enable(void) continue; } msg_pinfo("Enabling flash write... "); - ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name); + ret = chipset_enables[i].doit(cfg, dev, chipset_enables[i].device_name); if (ret == NOT_DONE_YET) { ret = -2; msg_pinfo("OK - searching further chips.\n"); @@ -2108,9 +2242,9 @@ int chipset_flash_enable(void) msg_pinfo("FAILED!\n"); else if (ret == 0) msg_pinfo("OK.\n"); - else if (ret == ERROR_NONFATAL) + else if (ret == ERROR_FLASHROM_NONFATAL) msg_pinfo("PROBLEMS, continuing anyway\n"); - if (ret == ERROR_FATAL) { + if (ret == ERROR_FLASHROM_FATAL) { msg_perr("FATAL ERROR!\n"); return ret; } |