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author | Sergii Dmytruk <sergii.dmytruk@3mdeb.com> | 2022-07-24 17:11:05 +0300 |
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committer | Anastasia Klimchuk <aklm@chromium.org> | 2022-11-19 06:56:11 +0000 |
commit | 125a328b4d8445f41c9fdde9e51c1b2bb40ad72e (patch) | |
tree | ebc90fd1c88be2924d9d034bd171312fe829229e /spi25_statusreg.c | |
parent | f32f5e31d99531ee61bd31c64f41cc4baee68d57 (diff) | |
download | flashrom-125a328b4d8445f41c9fdde9e51c1b2bb40ad72e.tar.gz flashrom-125a328b4d8445f41c9fdde9e51c1b2bb40ad72e.tar.bz2 flashrom-125a328b4d8445f41c9fdde9e51c1b2bb40ad72e.zip |
spi25_statusreg: support reading/writing configuration register
One more variation of registers.
This one is read via a separate RDCR command, but written as if it's
SR2 using WRSR_EXT2.
Change-Id: I45f9afcc31f1928ef6263a749596380082963de4
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66211
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'spi25_statusreg.c')
-rw-r--r-- | spi25_statusreg.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 2859b232..b178b2e3 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -107,6 +107,23 @@ int spi_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t */ msg_cerr("Cannot write SECURITY: unsupported by design\n"); return 1; + case CONFIG: + /* + * This one is read via a separate command, but written as if it's SR2 + * in FEATURE_WRSR_EXT2 case of WRSR command. + */ + if (feature_bits & FEATURE_CFGR) { + write_cmd[0] = JEDEC_WRSR; + if (spi_read_register(flash, STATUS1, &write_cmd[1])) { + msg_cerr("Writing CONFIG failed: failed to read SR1 for writeback.\n"); + return 1; + } + write_cmd[2] = value; + write_cmd_len = 3; + break; + } + msg_cerr("Cannot write CONFIG: unsupported by chip\n"); + return 1; default: msg_cerr("Cannot write register: unknown register\n"); return 1; @@ -209,6 +226,13 @@ int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t } msg_cerr("Cannot read SECURITY: unsupported by chip\n"); return 1; + case CONFIG: + if (feature_bits & FEATURE_CFGR) { + read_cmd = JEDEC_RDCR; + break; + } + msg_cerr("Cannot read CONFIG: unsupported by chip\n"); + return 1; default: msg_cerr("Cannot read register: unknown register\n"); return 1; |