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| author | Edward O'Callaghan <quasisec@google.com> | 2020-02-18 14:38:08 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-02-24 09:15:00 +0000 |
| commit | 0f510a7458e0efe95534667bba122b4ab67b26c1 (patch) | |
| tree | 19032bf855ce51d207b494e1c0ed54e7642c69a7 /ichspi.c | |
| parent | 7a7fee1695bc3ea9df4a9a058a1805210328d691 (diff) | |
| download | flashrom-0f510a7458e0efe95534667bba122b4ab67b26c1.tar.gz flashrom-0f510a7458e0efe95534667bba122b4ab67b26c1.tar.bz2 flashrom-0f510a7458e0efe95534667bba122b4ab67b26c1.zip | |
util/flashrom_tester: Upstream E2E testing framework
The following is a E2E tester for a specific chip/chipset
combo. The tester itself is completely self-contained and
allows the user to specify which tests they wish to preform.
Supported tests include:
- chip-name
- read
- write
- erase
- wp-locking
Change-Id: Ic2905a76cad90b1546b9328d668bf8abbf8aed44
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'ichspi.c')
0 files changed, 0 insertions, 0 deletions