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| author | Nikolai Artemiev <nartemiev@google.com> | 2021-10-20 23:34:15 +1100 |
|---|---|---|
| committer | Anastasia Klimchuk <aklm@chromium.org> | 2022-03-01 03:56:22 +0000 |
| commit | e00790865726b6f1a6492af0833e3cbf9c215496 (patch) | |
| tree | 28ad15a5adc3f532488c5a8b0812de879067c41b /flashchips.c | |
| parent | b7ea3a9a5d481a09229abba0fe6d2509ef2713a1 (diff) | |
| download | flashrom-e00790865726b6f1a6492af0833e3cbf9c215496.tar.gz flashrom-e00790865726b6f1a6492af0833e3cbf9c215496.tar.bz2 flashrom-e00790865726b6f1a6492af0833e3cbf9c215496.zip | |
flash.h,flashchips.c: add writeprotect bit layout map to chips
This patch adds a register bit map `struct reg_bit_info`, with fields
for storing the register, bit index, and writability of each bit that
affects the chip's write protection. This allows writeprotect code to be
independent of the register layout of any specific chip. The new fields
have been filled out for example chips.
The representation is centered around describing how bits can be
accessed and modified, rather than the layout of registers. This is
generally easier to work with in code that needs to access specific bits
and typically requires specifying the locations of fewer bits overall.
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
Change-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Diffstat (limited to 'flashchips.c')
| -rw-r--r-- | flashchips.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/flashchips.c b/flashchips.c index 9e10b5d2..e12c8fce 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6345,6 +6345,15 @@ const struct flashchip flashchips[] = { .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1695, 1950}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */ + .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */ + .cmp = {STATUS2, 6, RW}, + }, }, { @@ -6744,6 +6753,13 @@ const struct flashchip flashchips[] = { .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 6, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {STATUS1, 6, RW}, + }, }, { @@ -6783,6 +6799,15 @@ const struct flashchip flashchips[] = { .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */ + .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */ + .cmp = {STATUS2, 6, RW}, + }, }, { |