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authorSergii Dmytruk <sergii.dmytruk@3mdeb.com>2022-08-14 20:57:48 +0300
committerAnastasia Klimchuk <aklm@chromium.org>2022-11-19 07:12:07 +0000
commitd899d988590822d693ac5dde955946454e86763f (patch)
treefca96f129cc0660b9b58b2be57244ae36c218cbd /flashchips.c
parent994de3ae946820dd6e03eb600e2e623e917845a4 (diff)
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flashchips.c: enable WP for EN25QH32 and EN25QH64
Split chips: * EN25QH32 -> EN25QH32 and EN25QH32B * EN25QH64 -> EN25QH64 and EN25QH64A Unlike older revisions both newly added EN25QH32B and EN25QH64A support half block (32KiB) erase operation via 0x52 opcode. Change-Id: I759f0119346235ce0bddc78cde9c461495990c25 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Diffstat (limited to 'flashchips.c')
-rw-r--r--flashchips.c96
1 files changed, 96 insertions, 0 deletions
diff --git a/flashchips.c b/flashchips.c
index 88be1d13..cb993e00 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -5260,6 +5260,54 @@ const struct flashchip flashchips[] = {
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ,
.voltage = {2700, 3600},
+ .reg_bits =
+ {
+ .srp = {STATUS1, 7, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+ .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */
+ },
+ .decode_range = DECODE_RANGE_SPI25,
+ },
+
+ {
+ .vendor = "Eon",
+ .name = "EN25QH32B",
+ .bustype = BUS_SPI,
+ .manufacture_id = EON_ID_NOPREFIX,
+ .model_id = EON_EN25QH32,
+ .total_size = 4096,
+ .page_size = 256,
+ /* supports SFDP */
+ /* OTP: 1536B total; enter 0x3A */
+ /* QPI enable 0x38, disable 0xFF */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
+ .tested = TEST_OK_PREW,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 128} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 64} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {1024 * 4096, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {1024 * 4096, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
+ .unlock = spi_disable_blockprotect_bp3_srwd,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ,
+ .voltage = {2700, 3600},
},
{
@@ -5298,6 +5346,54 @@ const struct flashchip flashchips[] = {
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ,
.voltage = {2700, 3600},
+ .reg_bits =
+ {
+ .srp = {STATUS1, 7, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+ .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */
+ },
+ .decode_range = DECODE_RANGE_SPI25_64K_BLOCK,
+ },
+
+ {
+ .vendor = "Eon",
+ .name = "EN25QH64A",
+ .bustype = BUS_SPI,
+ .manufacture_id = EON_ID_NOPREFIX,
+ .model_id = EON_EN25QH64,
+ .total_size = 8192,
+ .page_size = 256,
+ /* supports SFDP */
+ /* OTP: 512B total; enter 0x3A */
+ /* QPI enable 0x38, disable 0xFF */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
+ .tested = TEST_OK_PREW,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 2048} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 256} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 128} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { { 8192 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { { 8192 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
+ .unlock = spi_disable_blockprotect_bp3_srwd,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ,
+ .voltage = {2700, 3600},
},
{