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authorLuka Kovacic <luka.kovacic@sartura.hr>2020-07-30 13:31:15 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-08-25 17:58:37 +0000
commit8f18e811e584507a9ba664f6d5d483a0408729b4 (patch)
tree7f9b8dfcebc1212abab4973eabdfb46a0a107805 /chipset_enable.c
parentda6b3b70cb852dd8e9f9e21aef95fa83e7f7ab0d (diff)
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chipset_enable.c: Add support for Intel C620 Series Chipset SPI Controller
Support for the Intel C620 Series Chipset SPI Controller (rev 04) is added to enable SPI flash access on the following platform: - Intel Xeon D-2187NT Support for this controller was shortly tested on the platform above. The flash is recognized, some regions of the flash are locked. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Tested-by: Jakov Petrina <jakov.petrina@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Change-Id: If39d9bb1acd4029f802a44a2940dd23f66ba09b1 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'chipset_enable.c')
-rw-r--r--chipset_enable.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c
index d56a5470..4772a1c4 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -2023,6 +2023,7 @@ const struct penable chipset_enables[] = {
{0x8086, 0xa153, B_S, NT, "Intel", "QM175", enable_flash_pch100},
{0x8086, 0xa154, B_S, NT, "Intel", "CM238", enable_flash_pch100},
{0x8086, 0xa155, B_S, NT, "Intel", "QMU185", enable_flash_pch100},
+ {0x8086, 0xa1a4, B_S, DEP, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620},
{0x8086, 0xa1c0, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620},
{0x8086, 0xa1c1, B_S, NT, "Intel", "C621 Series Chipset (QS/PRQ)", enable_flash_c620},
{0x8086, 0xa1c2, B_S, NT, "Intel", "C622 Series Chipset (QS/PRQ)", enable_flash_c620},