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| author | Nikolai Artemiev <nartemiev@google.com> | 2022-11-02 11:30:57 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2022-12-06 03:12:55 +0000 |
| commit | 49bcb78006d88189bb13513982f3fa734b441641 (patch) | |
| tree | 11586cf450e59b78d94a530b74028b04888da288 /bindings | |
| parent | 62ec7b7156e1b35da66f54f6d493b38a9e78f94c (diff) | |
| download | flashrom-49bcb78006d88189bb13513982f3fa734b441641.tar.gz flashrom-49bcb78006d88189bb13513982f3fa734b441641.tar.bz2 flashrom-49bcb78006d88189bb13513982f3fa734b441641.zip | |
writeprotect,ichspi,spi25: handle register access constraints
Make the spi25 register read/write functions return SPI_INVALID_OPCODE
if the programmer blocks the read/write opcode for the register.
Likewise, make ichspi read/write register functions return
SPI_INVALID_OPCODE for registers >SR1 as they cannot be accessd.
Make writeprotect ignore SPI_INVALID_OPCODE unless it is trying to
read/write SR1, which should always be supported.
BUG=b:253715389,b:253713774,b:240229722
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status} on dedede
Change-Id: I2145749dcc51f4556550650dab5aa1049f879c45
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/69129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'bindings')
0 files changed, 0 insertions, 0 deletions