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| author | Nico Huber <nico.huber@secunet.com> | 2017-03-20 14:25:09 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-06-04 10:28:53 +0000 |
| commit | a50b8fde67fa52984980159127de789cf9a1c688 (patch) | |
| tree | cb7230f818fd01fd47e22de2258e1d6914528b74 /atahpt.c | |
| parent | 291c101c66adcb1c3435934f3f49fa7f24f7c249 (diff) | |
| download | flashrom-a50b8fde67fa52984980159127de789cf9a1c688.tar.gz flashrom-a50b8fde67fa52984980159127de789cf9a1c688.tar.bz2 flashrom-a50b8fde67fa52984980159127de789cf9a1c688.zip | |
chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs
The Kaby Lake "200 Series" PCHs [1,2] share the register layout of their
Skylake "100 Series" siblings.
[1] Intel® 200 Series (including X299) and Intel® Z370 Series
Chipset Families Platform Controller Hub (PCH)
Datasheet - Volume 1 of 2
Revision 003
Document Number 335192
[2] Intel® 200 Series (including X299) Chipset Family Platform
Controller Hub (PCH)
Datasheet - Volume 2 of 2
Revision 003
Document Number 335193
Change-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'atahpt.c')
0 files changed, 0 insertions, 0 deletions