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authorAlan Mishchenko <alanmi@berkeley.edu>2014-09-17 15:20:04 -0700
committerAlan Mishchenko <alanmi@berkeley.edu>2014-09-17 15:20:04 -0700
commit69827a5a8848ada3ef70bcf25f4f523aed97bded (patch)
treeb8d329461b4fa68651fdba155ebdb089eaee228f /src/base/wlc/wlcReadVer.c
parentffd77ffedda47d5ec5541c6a51bb9e80540fd3f7 (diff)
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Improvements to word-level Verilog parser.
Diffstat (limited to 'src/base/wlc/wlcReadVer.c')
-rw-r--r--src/base/wlc/wlcReadVer.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/base/wlc/wlcReadVer.c b/src/base/wlc/wlcReadVer.c
index 9ee81844..34197e1b 100644
--- a/src/base/wlc/wlcReadVer.c
+++ b/src/base/wlc/wlcReadVer.c
@@ -705,8 +705,9 @@ int Wlc_PrsDerive( Wlc_Prs_t * p )
if ( Wlc_PrsStrCmp( pName, "table" ) )
{
// THIS IS A HACK TO DETECT tables
- int Width1, Width2;
- int v, b, Value, nBits, nInts, * pTable;
+ int Width1 = -1, Width2 = -1;
+ int v, b, Value, nBits, nInts;
+ unsigned * pTable;
Vec_Int_t * vValues = Vec_IntAlloc( 256 );
Wlc_PrsForEachLineStart( p, pStart, i, i+1 )
{