From 69827a5a8848ada3ef70bcf25f4f523aed97bded Mon Sep 17 00:00:00 2001 From: Alan Mishchenko Date: Wed, 17 Sep 2014 15:20:04 -0700 Subject: Improvements to word-level Verilog parser. --- src/base/wlc/wlcReadVer.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/base/wlc/wlcReadVer.c') diff --git a/src/base/wlc/wlcReadVer.c b/src/base/wlc/wlcReadVer.c index 9ee81844..34197e1b 100644 --- a/src/base/wlc/wlcReadVer.c +++ b/src/base/wlc/wlcReadVer.c @@ -705,8 +705,9 @@ int Wlc_PrsDerive( Wlc_Prs_t * p ) if ( Wlc_PrsStrCmp( pName, "table" ) ) { // THIS IS A HACK TO DETECT tables - int Width1, Width2; - int v, b, Value, nBits, nInts, * pTable; + int Width1 = -1, Width2 = -1; + int v, b, Value, nBits, nInts; + unsigned * pTable; Vec_Int_t * vValues = Vec_IntAlloc( 256 ); Wlc_PrsForEachLineStart( p, pStart, i, i+1 ) { -- cgit v1.2.3