1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
|
include relpath.mk
PART=xc6slx9-2-tqg144
TOP=hp_lcd_driver
BUILD=build
VSRCS=hp_lcd_driver.vhd
UCF=hp_lcd_driver.ucf
UT=hp_lcd_driver.ut
IPSRCS=vram.xco
DESIGN_NAME=${TOP}
ISE_BINDIR=/software/apps/xilinx/ISE/14.7/ISE_DS/ISE/bin/lin64
INTSTYLE=
XST_FLAGS=${INTSTYLE}
NGDBUILD_FLAGS=${INTSTYLE} -p ${PART} -dd _ngo -nt timestamp
MAP_FLAGS=${INTSTYLE} -p ${PART} -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off
PAR_FLAGS=${INTSTYLE} -w -ol high -mt off
TRCE_FLAGS=${INTSTYLE} -v 3 -s 2 -n 3 -fastpaths
BITGEN_FLAGS=${INTSTYLE}
GEN_VSRCS=${IPSRCS:%.xco=${BUILD}/%.vhd}
BASE=${BUILD}/${DESIGN_NAME}
XST=${BASE}.xst
PRJ=${BASE}.prj
SYR=${BASE}.syr
NGC=${BASE}.ngc
NGD=${BASE}.ngd
MAP_NCD=${BASE}_map.ncd
NCD=${BASE}.ncd
PCF=${BASE}.pcf
TWR=${BASE}.twr
TWX=${BASE}.twx
BIT=${BASE}.bit
SVF=${BASE}.svf
XST_TMPDIR=xst/projnav.tmp
XST_DIR=xst
default: ${NCD} ${TWR} ${TWX} ${BIT} ${SVF}
clean:
/bin/rm -rf ${BUILD}
${PRJ}: ${VSRCS} ${GEN_VSRCS}
mkdir -p ${BUILD}
rm -f $@
for file in $(GEN_VSRCS) ${VSRCS}; do \
echo "vhdl work $$(realpath -m --relative-to=${BUILD} $${file})" >> $@ ; \
done ;
${NGC}:${XST}
(cd ${BUILD} && mkdir -p ${XST_DIR} ${XST_TMPDIR} && ${ISE_BINDIR}/xst ${XST_FLAGS} -ifn $(call relpath,$<,${BUILD}) -ofn $(call relpath,${SYR},${BUILD}))
${XST}: ${PRJ} ${DESIGN_NAME}.xst_template
rm -f $@
echo 'set -tmpdir "${XST_TMPDIR}"' >> $@
echo 'set -xsthdpdir "${XST_DIR}"' >> $@
cat ${DESIGN_NAME}.xst_template >> $@
echo "-ifn $(call relpath,${PRJ},${BUILD})" >> $@
echo "-ofn $(call relpath,${BASE},${BUILD})" >> $@
echo "-p ${PART}" >> $@
echo "-top ${TOP}" >> $@
${NGD}:${NGC} ${UCF}
(cd ${BUILD} && ${ISE_BINDIR}/ngdbuild $(NGDBUILD_FLAGS) -uc $(call relpath,${UCF},${BUILD}) $(call relpath,${NGC},${BUILD}) $(call relpath,$@,${BUILD}))
${MAP_NCD} ${PCF}:${NGD}
(cd ${BUILD} && ${ISE_BINDIR}/map $(MAP_FLAGS) -o $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NGD},${BUILD}) $(call relpath,${PCF},${BUILD}))
${NCD}: ${MAP_NCD} ${PCF}
(cd ${BUILD} && ${ISE_BINDIR}/par $(PAR_FLAGS) $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NCD},${BUILD}) $(call relpath,${PCF},${BUILD}))
${TWR} ${TWX}: ${NCD} ${PCF}
(cd ${BUILD} && ${ISE_BINDIR}/trce ${TRCE_FLAGS} -xml $(call relpath,${TWX},${BUILD}) $(call relpath,${NCD},${BUILD}) -o $(call relpath,${TWR},${BUILD}) $(call relpath,${PCF},${BUILD}))
${BIT}:${NCD} ${UT}
(cd ${BUILD} && ${ISE_BINDIR}/bitgen ${BITGEN_FLAGS} -f $(call relpath,${UT},${BUILD}) $(call relpath,${NCD},${BUILD}))
${SVF}:${BIT}
( cd ${BUILD} && \
echo -e "setMode -bs \n\
setCable -p svf -file \"$(call relpath,${SVF},${BUILD})\" \n\
addDevice -p 1 -file \"$(call relpath,${BIT},${BUILD})\" \n\
program -p 1 \n\
quit \n" > impact.run &&\
${ISE_BINDIR}/impact -batch impact.run)
${BUILD}/%.vhd:%.xco
mkdir -p ${BUILD}
(cd ${BUILD} && touch empty.prj && ${ISE_BINDIR}/coregen -b $(call relpath,$<,${BUILD}) -p empty.prj)
#
#
##
## Flags and option values that control the behavior of the Xilinx tools.
## You can override these values in the makefile that includes this one.
## Otherwise, the default values will be set as shown below.
##
#
## Unless otherwise specified, the name of the design and the top-level
## entity are derived from the name of the directory that contains the design.
#DIR_SPACES := $(subst /, ,$(CURDIR))
#DIR_NAME := $(word $(words $(DIR_SPACES)), $(DIR_SPACES))
#DESIGN_NAME ?= $(DIR_NAME)
#TOP_NAME ?= $(DESIGN_NAME)
#SYNTH_DIR ?= .
#SIM_DIR ?= .
#
## Extract the part identifier from the project .npl file.
#PART_TYPE ?= $(shell $(GET_OPTION_VALUES) $(DESIGN_NAME).npl DEVICE)
#PART_SPEED_GRADE ?= $(subst -,,$(shell $(GET_OPTION_VALUES) $(DESIGN_NAME).npl DEVSPEED))
#PART_PACKAGE ?= $(shell $(GET_OPTION_VALUES) $(DESIGN_NAME).npl DEVPKG)
#PART ?= $(PART_TYPE)-$(PART_SPEED_GRADE)-$(PART_PACKAGE)
#
## Flags common to both FPGA design flow.
#INTSTYLE ?= -intstyle silent # call Xilinx tools in silent mode
#XST_FLAGS ?= $(INTSTYLE) # most synthesis flags are specified in the .xst file
#UCF_FILE ?= $(DESIGN_NAME).ucf # constraint/pin-assignment file
#NGDBUILD_FLAGS ?= $(INTSTYLE) -dd _ngo # ngdbuild flags
#NGDBUILD_FLAGS += $(if $(UCF_FILE),-uc,) $(UCF_FILE) # append the UCF file option if it is specified
#
## Flags for FPGA-specific tools. These were extracted by looking in the
## .cmd_log file after compiling the design with the WebPACK/ISE GUI.
#MAP_FLAGS ?= $(INTSTYLE) -cm area -pr b -c 100 -tx off
#PAR_FLAGS ?= $(INTSTYLE) -w -ol std -t 1
#TRCE_FLAGS ?= $(INTSTYLE) -e 3 -l 3
#BITGEN_FLAGS ?= $(INTSTYLE) -w # most bitgen flags are specified in the .ut file
#PROMGEN_FLAGS ?= -u 0 # flags that control the MCS/EXO file generation
#
## Determine the version of Xilinx ISE that is being used by reading it from the
## readme.txt file in the top-level directory of the Xilinx software.
#PROJNAV_DIR ?= .
#
#XST_FPGA_OPTIONS_FILE ?= $(PROJNAV_DIR)/$(DESIGN_NAME).xst
#BITGEN_OPTIONS_FILE ?= $(DESIGN_NAME).ut
#XST_OPTIONS_FILE = $(XST_FPGA_OPTIONS_FILE)
#
#
#
##
## The following rules describe how to compile the design to an FPGA
##
#
#HDL_FILES := $(foreach file,$(SRCS_SYNTH),$(SYNTH_DIR)/$(file))
#SIM_FILES := $(foreach file,$(SRCS_SIM),$(SIM_DIR)/$(file))
#
## default target
#all: bit
#
#
## cleanup the source code to make it look nice
#%.nice: %.vhd
# $(EMACS) -batch $< -f vhdl-beautify-buffer -f save-buffer
# $(RM) $<~
#
##PRJ FIle generation
#%.prj:
# rm -f $(DESIGN_NAME).prj;
# for file in $(HDL_FILES); do \
# echo "vhdl work $${file}" >> $(DESIGN_NAME).prj ; \
# done ;
#
#%.ut:
# cp -n $(UTILITY_DIR)/default.ut $(DESIGN_NAME).ut
#
#%.xst:
# cp -n $(UTILITY_DIR)/default.xst $(DESIGN_NAME).xst
#
#%.ucf:
# cp -n $(UTILITY_DIR)/default.ucf $(UCF_FILE)
#
#
#
#
#
## Synthesize the HDL files into an NGC file. This rule is triggered if
## any of the HDL files are changed or the synthesis options are changed.
#%.ngc: $(HDL_FILES) $(XST_OPTIONS_FILE) $(DESIGN_NAME).prj $(DESIGN_NAME).ut
# $(SET_OPTION_VALUES) $(XST_OPTIONS_FILE) \
# "set -tmpdir $(PROJNAV_DIR)" \
# "-lso $(DESIGN_NAME).lso" \
# "-ifn $(DESIGN_NAME).prj" \
# "-ofn $(DESIGN_NAME)" \
# "-p $(PART)" \
# "-top $(TOP_NAME)" \
# > $(PROJNAV_DIR)/tmp.xst
# ${ISE_BINDIR}/xst $(XST_FLAGS) -ifn $(PROJNAV_DIR)/tmp.xst -ofn $*.syr
#
## Take the output of the synthesizer and create the NGD file. This rule
## will also be triggered if constraints file is changed.
#%.ngd: %.ngc %.ucf
# ${ISE_BINDIR}/ngdbuild $(NGDBUILD_FLAGS) -p $(PART) $*.ngc $*.ngd
#
## Map the NGD file and physical-constraints to the FPGA to create the mapped NCD file.
#%_map.ncd %.pcf: %.ngd
# ${ISE_BINDIR}/map $(MAP_FLAGS) -p $(PART) -o $*_map.ncd $*.ngd $*.pcf
#
## Place & route the mapped NCD file to create the final NCD file.
#%.ncd: %_map.ncd %.pcf
# ${ISE_BINDIR}/par $(PAR_FLAGS) $*_map.ncd $*.ncd $*.pcf
#
## Take the final NCD file and create an FPGA bitstream file. This rule will also be
## triggered if the bit generation options file is changed.
#%.bit: %.ncd $(BITGEN_OPTIONS_FILE)
# ${ISE_BINDIR}/bitgen $(BITGEN_FLAGS) -f $(BITGEN_OPTIONS_FILE) $*.ncd
#
## Convert a bitstream file into an MCS hex file that can be stored into Flash memory.
#%.mcs: %.bit
# ${ISE_BINDIR}/promgen $(PROMGEN_FLAGS) $*.bit -p mcs
#
## Convert a bitstream file into an EXO hex file that can be stored into Flash memory.
#%.exo: %.bit
# ${ISE_BINDIR}/promgen $(PROMGEN_FLAGS) $*.bit -p exo
#
## Use .config suffix to trigger creation of a bit/svf file
## depending upon whether an FPGA is the target device.
#%.config: %.bit ;
#
## Create the FPGA timing report after place & route.
#%.twr: %.ncd %.pcf
# ${ISE_BINDIR}/trce $(TRCE_FLAGS) $*.ncd -o $*.twr $*.pcf
#
## Use .timing suffix to trigger timing report creation.
#%.timing: %.twr ;
#
## Preserve intermediate files.
#.PRECIOUS: %.ngc %.ngd %_map.ncd %.ncd %.twr %.vm6 %.jed %.prj %.ut %.xst %.ucf
#
## Clean up after creating the configuration file.
#%.clean:
# -$(RM) *.stx *.ucf.untf *.mrp *.nc1 *.ngm *.prm *.lfp
# -$(RM) *.placed_ncd_tracker *.routed_ncd_tracker
# -$(RM) *.pad_txt *.twx *.log *.vhd~ *.dhp *.jhd *.cel
# -$(RM) *.ngr *.ngc *.ngd *.syr *.bld *.pcf
# -$(RM) *_map.mrp *_map.ncd *_map.ngm *.ncd *.pad *.bit
# -$(RM) *.par *.xpi *_pad.csv *_pad.txt *.drc *.bgn *.lso *.npl
# -$(RM) *.xml *_build.xml *.rpt *.gyd *.mfd *.pnx *.xrpt *.ptwx *.twr *.srp
# -$(RM) *.vm6 *.jed *.err *.ER result.txt tmperr.err *.bak *.vhd~
# -$(RM) *.zip *_backup *.*log *.map *.unroutes *.html
# -$(RM) impactcmd.txt tmp.xst impact.run *.wlf transcript
# -$(RMDIR) xst _ngo *_html __projnav xlnx_auto_* work
#
## Clean everything.
#%.distclean: %.clean
# -$(RM) *.prj
#
#%.impact : $(DESIGN_NAME).bit
# echo -e "setMode -bs \n\
# setCable -p auto \n\
# identify \n\
# assignFile -p 1 -file $(DESIGN_NAME).bit \n\
# program -p 1 \n\
# quit \n" > impact.run
# ${ISE_BINDIR}/impact -batch impact.run
#
##Simulation using ModelSIM
#setlib:
# ${ISE_BINDIR}/vlib work
#
#vsim-compile: setlib $(SIM_FILES) $(HDL_FILES)
# ${ISE_BINDIR}/vcom $(HDL_FILES) $(SIM_FILES)
#
#vsim: vsim-compile
# ${ISE_BINDIR}/vsim $(TESTBENCH_NAME)
#
#vsim-run: vsim-compile
# ${ISE_BINDIR}/vsim -c -do "run -all; quit" $(TESTBENCH_NAME)
#
##
## Default targets for FPGA compilations.
##
#
#config : $(DESIGN_NAME).config
#bit : $(DESIGN_NAME).bit
#mcs : $(DESIGN_NAME).mcs
#exo : $(DESIGN_NAME).exo
#timing : $(DESIGN_NAME).timing
#clean : $(DESIGN_NAME).clean
#distclean : $(DESIGN_NAME).distclean
#nice : $(subst .vhd,.nice,$(HDL_FILES))
#impact : $(DESIGN_NAME).impact
|
