blob: e6acad842303b07caacd5959ebbc0acbbfdebcab (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
|
BUILD=build_${BOARD}
IP= \
zynq7_ip/mmcm_0.tcl \
zynq7_ip/mmcm_1.tcl \
zynq7_ip/blk_mem_gen_0.tcl \
zynq7_ip/processing_system7_0.tcl \
zynq7_ip/fifo_generator_0.tcl
BIT=${BUILD}/out/hp_lcd_driver.bit
BIN=${BUILD}/out/hp_lcd_driver.bin
IP_STAMP=${IP:zynq7_ip/%.tcl=${BUILD}/ip/%/stamp}
SRCS= ${IP} \
zynq7_config.tcl \
zynq7_hp_lcd_driver.tcl \
${BOARD}.tcl \
${BOARD}.xdc \
clkgen_artix7.vhdl \
debounce.vhdl \
delay.vhdl \
edge_det.vhdl \
common.vhdl \
input_formatter.vhdl \
input_stage.vhdl \
output_analog.vhdl \
output_formatter.vhdl \
output_stage.vhdl \
synchronizer.vhdl \
tmds_encoder.vhdl \
tmds_encode.vhdl \
tmds_output_artix7.vhdl \
tmds_phy_artix7.vhdl \
vram_artix7.vhdl \
zynq7_wrapper.vhdl \
fifo_to_axi.vhdl \
vnc_serializer.vhdl
OPENOCD=openocd -f openocd/${BOARD}.cfg
default: ${BUILD}/build.stamp
${BIN} ${BIT}:${BUILD}/build.stamp
${BUILD}/build.stamp:${SRCS} ${IP_STAMP}
mkdir -p ${BUILD}
(cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch -source ../zynq7_hp_lcd_driver.tcl)
#scripts/xilinx_bit_to_bin.pl ${BIT} ${BIN}
touch $@
${BUILD}/ip/%/stamp:zynq7_ip/%.tcl
mkdir -p ${BUILD}/ip
/bin/rm -rf $(dir $@)
(cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch -source ../$<) && touch $@
${BIT}: ${BUILD}/build.stamp
clean:
/bin/rm -rf ${BUILD}
|