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library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity tmds_phy_cyclone4 is
port (
sys_rst_n : in std_logic;
pclk_phy : in std_logic;
b : natural;
din : in std_logic_vector(9 downto 0);
tmds_out_p : out std_logic;
tmds_out_n : out std_logic
);
end tmds_phy_cyclone4;
architecture beh of tmds_phy_cyclone4 is
signal d_rise : std_logic_vector(4 downto 0);
signal d_fall : std_logic_vector(4 downto 0);
signal out_p : std_logic_vector(0 downto 0);
signal out_n : std_logic_vector(0 downto 0);
signal bb : natural;
begin
process (pclk_phy)
begin
if rising_edge(pclk_phy) then
if b = 4 then
d_rise <= (4 => din(8), 3 => din(6), 2 => din(4), 1 => din(2), 0 => din(0));
d_fall <= (4 => din(9), 3 => din(7), 2 => din(5), 1 => din(3), 0 => din(1));
--d_rise <= (4 => din(1), 3 => din(3), 2 => din(5), 1 => din(7), 0 => din(9));
--d_fall <= (4 => din(0), 3 => din(2), 2 => din(4), 1 => din(6), 0 => din(8));
else
d_rise(3 downto 0) <= d_rise(4 downto 1);
d_fall(3 downto 0) <= d_fall(4 downto 1);
end if;
end if;
end process;
obuf_p : ALTDDIO_OUT
generic map (
extend_oe_disable => "OFF",
intended_device_family => "Cyclone IV E",
invert_output => "OFF",
lpm_hint => "UNUSED",
lpm_type => "altddio_out",
oe_reg => "UNREGISTERED",
power_up_high => "OFF",
width => 1
)
port map (
aclr => not sys_rst_n,
datain_h => d_rise(0 downto 0),
datain_l => d_fall(0 downto 0),
outclock => not pclk_phy,
dataout => out_p
);
tmds_out_p <= out_p(0);
obuf_n : ALTDDIO_OUT
generic map (
extend_oe_disable => "OFF",
intended_device_family => "Cyclone IV E",
invert_output => "OFF",
lpm_hint => "UNUSED",
lpm_type => "altddio_out",
oe_reg => "UNREGISTERED",
power_up_high => "OFF",
width => 1
)
port map (
aclr => not sys_rst_n,
datain_h => not d_rise(0 downto 0),
datain_l => not d_fall(0 downto 0),
outclock => not pclk_phy,
dataout => out_n
);
tmds_out_n <= out_n(0);
end beh;
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