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library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity tmds_output is
port (
sys_rst_n : in std_logic;
pclk_locked : in std_logic;
pclk : in std_logic;
pclk_x2 : in std_logic;
pclk_phy : in std_logic;
r_p10 : in std_logic_vector(9 downto 0);
g_p10 : in std_logic_vector(9 downto 0);
b_p10 : in std_logic_vector(9 downto 0);
c_p10 : in std_logic_vector(9 downto 0);
tmds_c_out_p : out std_logic;
tmds_c_out_n : out std_logic;
tmds_r_out_p : out std_logic;
tmds_r_out_n : out std_logic;
tmds_g_out_p : out std_logic;
tmds_g_out_n : out std_logic;
tmds_b_out_p : out std_logic;
tmds_b_out_n : out std_logic
);
end tmds_output;
architecture beh of tmds_output is
signal phy_reset : std_logic;
signal upper : std_logic;
signal pll_locked : std_logic;
signal ioclk : std_logic;
signal serdesstrobe : std_logic;
begin
phy_reset <= not sys_rst_n or not pll_locked;
process (pclk_x2, phy_reset)
begin
if phy_reset = '1' then
upper <= '1';
elsif rising_edge(pclk_x2) then
upper <= not upper;
end if;
end process;
ioclk_buf : BUFPLL generic map (DIVIDE => 5)
port map (
PLLIN => pclk_phy,
GCLK => pclk_x2,
LOCKED => pclk_locked,
IOCLK => ioclk,
SERDESSTROBE => serdesstrobe,
LOCK => pll_locked);
phy_c : entity work.tmds_phy_spartan6
port map (
reset => phy_reset,
pclk_x2 => pclk_x2,
serdesstrobe => serdesstrobe,
ioclk => ioclk,
upper => upper,
din => c_p10,
tmds_out_p => tmds_c_out_p,
tmds_out_n => tmds_c_out_n
);
phy_r : entity work.tmds_phy_spartan6
port map (
reset => phy_reset,
pclk_x2 => pclk_x2,
serdesstrobe => serdesstrobe,
ioclk => ioclk,
upper => upper,
din => r_p10,
tmds_out_p => tmds_r_out_p,
tmds_out_n => tmds_r_out_n
);
phy_g : entity work.tmds_phy_spartan6
port map (
reset => phy_reset,
pclk_x2 => pclk_x2,
serdesstrobe => serdesstrobe,
ioclk => ioclk,
upper => upper,
din => g_p10,
tmds_out_p => tmds_g_out_p,
tmds_out_n => tmds_g_out_n
);
phy_b : entity work.tmds_phy_spartan6
port map (
reset => phy_reset,
pclk_x2 => pclk_x2,
serdesstrobe => serdesstrobe,
ioclk => pclk_phy,
upper => upper,
din => b_p10,
tmds_out_p => tmds_b_out_p,
tmds_out_n => tmds_b_out_n
);
end beh;
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