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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity clkgen is
port (
sys_rst_n : in std_logic;
clk_in : in std_logic;
i_clk : out std_logic;
o_clk : out std_logic;
o_clk_x2 : out std_logic;
o_clk_phy : out std_logic;
locked : out std_logic
);
end clkgen;
architecture Behavioural of clkgen is
signal clkfbout1 : std_logic;
signal clkfbout2 : std_logic;
signal clk_200m : std_logic;
signal clk_80m : std_logic;
signal clk_78_571m : std_logic;
signal clk_40m : std_logic;
signal clk_20m : std_logic;
signal pll_locked1 : std_logic;
signal pll_locked2 : std_logic;
signal reset1 : std_logic;
signal reset2 : std_logic;
begin
pll1 : PLL_BASE generic map (
CLKIN_PERIOD => 20.0,
CLKFBOUT_MULT => 11,
CLKOUT0_DIVIDE => 7,
COMPENSATION => "INTERNAL")
port map (
CLKFBOUT => clkfbout1,
CLKOUT0 => clk_78_571m,
CLKFBIN => clkfbout1,
CLKIN => clk_in,
LOCKED => pll_locked1,
RST => reset1);
reset1 <= (not pll_locked1) or (not sys_rst_n);
pll2 : PLL_BASE generic map (
CLKIN_PERIOD => 20.0,
CLKFBOUT_MULT => 8,
CLKOUT0_DIVIDE => 2,
CLKOUT1_DIVIDE => 5,
CLKOUT2_DIVIDE => 10,
CLKOUT3_DIVIDE => 20,
COMPENSATION => "INTERNAL")
port map (
CLKFBOUT => clkfbout2,
CLKOUT0 => clk_200m,
CLKOUT1 => open,
CLKOUT2 => clk_40m,
CLKOUT3 => clk_20m,
LOCKED => pll_locked2,
CLKFBIN => clkfbout2,
CLKIN => clk_in,
RST => reset2);
reset2 <= (not pll_locked2) or (not sys_rst_n);
o_clk_buf : BUFG port map (
I => clk_20m,
O => o_clk);
o_clk_x2_buf : BUFG port map (
I => clk_40m,
O => o_clk_x2);
i_clk_buf : BUFG port map (
I => clk_78_571m,
O => i_clk);
o_clk_phy <= clk_200m;
locked <= pll_locked2;
end Behavioural;
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