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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity clkgen is
port (
sys_rst_n : in std_logic;
clk_in : in std_logic;
i_clk : out std_logic;
o_clk : out std_logic;
o_clk_x2 : out std_logic;
o_clk_phy : out std_logic;
locked : out std_logic
);
end clkgen;
architecture Behavioural of clkgen is
signal clk_240m : std_logic;
signal clk_78_571m : std_logic;
signal clk_80m : std_logic;
signal clk_24m : std_logic;
signal clk_48m : std_logic;
signal clk_50m : std_logic;
signal reset : std_logic;
begin
reset <= not sys_rst_n;
o_clk_buf : BUFG port map (
I => clk_in,
O => clk_50m);
mmcm_0_i : mmcm_0 port map (
clk_in1 => clk_50m,
clk_out1 => clk_240m,
clk_out2 => clk_80m,
clk_out3 => clk_48m,
clk_out4 => clk_24m,
reset => reset,
locked => locked
);
mmcm_1_i : mmcm_1 port map (
clk_in1 => clk_50m,
clk_out1 => clk_78_571m,
reset => reset
);
o_clk_phy <= clk_240m;
o_clk <= clk_24m;
o_clk_x2 <= clk_48m;
i_clk <= clk_78_571m;
end Behavioural;
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