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* move fpga to fpga directoryroot2025-04-3038-4433/+0
* add phase slip tidyroot2025-04-307-106/+104
* shimmeringroot2025-04-308-31/+137
* working build for bothJames McKenzie2025-04-301-1/+6
* workingroot2025-04-302-8/+2
* workingroot2025-04-301-12/+12
* workingroot2025-04-303-20/+55
* hdmi almost workingroot2025-04-299-64/+124
* build everything all at onceroot2025-04-298-78/+345
* possibly working bothJames McKenzie2025-04-284-108/+109
* c4 hdmiJames McKenzie2025-04-282-0/+544
* c4 hdmiJames McKenzie2025-04-288-209/+125
* tidyJames McKenzie2025-04-283-44/+44
* tidyJames McKenzie2025-04-282-37/+37
* cyclone4 first stepsJames McKenzie2025-04-2815-40/+743
* move vram to moduleJames McKenzie2025-04-285-2/+38
* tidyJames McKenzie2025-04-288-187/+188
* tidyJames McKenzie2025-04-289-228/+255
* finished input stageJames McKenzie2025-04-272-0/+941
* finished input stageJames McKenzie2025-04-279-675/+137
* tidyJames McKenzie2025-04-278-455/+457
* meets timingJames McKenzie2025-04-274-102/+74
* note quite workingJames McKenzie2025-04-273-25/+75
* note quite workingJames McKenzie2025-04-2710-96/+628
* after tidyJames McKenzie2025-04-2610-749/+563
* before tidyJames McKenzie2025-04-2614-109/+1481
* first cut at spartan 6 fpgaJames McKenzie2025-04-268-0/+595
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-19 02:36:11 +0000