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-rw-r--r--spartan6/hp_lcd_driver/clkgen_cyclone4_impl.vhdl36
-rw-r--r--spartan6/hp_lcd_driver/ep4ce15.cfg11
-rw-r--r--spartan6/hp_lcd_driver/hp_lcd_driver.ep4ce15_qsft95
-rw-r--r--spartan6/hp_lcd_driver/hp_lcd_driver.vhdl6
-rw-r--r--spartan6/hp_lcd_driver/output_formatter.vhdl2
-rw-r--r--spartan6/hp_lcd_driver/output_stage.vhdl8
-rwxr-xr-xspartan6/hp_lcd_driver/prog14
-rw-r--r--spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl6
-rw-r--r--spartan6/hp_lcd_driver/tmds_phy_cyclone4.vhdl10
9 files changed, 124 insertions, 64 deletions
diff --git a/spartan6/hp_lcd_driver/clkgen_cyclone4_impl.vhdl b/spartan6/hp_lcd_driver/clkgen_cyclone4_impl.vhdl
index f9c4797..5a60e85 100644
--- a/spartan6/hp_lcd_driver/clkgen_cyclone4_impl.vhdl
+++ b/spartan6/hp_lcd_driver/clkgen_cyclone4_impl.vhdl
@@ -164,21 +164,21 @@ BEGIN
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
- clk0_divide_by => 1,
+ clk0_divide_by => 5,
clk0_duty_cycle => 50,
- clk0_multiply_by => 2,
+ clk0_multiply_by => 12,
clk0_phase_shift => "0",
clk1_divide_by => 5,
clk1_duty_cycle => 50,
clk1_multiply_by => 8,
clk1_phase_shift => "0",
- clk2_divide_by => 5,
+ clk2_divide_by => 25,
clk2_duty_cycle => 50,
- clk2_multiply_by => 4,
+ clk2_multiply_by => 24,
clk2_phase_shift => "0",
- clk3_divide_by => 5,
+ clk3_divide_by => 25,
clk3_duty_cycle => 50,
- clk3_multiply_by => 2,
+ clk3_multiply_by => 12,
clk3_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
@@ -269,10 +269,10 @@ END SYN;
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "120.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "80.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "40.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "20.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "48.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "24.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -306,10 +306,10 @@ END SYN;
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "80.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "40.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "48.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "24.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
@@ -369,21 +369,21 @@ END SYN;
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "12"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "24"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "12"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
diff --git a/spartan6/hp_lcd_driver/ep4ce15.cfg b/spartan6/hp_lcd_driver/ep4ce15.cfg
new file mode 100644
index 0000000..28de10c
--- /dev/null
+++ b/spartan6/hp_lcd_driver/ep4ce15.cfg
@@ -0,0 +1,11 @@
+interface usb_blaster
+usb_blaster_lowlevel_driver ftdi
+set CHIPNAME ep4ce15
+set FPGA_TAPID 0x020f20dd
+
+jtag newtap $CHIPNAME tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-id $FPGA_TAPID
+
+init
+scan_chain
+svf -tap $CHIPNAME.tap ./build_ep4ce15/hp_lcd_driver.svf
+exit
diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.ep4ce15_qsft b/spartan6/hp_lcd_driver/hp_lcd_driver.ep4ce15_qsft
index 93c6e74..a39658f 100644
--- a/spartan6/hp_lcd_driver/hp_lcd_driver.ep4ce15_qsft
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.ep4ce15_qsft
@@ -19,41 +19,66 @@ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-#set_location_assignment PIN_T22 -to clk_50m
-#set_location_assignment PIN_U20 -to sys_rst_n
-#
-#set_location_assignment PIN_H21 -to hdmi_c_p
-#set_location_assignment PIN_H22 -to hdmi_c_n
-#
-#set_location_assignment PIN_F21 -to hdmi_r_p
-#set_location_assignment PIN_F22 -to hdmi_r_n
-#
-#set_location_assignment PIN_E21 -to hdmi_g_p
-#set_location_assignment PIN_E22 -to hdmi_g_n
-#
-#set_location_assignment PIN_D21 -to hdmi_b_p
-#set_location_assignment PIN_D22 -to hdmi_b_n
-#
-#
-#set_location_assignment PIN_AB17 -to vsync_out
-#set_location_assignment PIN_AA18 -to hsync_out
-#
-#set_location_assignment PIN_J21 -to r_out
-##set_location_assignment PIN_K21 -to rgb[14]
-##set_location_assignment PIN_L22 -to rgb[13]
-##set_location_assignment PIN_L21 -to rgb[12]
-##set_location_assignment PIN_M22 -to rgb[11]
-#set_location_assignment PIN_M21 -to g_out
-##set_location_assignment PIN_N21 -to rgb[9]
-##set_location_assignment PIN_N20 -to rgb[8]
-##set_location_assignment PIN_U22 -to rgb[7]
-##set_location_assignment PIN_U21 -to rgb[6]
-##set_location_assignment PIN_W20 -to rgb[5]
-#set_location_assignment PIN_W19 -to b_out
-##set_location_assignment PIN_Y21 -to rgb[3]
-##set_location_assignment PIN_AB19 -to rgb[2]
-##set_location_assignment PIN_AA19 -to rgb[1]
-##set_location_assignment PIN_AB18 -to rgb[0]
+set_location_assignment PIN_T22 -to clk_50m
+set_location_assignment PIN_U20 -to sys_rst_n
+
+set_location_assignment PIN_AB17 -to vsync_out
+set_location_assignment PIN_AA18 -to hsync_out
+
+set_location_assignment PIN_J21 -to r_out
+set_instance_assignment -name IO_STANDARD "2.5 V" -to r_out
+#set_location_assignment PIN_K21 -to rgb[14]
+#set_location_assignment PIN_L22 -to rgb[13]
+#set_location_assignment PIN_L21 -to rgb[12]
+#set_location_assignment PIN_M22 -to rgb[11]
+set_location_assignment PIN_M21 -to g_out
+#set_location_assignment PIN_N21 -to rgb[9]
+#set_location_assignment PIN_N20 -to rgb[8]
+#set_location_assignment PIN_U22 -to rgb[7]
+#set_location_assignment PIN_U21 -to rgb[6]
+#set_location_assignment PIN_W20 -to rgb[5]
+set_location_assignment PIN_W19 -to b_out
+#set_location_assignment PIN_Y21 -to rgb[3]
+#set_location_assignment PIN_AB19 -to rgb[2]
+#set_location_assignment PIN_AA19 -to rgb[1]
+#set_location_assignment PIN_AB18 -to rgb[0]
+
+
+
+set_location_assignment PIN_H21 -to hdmi_c_p
+set_location_assignment PIN_H22 -to hdmi_c_n
+set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_c_p
+set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_c_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_c_p
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_c_n
+
+set_location_assignment PIN_F21 -to hdmi_r_p
+set_location_assignment PIN_F22 -to hdmi_r_n
+set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_r_p
+set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_r_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_r_p
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_r_n
+
+set_location_assignment PIN_E21 -to hdmi_g_p
+set_location_assignment PIN_E22 -to hdmi_g_n
+set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_g_p
+set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_g_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_g_p
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_g_n
+
+set_location_assignment PIN_D21 -to hdmi_b_p
+set_location_assignment PIN_D22 -to hdmi_b_n
+set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_b_p
+set_instance_assignment -name IO_STANDARD "2.5 V" -to hdmi_b_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_b_p
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to hdmi_b_n
+
+
+set_location_assignment PIN_A10 -to hsync_in
+set_location_assignment PIN_C10 -to vsync_in
+set_location_assignment PIN_A13 -to video[0]
+set_location_assignment PIN_C13 -to video[1]
+
diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
index a16b193..51d5c38 100644
--- a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -111,8 +111,10 @@ begin
g <= x"ff" when rd_data(0) = '1' else
x"ff" when rd_data(1) = '1' else
x"00";
- b <= x"ff" when rd_data(1) = '1' else
- x"00";
+ --b <= x"ff" when rd_data(1) = '1' else
+ -- x"00";
+
+ b<=x"ff";
diff --git a/spartan6/hp_lcd_driver/output_formatter.vhdl b/spartan6/hp_lcd_driver/output_formatter.vhdl
index 32e16c0..f490c8b 100644
--- a/spartan6/hp_lcd_driver/output_formatter.vhdl
+++ b/spartan6/hp_lcd_driver/output_formatter.vhdl
@@ -69,7 +69,7 @@ begin
if v /= (v_total-1) then
v <= v+1;
h <= 0;
- elsif vsync_in_ne = '1' then
+ else --if vsync_in_ne = '1' then
h <= 0;
v <= 0;
end if;
diff --git a/spartan6/hp_lcd_driver/output_stage.vhdl b/spartan6/hp_lcd_driver/output_stage.vhdl
index 8dc91ae..19e9d35 100644
--- a/spartan6/hp_lcd_driver/output_stage.vhdl
+++ b/spartan6/hp_lcd_driver/output_stage.vhdl
@@ -175,12 +175,12 @@ begin
tmds_c_out_p => hdmi_c_p,
tmds_c_out_n => hdmi_c_n,
- tmds_r_out_p => hdmi_r_p,
- tmds_r_out_n => hdmi_r_n,
+ tmds_r_out_p => hdmi_b_p,
+ tmds_r_out_n => hdmi_b_n,
tmds_g_out_p => hdmi_g_p,
tmds_g_out_n => hdmi_g_n,
- tmds_b_out_p => hdmi_b_p,
- tmds_b_out_n => hdmi_b_n
+ tmds_b_out_p => hdmi_r_p,
+ tmds_b_out_n => hdmi_r_n
);
diff --git a/spartan6/hp_lcd_driver/prog b/spartan6/hp_lcd_driver/prog
new file mode 100755
index 0000000..a637b38
--- /dev/null
+++ b/spartan6/hp_lcd_driver/prog
@@ -0,0 +1,14 @@
+#!/bin/bash
+
+SOF=output_files/vga_colorbar.sof
+SVF=vga_colorbar.svf
+RBF=vga_colorbar.rbf
+run_quartus quartus_cpf -c -q 1MHZ -g 3.3 -n p ${SOF} ${SVF}
+#run_quartus quartus_cpf -c ${SOF} ${RBF}
+
+#OPENOCD="/root/projects/hp_instrument_lcds/fpga/prefix/bin/openocd -f interface/altera-usb-blaster.cfg -f fpga/altera-cycloneiv.cfg"
+#${OPENOCD} -c "init; pld load cycloneiv.pld vga_colorbar.rbf; shutdown; quit"
+
+OPENOCD="/root/projects/hp_instrument_lcds/fpga/prefix/bin/openocd -f interface/altera-usb-blaster.cfg -f ep4ce15.cfg"
+${OPENOCD} -c quit
+
diff --git a/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl b/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl
index fe3f850..1421211 100644
--- a/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl
+++ b/spartan6/hp_lcd_driver/tmds_output_cyclone4.vhdl
@@ -30,7 +30,7 @@ end tmds_output;
architecture beh of tmds_output is
- signal b : natural;
+ signal b : natural:=0;
begin
@@ -38,10 +38,10 @@ begin
process (pclk_phy, b, sys_rst_n)
begin
- if sys_rst_n = '1' then
+ if sys_rst_n = '0' then
b <=0;
elsif rising_edge(pclk_phy) then
- if b = 5 then
+ if b = 4 then
b <=0;
else
b <=b+1;
diff --git a/spartan6/hp_lcd_driver/tmds_phy_cyclone4.vhdl b/spartan6/hp_lcd_driver/tmds_phy_cyclone4.vhdl
index d4801c5..bd4835e 100644
--- a/spartan6/hp_lcd_driver/tmds_phy_cyclone4.vhdl
+++ b/spartan6/hp_lcd_driver/tmds_phy_cyclone4.vhdl
@@ -19,20 +19,26 @@ end tmds_phy_cyclone4;
architecture beh of tmds_phy_cyclone4 is
+
signal d_rise : std_logic_vector(4 downto 0);
signal d_fall : std_logic_vector(4 downto 0);
signal out_p : std_logic_vector(0 downto 0);
signal out_n : std_logic_vector(0 downto 0);
+signal bb:natural;
+
begin
+
process (pclk_phy)
begin
if rising_edge(pclk_phy) then
- if b = 5 then
+ if b = 4 then
d_rise <= (4 => din(8), 3 => din(6), 2 => din(4), 1 => din(2), 0 => din(0));
d_fall <= (4 => din(9), 3 => din(7), 2 => din(5), 1 => din(3), 0 => din(1));
+ --d_rise <= (4 => din(1), 3 => din(3), 2 => din(5), 1 => din(7), 0 => din(9));
+ --d_fall <= (4 => din(0), 3 => din(2), 2 => din(4), 1 => din(6), 0 => din(8));
else
d_rise(3 downto 0) <= d_rise(4 downto 1);
d_fall(3 downto 0) <= d_fall(4 downto 1);
@@ -40,6 +46,7 @@ begin
end if;
end process;
+
obuf_p : ALTDDIO_OUT
generic map (
extend_oe_disable => "OFF",
@@ -80,4 +87,5 @@ begin
);
tmds_out_n <= out_n(0);
+
end beh;
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-12 20:31:53 +0000