diff options
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7_ip/fifo_generator_0.tcl | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/fpga/hp_lcd_driver/zynq7_ip/fifo_generator_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/fifo_generator_0.tcl new file mode 100644 index 0000000..77d7a52 --- /dev/null +++ b/fpga/hp_lcd_driver/zynq7_ip/fifo_generator_0.tcl @@ -0,0 +1,27 @@ +set source_dir [file dirname [file dirname [file normalize [info script]]]] + +source $source_dir/zynq7_config.tcl + +create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name fifo_generator_0 + +set_property -dict [list \ + CONFIG.Performance_Options {First_Word_Fall_Through} \ + CONFIG.Input_Data_Width {65} \ + CONFIG.Input_Depth {512} \ + CONFIG.Output_Data_Width {65} \ + CONFIG.Output_Depth {512} \ + CONFIG.Data_Count_Width {9} \ + CONFIG.Write_Data_Count_Width {9} \ + CONFIG.Read_Data_Count_Width {9} \ + CONFIG.Read_Clock_Frequency {100} \ + CONFIG.Write_Clock_Frequency {25} \ + CONFIG.Full_Threshold_Assert_Value {505} \ + CONFIG.Full_Threshold_Negate_Value {504} \ + CONFIG.Empty_Threshold_Assert_Value {6} \ + CONFIG.Empty_Threshold_Negate_Value {7} \ +] [get_ips fifo_generator_0] + +generate_target all [get_ips] + +synth_ip [get_ips] + |