diff options
Diffstat (limited to 'fpga/hp_lcd_driver')
36 files changed, 2164 insertions, 918 deletions
diff --git a/fpga/hp_lcd_driver/.gitignore b/fpga/hp_lcd_driver/.gitignore index 4284f6d..4b83774 100644 --- a/fpga/hp_lcd_driver/.gitignore +++ b/fpga/hp_lcd_driver/.gitignore @@ -7,3 +7,4 @@ NOT/ *.swp *.lic *.orig +build_ebaz4205 diff --git a/fpga/hp_lcd_driver/Makefile b/fpga/hp_lcd_driver/Makefile index 458951d..6b72967 100644 --- a/fpga/hp_lcd_driver/Makefile +++ b/fpga/hp_lcd_driver/Makefile @@ -1,8 +1,13 @@ -TARGETS= rando_a7 #smh-ac415b #spartan6 #ep4ce6 smh-ac415 +DIP=10.16.66.113 +TARGETS= ebaz4205 #rando_a7 #smh-ac415b #spartan6 #ep4ce6 smh-ac415 #fish:smh-ac415 -better_default: build_rando_a7/hp_lcd_driver.svf - ./prog_a7 +#better_default: build_rando_a7/hp_lcd_driver.svf +# ./prog_a7 + +better_default: ${TARGETS:%=build_%/hp_lcd_driver.svf} + scp build_ebaz4205/out/hp_lcd_driver.bin ${DIP}:/boot/uboot/hp_lcd_driver.bin + ssh -n ${DIP} reboot < /dev/null & default: ${TARGETS:%=build_%/hp_lcd_driver.svf} diff --git a/fpga/hp_lcd_driver/artix7.mk b/fpga/hp_lcd_driver/artix7.mk index 8c83e78..c20c11d 100644 --- a/fpga/hp_lcd_driver/artix7.mk +++ b/fpga/hp_lcd_driver/artix7.mk @@ -19,6 +19,7 @@ SRCS= ${IP} \ debounce.vhdl \ delay.vhdl \ edge_det.vhdl \ + common.vhdl \ hp_lcd_driver.vhdl \ input_formatter.vhdl \ input_stage.vhdl \ @@ -30,8 +31,7 @@ SRCS= ${IP} \ tmds_encode.vhdl \ tmds_output_artix7.vhdl \ tmds_phy_artix7.vhdl \ - vram_artix7.vhdl - + vram_artix7.vhdl OPENOCD=openocd -f openocd/${BOARD}.cfg @@ -51,3 +51,6 @@ ${BUILD}/ip/%/stamp:artix7_ip/%.tcl ${BIT}: ${BUILD}/build.stamp + +clean: + /bin/rm -rf ${BUILD} diff --git a/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl b/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl index 3859382..f1558ac 100644 --- a/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl +++ b/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl @@ -20,7 +20,7 @@ if {[llength $files] != 0} { #read_verilog [ glob ../source/*.v ] #read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ] -read_vhdl -vhdl2008 -library work { ../clkgen_artix7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../hp_lcd_driver.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl } +read_vhdl -vhdl2008 -library work { ../clkgen_artix7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../hp_lcd_driver.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl ../common.vhdl } set generics {} append generics { } "video_width=$video_width" diff --git a/fpga/hp_lcd_driver/clkgen_artix7.vhdl b/fpga/hp_lcd_driver/clkgen_artix7.vhdl index f7f8971..643b91f 100644 --- a/fpga/hp_lcd_driver/clkgen_artix7.vhdl +++ b/fpga/hp_lcd_driver/clkgen_artix7.vhdl @@ -19,7 +19,7 @@ entity clkgen is end clkgen; architecture Behavioural of clkgen is - signal clk_240m : std_logic; + signal clk_260m : std_logic; signal clk_78_571m : std_logic; signal clk_80m : std_logic; signal clk_24m : std_logic; @@ -38,7 +38,7 @@ begin mmcm_0_i : mmcm_0 port map ( clk_in1 => clk_50m, - clk_out1 => clk_240m, + clk_out1 => clk_260m, clk_out2 => clk_80m, clk_out3 => clk_48m, clk_out4 => clk_24m, @@ -52,7 +52,7 @@ begin reset => reset ); - o_clk_phy <= clk_240m; + o_clk_phy <= clk_260m; o_clk <= clk_24m; o_clk_x2 <= clk_48m; i_clk <= clk_78_571m; diff --git a/fpga/hp_lcd_driver/clkgen_cyclone4_a_impl.vhdl b/fpga/hp_lcd_driver/clkgen_cyclone4_a_impl.vhdl index 9a4bafa..2de5b04 100644 --- a/fpga/hp_lcd_driver/clkgen_cyclone4_a_impl.vhdl +++ b/fpga/hp_lcd_driver/clkgen_cyclone4_a_impl.vhdl @@ -6,10 +6,10 @@ -- ============================================================ -- File Name: clkgen_cyclone4_a_impl.vhd -- Megafunction Name(s): --- altpll +-- altpll -- -- Simulation Library Files(s): --- altera_mf +-- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! @@ -33,178 +33,178 @@ --applicable agreement for further details. -LIBRARY ieee; -USE ieee.std_logic_1164.all; +library ieee; +use ieee.std_logic_1164.all; -LIBRARY altera_mf; -USE altera_mf.all; +library altera_mf; +use altera_mf.all; -ENTITY clkgen_cyclone4_a_impl IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - locked : OUT STD_LOGIC - ); -END clkgen_cyclone4_a_impl; +entity clkgen_cyclone4_a_impl is + port + ( + areset : in std_logic := '0'; + inclk0 : in std_logic := '0'; + c0 : out std_logic; + locked : out std_logic + ); +end clkgen_cyclone4_a_impl; -ARCHITECTURE SYN OF clkgen_cyclone4_a_impl IS +architecture SYN of clkgen_cyclone4_a_impl is - SIGNAL sub_wire0 : STD_LOGIC ; - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + signal sub_wire0 : std_logic; + signal sub_wire1 : std_logic_vector (4 downto 0); + signal sub_wire2 : std_logic; + signal sub_wire3 : std_logic; + signal sub_wire4 : std_logic_vector (1 downto 0); + signal sub_wire5_bv : bit_vector (0 downto 0); + signal sub_wire5 : std_logic_vector (0 downto 0); - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - self_reset_on_loss_lock : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - locked : OUT STD_LOGIC - ); - END COMPONENT; + component altpll + generic ( + bandwidth_type : string; + clk0_divide_by : natural; + clk0_duty_cycle : natural; + clk0_multiply_by : natural; + clk0_phase_shift : string; + compensate_clock : string; + inclk0_input_frequency : natural; + intended_device_family : string; + lpm_hint : string; + lpm_type : string; + operation_mode : string; + pll_type : string; + port_activeclock : string; + port_areset : string; + port_clkbad0 : string; + port_clkbad1 : string; + port_clkloss : string; + port_clkswitch : string; + port_configupdate : string; + port_fbin : string; + port_inclk0 : string; + port_inclk1 : string; + port_locked : string; + port_pfdena : string; + port_phasecounterselect : string; + port_phasedone : string; + port_phasestep : string; + port_phaseupdown : string; + port_pllena : string; + port_scanaclr : string; + port_scanclk : string; + port_scanclkena : string; + port_scandata : string; + port_scandataout : string; + port_scandone : string; + port_scanread : string; + port_scanwrite : string; + port_clk0 : string; + port_clk1 : string; + port_clk2 : string; + port_clk3 : string; + port_clk4 : string; + port_clk5 : string; + port_clkena0 : string; + port_clkena1 : string; + port_clkena2 : string; + port_clkena3 : string; + port_clkena4 : string; + port_clkena5 : string; + port_extclk0 : string; + port_extclk1 : string; + port_extclk2 : string; + port_extclk3 : string; + self_reset_on_loss_lock : string; + width_clock : natural + ); + port ( + areset : in std_logic; + clk : out std_logic_vector (4 downto 0); + inclk : in std_logic_vector (1 downto 0); + locked : out std_logic + ); + end component; -BEGIN - sub_wire5_bv(0 DOWNTO 0) <= "0"; - sub_wire5 <= To_stdlogicvector(sub_wire5_bv); - locked <= sub_wire0; - sub_wire2 <= sub_wire1(0); - c0 <= sub_wire2; - sub_wire3 <= inclk0; - sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; +begin + sub_wire5_bv(0 downto 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + locked <= sub_wire0; + sub_wire2 <= sub_wire1(0); + c0 <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 downto 0) & sub_wire3; - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 25, - clk0_duty_cycle => 50, - clk0_multiply_by => 44, - clk0_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 20000, - intended_device_family => "Cyclone IV E", - lpm_hint => "CBX_MODULE_PREFIX=clkgen_cyclone4_a_impl", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_USED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_UNUSED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - self_reset_on_loss_lock => "ON", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire4, - locked => sub_wire0, - clk => sub_wire1 - ); + altpll_component : altpll + generic map ( + bandwidth_type => "AUTO", + clk0_divide_by => 25, + clk0_duty_cycle => 50, + clk0_multiply_by => 44, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + intended_device_family => "Cyclone IV E", + lpm_hint => "CBX_MODULE_PREFIX=clkgen_cyclone4_a_impl", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "ON", + width_clock => 5 + ) + port map ( + areset => areset, + inclk => sub_wire4, + locked => sub_wire0, + clk => sub_wire1 + ); -END SYN; +end SYN; -- ============================================================ -- CNX file retrieval info diff --git a/fpga/hp_lcd_driver/clkgen_cyclone4_b_impl.vhdl b/fpga/hp_lcd_driver/clkgen_cyclone4_b_impl.vhdl index 9a51b3a..3ba326a 100644 --- a/fpga/hp_lcd_driver/clkgen_cyclone4_b_impl.vhdl +++ b/fpga/hp_lcd_driver/clkgen_cyclone4_b_impl.vhdl @@ -6,10 +6,10 @@ -- ============================================================ -- File Name: clkgen_cyclone4_b_impl.vhd -- Megafunction Name(s): --- altpll +-- altpll -- -- Simulation Library Files(s): --- altera_mf +-- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! @@ -33,214 +33,214 @@ --applicable agreement for further details. -LIBRARY ieee; -USE ieee.std_logic_1164.all; +library ieee; +use ieee.std_logic_1164.all; -LIBRARY altera_mf; -USE altera_mf.all; +library altera_mf; +use altera_mf.all; -ENTITY clkgen_cyclone4_b_impl IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC ; - locked : OUT STD_LOGIC - ); -END clkgen_cyclone4_b_impl; +entity clkgen_cyclone4_b_impl is + port + ( + areset : in std_logic := '0'; + inclk0 : in std_logic := '0'; + c0 : out std_logic; + c1 : out std_logic; + c2 : out std_logic; + c3 : out std_logic; + locked : out std_logic + ); +end clkgen_cyclone4_b_impl; -ARCHITECTURE SYN OF clkgen_cyclone4_b_impl IS +architecture SYN of clkgen_cyclone4_b_impl is - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC ; - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); + signal sub_wire0 : std_logic_vector (4 downto 0); + signal sub_wire1 : std_logic; + signal sub_wire2 : std_logic; + signal sub_wire3 : std_logic; + signal sub_wire4 : std_logic; + signal sub_wire5 : std_logic; + signal sub_wire6 : std_logic; + signal sub_wire7 : std_logic_vector (1 downto 0); + signal sub_wire8_bv : bit_vector (0 downto 0); + signal sub_wire8 : std_logic_vector (0 downto 0); - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - self_reset_on_loss_lock : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - locked : OUT STD_LOGIC - ); - END COMPONENT; + component altpll + generic ( + bandwidth_type : string; + clk0_divide_by : natural; + clk0_duty_cycle : natural; + clk0_multiply_by : natural; + clk0_phase_shift : string; + clk1_divide_by : natural; + clk1_duty_cycle : natural; + clk1_multiply_by : natural; + clk1_phase_shift : string; + clk2_divide_by : natural; + clk2_duty_cycle : natural; + clk2_multiply_by : natural; + clk2_phase_shift : string; + clk3_divide_by : natural; + clk3_duty_cycle : natural; + clk3_multiply_by : natural; + clk3_phase_shift : string; + compensate_clock : string; + inclk0_input_frequency : natural; + intended_device_family : string; + lpm_hint : string; + lpm_type : string; + operation_mode : string; + pll_type : string; + port_activeclock : string; + port_areset : string; + port_clkbad0 : string; + port_clkbad1 : string; + port_clkloss : string; + port_clkswitch : string; + port_configupdate : string; + port_fbin : string; + port_inclk0 : string; + port_inclk1 : string; + port_locked : string; + port_pfdena : string; + port_phasecounterselect : string; + port_phasedone : string; + port_phasestep : string; + port_phaseupdown : string; + port_pllena : string; + port_scanaclr : string; + port_scanclk : string; + port_scanclkena : string; + port_scandata : string; + port_scandataout : string; + port_scandone : string; + port_scanread : string; + port_scanwrite : string; + port_clk0 : string; + port_clk1 : string; + port_clk2 : string; + port_clk3 : string; + port_clk4 : string; + port_clk5 : string; + port_clkena0 : string; + port_clkena1 : string; + port_clkena2 : string; + port_clkena3 : string; + port_clkena4 : string; + port_clkena5 : string; + port_extclk0 : string; + port_extclk1 : string; + port_extclk2 : string; + port_extclk3 : string; + self_reset_on_loss_lock : string; + width_clock : natural + ); + port ( + areset : in std_logic; + clk : out std_logic_vector (4 downto 0); + inclk : in std_logic_vector (1 downto 0); + locked : out std_logic + ); + end component; -BEGIN - sub_wire8_bv(0 DOWNTO 0) <= "0"; - sub_wire8 <= To_stdlogicvector(sub_wire8_bv); - sub_wire5 <= sub_wire0(2); - sub_wire4 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - locked <= sub_wire3; - c0 <= sub_wire4; - c2 <= sub_wire5; - sub_wire6 <= inclk0; - sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; +begin + sub_wire8_bv(0 downto 0) <= "0"; + sub_wire8 <= To_stdlogicvector(sub_wire8_bv); + sub_wire5 <= sub_wire0(2); + sub_wire4 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + locked <= sub_wire3; + c0 <= sub_wire4; + c2 <= sub_wire5; + sub_wire6 <= inclk0; + sub_wire7 <= sub_wire8(0 downto 0) & sub_wire6; - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 5, - clk0_duty_cycle => 50, - clk0_multiply_by => 12, - clk0_phase_shift => "0", - clk1_divide_by => 5, - clk1_duty_cycle => 50, - clk1_multiply_by => 8, - clk1_phase_shift => "0", - clk2_divide_by => 25, - clk2_duty_cycle => 50, - clk2_multiply_by => 24, - clk2_phase_shift => "0", - clk3_divide_by => 25, - clk3_duty_cycle => 50, - clk3_multiply_by => 12, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 20000, - intended_device_family => "Cyclone IV E", - lpm_hint => "CBX_MODULE_PREFIX=clkgen_cyclone4_b_impl", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_USED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - self_reset_on_loss_lock => "ON", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire7, - clk => sub_wire0, - locked => sub_wire3 - ); + altpll_component : altpll + generic map ( + bandwidth_type => "AUTO", + clk0_divide_by => 5, + clk0_duty_cycle => 50, + clk0_multiply_by => 12, + clk0_phase_shift => "0", + clk1_divide_by => 5, + clk1_duty_cycle => 50, + clk1_multiply_by => 8, + clk1_phase_shift => "0", + clk2_divide_by => 25, + clk2_duty_cycle => 50, + clk2_multiply_by => 24, + clk2_phase_shift => "0", + clk3_divide_by => 25, + clk3_duty_cycle => 50, + clk3_multiply_by => 12, + clk3_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + intended_device_family => "Cyclone IV E", + lpm_hint => "CBX_MODULE_PREFIX=clkgen_cyclone4_b_impl", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "ON", + width_clock => 5 + ) + port map ( + areset => areset, + inclk => sub_wire7, + clk => sub_wire0, + locked => sub_wire3 + ); -END SYN; +end SYN; -- ============================================================ -- CNX file retrieval info diff --git a/fpga/hp_lcd_driver/clkgen_spartan6.vhdl b/fpga/hp_lcd_driver/clkgen_spartan6.vhdl index 555ef9e..474879a 100644 --- a/fpga/hp_lcd_driver/clkgen_spartan6.vhdl +++ b/fpga/hp_lcd_driver/clkgen_spartan6.vhdl @@ -21,11 +21,11 @@ architecture Behavioural of clkgen is signal clkfbout1 : std_logic; signal clkfbout2 : std_logic; - signal clk_200m : std_logic; - signal clk_80m : std_logic; - signal clk_78_571m : std_logic; - signal clk_40m : std_logic; - signal clk_20m : std_logic; + signal clk_200m : std_logic; + signal clk_80m : std_logic; + signal clk_78_571m : std_logic; + signal clk_40m : std_logic; + signal clk_20m : std_logic; signal pll_locked1 : std_logic; signal pll_locked2 : std_logic; diff --git a/fpga/hp_lcd_driver/common.vhdl b/fpga/hp_lcd_driver/common.vhdl new file mode 100644 index 0000000..7275184 --- /dev/null +++ b/fpga/hp_lcd_driver/common.vhdl @@ -0,0 +1,381 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.all; + +-- on the cyclone iv +-- i_clk/4 = 19.676158 +-- the scope's pixel clock is 19.66080 +-- (p-0.25)*19.66080 = p * 19.676158 +--p=1/[4*(1-(19.676158/19.66080))]=320.04 + + +entity common is + generic (input_video_width : natural := 2; + video_width : natural := 2; + addr_width : natural := 18; + phase_slip : natural := 320; + i_clk_multiple : natural := 4; + use_pclk : natural := 0; + target : string := "artix7"); + port (clk_50m : in std_logic; + sys_rst_n : in std_logic; + video : in std_logic_vector(input_video_width -1 downto 0); + hsync_in : in std_logic; + vsync_in : in std_logic; + pclk_in : in std_logic; + r_out : out std_logic; + b_out : out std_logic; + g_out : out std_logic; + hsync_out : out std_logic; + vsync_out : out std_logic; + hdmi_c_p : out std_logic; + hdmi_c_n : out std_logic; + hdmi_r_p : out std_logic; + hdmi_r_n : out std_logic; + hdmi_g_p : out std_logic; + hdmi_g_n : out std_logic; + hdmi_b_p : out std_logic; + hdmi_b_n : out std_logic; + hdmi_vcc : out std_logic; + i_clk_out : out std_logic; + led : out std_logic; + video_out_data : out std_logic_vector(video_width-1 downto 0); + video_out_valid : out std_logic; + video_out_clk : out std_logic; + video_out_index : out std_logic + ); + +end common; + +architecture Behavioral of common is + + signal video_lut : std_logic_vector (video_width-1 downto 0); + signal wr_addr : std_logic_vector(addr_width-1 downto 0); + signal wr_data : std_logic_vector(video_width-1 downto 0); + signal wr_data_b : std_logic_vector(video_width-1 downto 0); + signal wr_en : std_logic; + + signal rd_addr : std_logic_vector(addr_width-1 downto 0); + signal rd_data : std_logic_vector(video_width-1 downto 0); + + signal r : std_logic_vector(7 downto 0); + signal g : std_logic_vector(7 downto 0); + signal b : std_logic_vector(7 downto 0); + + + signal clk_locked : std_logic; + + signal i_clk : std_logic; + + signal o_clk : std_logic; + signal o_clk_x2 : std_logic; + signal o_clk_phy : std_logic; + signal sys_rst : std_logic; + + signal pa : natural; + signal epk : std_logic; + signal ic : natural; + + + signal h : natural; + signal v : natural; + + + signal c : natural; + signal t : std_logic; + + signal wr_index : std_logic; + +begin + + +-- clocking: +-- i_clk is 4*(nominal) 20MHz to give us 4 choices of sampling position +-- o_clk is the output pixel clock +-- o_clk_x2 is used by the spartan serdes +-- o_clk_phy is used the the hdmi phy (cylone4 it's o_clk x5, spartan 6 it's o_clk x 10) + + clkgen : entity work.clkgen + port map ( + sys_rst_n => sys_rst_n, + clk_in => clk_50m, + i_clk => i_clk, + o_clk => o_clk, + o_clk_x2 => o_clk_x2, + o_clk_phy => o_clk_phy, + locked => clk_locked + ); + + + video_lut <= "1111" when video(0) = '1' else + "1011" when video(1) = '1' else + "1100" when video(2) = '1' else + "1010" when video(3) = '1' else + "0011" when video(4) = '1' else + "1110" when video(5) = '1' else + "1001" when video(6) = '1' else + "1101" when video(7) = '1' else + "0000"; + + hdmi_vcc <= '1'; + + + process (i_clk, sys_rst_n) + begin + if sys_rst_n = '0' then + ic <= 0; + pa <= phase_slip; + epk <= '0'; + elsif rising_edge(i_clk) then + + if ic = 0 then + epk <= '1'; + if pa = 0 then + pa <= phase_slip; + ic <= i_clk_multiple; + else + ic <= i_clk_multiple-1; + pa <= pa -1; + end if; + else + if epk = '1' then + epk <= '0'; + end if; + ic <= ic-1; + end if; + end if; + end process; + + + i_clk_out <= epk; + + + input0 : entity work.input_stage + generic map( + video_width => video_width, + addr_width => addr_width, + clk_multiple => i_clk_multiple, +-- HP54502A +-- phase => 1, +-- h_front_porch => 200, +-- h_active => 592, +-- v_front_porch => 1, +-- v_active => 384, +-- frame_start => 383, +-- h_stride => 384, +-- v_stride => 262143, +-- HP54522A + phase => 1, + h_front_porch => 190, + h_active => 640, + v_front_porch => 22, + v_active => 384, + frame_start => 383, + h_stride => 384, + v_stride => 524287, + phase_slip => phase_slip, + use_pclk => use_pclk + ) + port map ( + sys_rst_n => sys_rst_n, + clk => i_clk, + video_in => video_lut, + pclk_in => pclk_in, + hsync_in => not hsync_in, + vsync_in => not vsync_in, + + video_out => wr_data, + addr_out => wr_addr, + wren_out => wr_en, + index_out => wr_index + ); + + video_out_data <= wr_data; + video_out_valid <= wr_en; + video_out_index <= wr_index; + video_out_clk <= i_clk; + + + +-- +-- process (i_clk) begin +-- if sys_rst_n='0' then +-- h<=0; +-- v<=0; +-- wr_addr <=(others =>'0'); +-- elsif rising_edge(i_clk) then +-- if h /= 383 then +-- h<=h+1; +-- wr_addr <= std_logic_vector(unsigned(wr_addr)+1); +-- else +-- h<=0; +-- if v /= 591 then +-- v<=v+1; +-- wr_addr <= std_logic_vector(unsigned(wr_addr)+1); +-- else +-- v<=0; +-- wr_addr <=(others =>'0'); +-- end if; +-- end if; +-- end if; +-- end process; +-- +-- wr_en <= '1'; +-- +-- wr_data <="01" when (h=0) or (h=383) or (v=0) or (v=591) +-- else "00"; +-- + + vram0 : entity work.vram + generic map ( + video_width => video_width, + addr_width => addr_width + ) + port map ( + wr_clk => i_clk, + wr_en => wr_en, + wr_addr => wr_addr, + wr_data => wr_data, + rd_clk => o_clk, + rd_addr => rd_addr, + rd_data => rd_data + ); + + + +-- r<=x"00"; +-- b<=x"00"; + + + + + r <= x"ff" when rd_data(0) = '1' else + x"00"; + +-- r<=x"ff" when rd_data(0)='1' and rd_data(3)='1' else +-- x"80" when rd_data(0)='1' else +-- x"00"; + + g <= x"ff" when rd_data(1) = '1' and rd_data(3) = '1' else + x"80" when rd_data(1) = '1' else + x"00"; + b <= x"ff" when rd_data(2) = '1' and rd_data(3) = '1' else + x"80" when rd_data(2) = '1' else + x"00"; + + + +--"ff" when rd_data(1) = '1' else +-- x"80" when rd_data(0) = '1' else +-- ix"00"; + + + + + output0 : entity work.output_stage + +-- didn't work for me from this thing, only from mac, works at 60Hz xrandr --newmode "$M" 18.24 384 400 440 600 592 593 596 613 -HSync +Vsync +-- Modeline "384x592_80.00" 25.40 384 408 448 512 592 593 596 620 -HSync +Vsync + + generic map ( + target => target, + addr_width => addr_width, +-- h_active => 384, +-- h_sync_start => 400, +-- h_sync_end => 440, +-- h_total => 640, +-- v_active => 592, +-- v_sync_start => 593, +-- v_sync_end => 596, +-- v_total => 613, +-- h_stride => 1, +-- v_stride => 384 + +-- HP54502A +-- h_active => 384, +-- h_sync_start => 400, +-- h_sync_end => 440, +-- h_total => 660, +-- v_active => 592, +-- v_sync_start => 593, +-- v_sync_end => 596, +-- v_total => 613, +-- h_stride => 1, +-- v_stride => 384 + +-- HP54522A + h_active => 384, + h_sync_start => 400, + h_sync_end => 456, + h_total => 660, +-- h_active => 417, +-- h_sync_start => 440, +-- h_sync_end => 480, +-- h_total => 660, + v_active => 640, + v_sync_start => 641, + v_sync_end => 644, + v_total => 650, + h_stride => 1, + v_stride => 384 + +-- h_active => 640, +-- h_sync_start=>656, +-- h_sync_end =>752, +-- h_total=>800, +-- +-- v_active =>480, +-- v_sync_start=>490, +-- v_sync_end=>492, +-- v_total=>525, +-- h_stride=>1, +-- v_stride=>384 + + ) + + port map( + clk_locked => clk_locked, + clk => o_clk, + clk_x2 => o_clk_x2, + clk_phy => o_clk_phy, + sys_rst_n => sys_rst_n, + vsync_in => not vsync_in, + r_in => r, + g_in => g, + b_in => b, + addr_out => rd_addr, + r_out => r_out, + g_out => g_out, + b_out => b_out, + hsync_out => hsync_out, + vsync_out => vsync_out, + hdmi_c_p => hdmi_c_p, + hdmi_c_n => hdmi_c_n, + hdmi_r_p => hdmi_r_p, + hdmi_r_n => hdmi_r_n, + hdmi_g_p => hdmi_g_p, + hdmi_g_n => hdmi_g_n, + hdmi_b_p => hdmi_b_p, + hdmi_b_n => hdmi_b_n + ); + + process (clk_50m, c) + begin + if rising_edge(clk_50m) then + + if c < 19999999 then + c <= c+1; + else + c <= 0; + t <= not t; + end if; + end if; + end process; + + + led <= t; + + +end Behavioral; + diff --git a/fpga/hp_lcd_driver/ebaz4205.mk b/fpga/hp_lcd_driver/ebaz4205.mk new file mode 100644 index 0000000..e6921b5 --- /dev/null +++ b/fpga/hp_lcd_driver/ebaz4205.mk @@ -0,0 +1,2 @@ +BOARD=ebaz4205 +include zynq7.mk diff --git a/fpga/hp_lcd_driver/ebaz4205.tcl b/fpga/hp_lcd_driver/ebaz4205.tcl new file mode 100644 index 0000000..025ac07 --- /dev/null +++ b/fpga/hp_lcd_driver/ebaz4205.tcl @@ -0,0 +1,6 @@ +# +set part_num "xc7z010clg400-1" +set normal_xdc "../ebaz4205.xdc" +set use_pclk 1 +set input_video_width 8 +set video_width 4 diff --git a/fpga/hp_lcd_driver/ebaz4205.xdc b/fpga/hp_lcd_driver/ebaz4205.xdc new file mode 100644 index 0000000..64660eb --- /dev/null +++ b/fpga/hp_lcd_driver/ebaz4205.xdc @@ -0,0 +1,216 @@ +# "Normal" constraints file- not early not late + +set_property PACKAGE_PIN U18 [get_ports {eth0_clk_o}] + +set_property PACKAGE_PIN U15 [get_ports {eth0_gmii_tx_clk_i}] +set_property PACKAGE_PIN W19 [get_ports {eth0_gmii_tx_en_o[0]}] +set_property PACKAGE_PIN W18 [get_ports {eth0_gmii_txd_o[0]}] +set_property PACKAGE_PIN Y18 [get_ports {eth0_gmii_txd_o[1]}] +set_property PACKAGE_PIN V18 [get_ports {eth0_gmii_txd_o[2]}] +set_property PACKAGE_PIN Y19 [get_ports {eth0_gmii_txd_o[3]}] + +set_property PACKAGE_PIN U14 [get_ports {eth0_gmii_rx_clk_i}] +set_property PACKAGE_PIN W16 [get_ports {eth0_gmii_rx_dv_i}] +set_property PACKAGE_PIN Y16 [get_ports {eth0_gmii_rxd_i[0]}] +set_property PACKAGE_PIN V16 [get_ports {eth0_gmii_rxd_i[1]}] +set_property PACKAGE_PIN V17 [get_ports {eth0_gmii_rxd_i[2]}] +set_property PACKAGE_PIN Y17 [get_ports {eth0_gmii_rxd_i[3]}] + + +set_property PACKAGE_PIN W15 [get_ports {eth0_mdio_mdc_o}] +set_property PACKAGE_PIN Y14 [get_ports {eth0_mdio_mdio_io}] + +set_property IOSTANDARD LVCMOS33 [get_ports eth0_*] + +set_property PACKAGE_PIN W13 [get_ports {green_led}] +set_property PACKAGE_PIN W14 [get_ports {red_led}] + +set_property IOSTANDARD LVCMOS33 [get_ports *_led] + +#set_property IOSTANDARD LVCMOS33 [get_ports clk_50m] +#set_property PACKAGE_PIN R4 [get_ports clk_50m] + +#set_property PACKAGE_PIN T1 [get_ports {led_1}] +#set_property IOSTANDARD LVCMOS33 [get_ports {led_1}] + +set_property PACKAGE_PIN G19 [get_ports {hdmi_b_p}]; #data2-5 +set_property PACKAGE_PIN G20 [get_ports {hdmi_b_n}]; #data2-7 +set_property PACKAGE_PIN K19 [get_ports {hdmi_g_p}]; #data2-13 +set_property PACKAGE_PIN J19 [get_ports {hdmi_g_n}]; #data2-9 +#set_property PACKAGE_PIN T20 [get_ports {hdmi_g_p}]; #data3-16 +#set_property PACKAGE_PIN U20 [get_ports {hdmi_g_n}]; #data3-17 +set_property PACKAGE_PIN L19 [get_ports {hdmi_r_p}]; #data2-16 +set_property PACKAGE_PIN L20 [get_ports {hdmi_r_n}]; #data2-18 +set_property PACKAGE_PIN L16 [get_ports {hdmi_c_p}]; #data2-15 +set_property PACKAGE_PIN L17 [get_ports {hdmi_c_n}]; #data2-20 +#set_property PACKAGE_PIN N17 [get_ports {hdmi_c_p}]; #data3-9 +#set_property PACKAGE_PIN P18 [get_ports {hdmi_c_n}]; #data3-7 + +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_p}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_n}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_p}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_n}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_p}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_n}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_p}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_n}] + +##set_property DRIVE 16 [get_ports {hdmi_c_p}] +##set_property DRIVE 16 [get_ports {hdmi_c_n}] +##set_property DRIVE 16 [get_ports {hdmi_r_p}] +##set_property DRIVE 16 [get_ports {hdmi_r_n}] +##set_property DRIVE 16 [get_ports {hdmi_g_p}] +##set_property DRIVE 16 [get_ports {hdmi_g_n}] +##set_property DRIVE 16 [get_ports {hdmi_b_p}] +# +set_property PACKAGE_PIN K18 [get_ports {hdmi_vcc}]; #data2-11 (12 is gnd) +set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_vcc}] +# +# +##set_property PACKAGE_PIN P20 [get_ports rxd] +##set_property PACKAGE_PIN T20 [get_ports txd] +##set_property IOSTANDARD LVCMOS33 [get_ports rxd] +##set_property IOSTANDARD LVCMOS33 [get_ports txd] +# +##set_property PACKAGE_PIN T3 [get_ports key] +##set_property IOSTANDARD LVCMOS33 [get_ports key] +# +set_property PACKAGE_PIN A20 [get_ports {video[0]}]; #data1-5 +set_property PACKAGE_PIN H16 [get_ports {video[1]}]; #data1-6 +set_property PACKAGE_PIN B19 [get_ports {video[2]}]; #data1-7 +set_property PACKAGE_PIN B20 [get_ports {video[3]}]; #data1-8 +set_property PACKAGE_PIN D20 [get_ports {video[4]}]; #data1-13 +set_property PACKAGE_PIN D18 [get_ports {video[5]}]; #data1-14 +set_property PACKAGE_PIN H18 [get_ports {video[6]}]; #data1-15 +set_property PACKAGE_PIN D19 [get_ports {video[7]}]; #data1-16 +## +set_property IOSTANDARD LVCMOS33 [get_ports {video[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {video[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {video[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {video[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {video[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {video[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {video[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {video[7]}] +# +set_property PACKAGE_PIN H17 [get_ports {pclk_in}]; #data1-11 (12 is gnd) + +set_property PACKAGE_PIN F19 [get_ports {vsync_in}]; #data1-19 +set_property PACKAGE_PIN K17 [get_ports {hsync_in}]; #data1-20 +# +#set_property PACKAGE_PIN P16 [get_ports {r_out}] +#set_property PACKAGE_PIN V18 [get_ports {g_out}] +#set_property PACKAGE_PIN P15 [get_ports {b_out}] +#set_property PACKAGE_PIN P14 [get_ports {i_clk_out}] +#set_property PACKAGE_PIN V17 [get_ports {hsync_out}] +#set_property PACKAGE_PIN N13 [get_ports {vsync_out}] +# +# +set_property IOSTANDARD LVCMOS33 [get_ports {pclk_in}] +set_property IOSTANDARD LVCMOS33 [get_ports {vsync_in}] +set_property IOSTANDARD LVCMOS33 [get_ports {hsync_in}] +#set_property IOSTANDARD LVCMOS33 [get_ports {r_out}] +#set_property IOSTANDARD LVCMOS33 [get_ports {g_out}] +#set_property IOSTANDARD LVCMOS33 [get_ports {b_out}] +#set_property IOSTANDARD LVCMOS33 [get_ports {i_clk_out}] +#set_property IOSTANDARD LVCMOS33 [get_ports {hsync_out}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vsync_out}] +# +#set_property PACKAGE_PIN AA18 [get_ports {sys_rst_n}] +#set_property IOSTANDARD LVCMOS33 [get_ports {sys_rst_n}] +#set_property PULLTYPE PULLUP [get_ports {sys_rst_n}] +# +#create_clock -period 20.000 -name pcie_clkin [get_ports clk_50m] +##set_false_path -from [get_ports pci_exp_rst_n] +# + +#set_false_path -from [get_clocks clk_out4_mmcm_0] -to [get_clocks clk_out1_mmcm_0] +# + + +exit + + + +############################################################################### +# Additional design / project settings +############################################################################### + +# Power down on overtemp +set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property BITSTREAM.CONFIG.USERID 32'hf00dbabe [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] + + +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + + +set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[*]/D}] 9 +set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[*]/D}] 9 +set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[*]/D}] 9 +set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[*]/D}] 9 + + + +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[0]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[0]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[0]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[0]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[0]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[0]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[0]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[0]/D}] +# +# +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[1]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[1]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[1]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[1]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[1]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[1]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[1]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[1]/D}] +# +# +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[2]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[2]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[2]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[2]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[2]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[2]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[2]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[2]/D}] +# +# +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[3]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[3]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[3]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[3]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[3]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[3]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[3]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[3]/D}] +# +# +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[4]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[4]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[4]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[4]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[4]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[4]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[4]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[4]/D}] +# +# +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[5]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[5]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[5]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[5]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[5]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[5]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[5]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[5]/D}] +# +# +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[6]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[6]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[6]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[6]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[6]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[6]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[6]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[6]/D}] +# +# +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[7]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[7]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[7]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[7]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[7]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[7]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[7]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[7]/D}] +# +# +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[8]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[8]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[8]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[8]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[8]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[8]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[8]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[8]/D}] +# +# +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[9]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[9]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[9]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[9]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[9]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[9]/D}] +#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[9]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[9]/D}] +# +# diff --git a/fpga/hp_lcd_driver/ep4ce15f23c8.mk b/fpga/hp_lcd_driver/ep4ce15f23c8.mk index 7597aad..33a825b 100644 --- a/fpga/hp_lcd_driver/ep4ce15f23c8.mk +++ b/fpga/hp_lcd_driver/ep4ce15f23c8.mk @@ -6,7 +6,7 @@ BUILD=build_${BOARD} OF=output_files PROJECT = hp_lcd_driver -VSRCS =delay.vhdl synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_phy_cyclone4.vhdl tmds_output_cyclone4.vhdl output_stage.vhdl clkgen_cyclone4.vhdl vram_cyclone4.vhdl hp_lcd_driver.vhdl +VSRCS =delay.vhdl synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_phy_cyclone4.vhdl tmds_output_cyclone4.vhdl output_stage.vhdl clkgen_cyclone4.vhdl vram_cyclone4.vhdl common.vhdl hp_lcd_driver.vhdl common.vhdl IPS= vram_cyclone4_impl.vhdl clkgen_cyclone4_a_impl.vhdl clkgen_cyclone4_b_impl.vhdl DESIGN_NAME=${TOP} diff --git a/fpga/hp_lcd_driver/fifo_to_axi.vhdl b/fpga/hp_lcd_driver/fifo_to_axi.vhdl new file mode 100644 index 0000000..c527ea1 --- /dev/null +++ b/fpga/hp_lcd_driver/fifo_to_axi.vhdl @@ -0,0 +1,107 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity fifo_to_axi is + generic ( + ADDR_WIDTH : integer := 32; + START : unsigned(31 downto 0) := x"FFFC0000"; + SIZE : unsigned(31 downto 0) := x"00040000" + ); + port ( + aclk : in std_logic; + aresetn : in std_logic; + + run : in std_logic; + + fifo_empty : in std_logic; + fifo_rdata : in std_logic_vector(64 downto 0); + fifo_rd_en : out std_logic; + + axi_awaddr : out std_logic_vector (ADDR_WIDTH-1 downto 0); + axi_awvalid : out std_logic; + axi_awready : in std_logic; + axi_wdata : out std_logic_vector (63 downto 0); + axi_wstrb : out std_logic_vector (7 downto 0); + axi_wvalid : out std_logic; + axi_wready : in std_logic; + axi_bvalid : in std_logic; + axi_bready : out std_logic + ); +end entity fifo_to_axi; + +architecture Behavioral of fifo_to_axi is + + --signal lazy : std_logic_vector(63 downto 0); + signal addr : std_logic_vector(ADDR_WIDTH-1 downto 0) := std_logic_vector(START); + signal data : std_logic_vector(63 downto 0); + signal do_bus_cycle : std_logic; + signal s_run : std_logic; + +begin + + + run_sync : entity work.synchronizer + generic map(stages => 2) + port map ( + clk => aclk, + i => run, + o => s_run + ); + + + + axi_bready <= do_bus_cycle; + axi_wdata <= data; + axi_wstrb <= (others => '1'); + axi_awaddr <= addr; + + --XXX this is moderately budget, it could do with a tonne of pipelining + + process (aclk) + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awvalid <= '0'; + axi_wvalid <= '0'; + do_bus_cycle <= '0'; + fifo_rd_en <= '0'; + addr <= std_logic_vector(START); + elsif run = '1' and do_bus_cycle = '1' then + fifo_rd_en <= '0'; + + if axi_bvalid = '1' then + do_bus_cycle <= '0'; + if addr /= std_logic_vector(START+SIZE-to_unsigned(8, ADDR_WIDTH)) then + addr <= std_logic_vector(unsigned(addr) +to_unsigned(8, ADDR_WIDTH)); + end if; + axi_awvalid <= '0'; + axi_wvalid <= '0'; + end if; + if axi_awready = '1' then + axi_awvalid <= '0'; + end if; + if axi_wready = '1' then + axi_wvalid <= '0'; + end if; + elsif do_bus_cycle = '0' then + + if fifo_empty = '0' then + data <= fifo_rdata (63 downto 0); + if fifo_rdata(64) = '1' then + addr <= std_logic_vector(START); + end if; + fifo_rd_en <= '1'; + do_bus_cycle <= '1'; + axi_awvalid <= '1'; + axi_wvalid <= '1'; + end if; + end if; + + end if; + + end process; + +end Behavioral; + + diff --git a/fpga/hp_lcd_driver/flash_loader.vhdl b/fpga/hp_lcd_driver/flash_loader.vhdl index 41eb1df..0315c25 100644 --- a/fpga/hp_lcd_driver/flash_loader.vhdl +++ b/fpga/hp_lcd_driver/flash_loader.vhdl @@ -6,10 +6,10 @@ -- ============================================================ -- File Name: flash_loader.vhd -- Megafunction Name(s): --- altserial_flash_loader +-- altserial_flash_loader -- -- Simulation Library Files(s): --- altera_mf +-- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! @@ -33,55 +33,55 @@ --applicable agreement for further details. -LIBRARY ieee; -USE ieee.std_logic_1164.all; +library ieee; +use ieee.std_logic_1164.all; -LIBRARY altera_mf; -USE altera_mf.all; +library altera_mf; +use altera_mf.all; -ENTITY flash_loader IS - PORT - ( - noe_in : IN STD_LOGIC - ); -END flash_loader; +entity flash_loader is + port + ( + noe_in : in std_logic + ); +end flash_loader; -ARCHITECTURE SYN OF flash_loader IS +architecture SYN of flash_loader is - COMPONENT altserial_flash_loader - GENERIC ( - enable_quad_spi_support : NATURAL; - enable_shared_access : STRING; - enhanced_mode : NATURAL; - intended_device_family : STRING; - lpm_type : STRING - ); - PORT ( - noe : IN STD_LOGIC - ); - END COMPONENT; + component altserial_flash_loader + generic ( + enable_quad_spi_support : natural; + enable_shared_access : string; + enhanced_mode : natural; + intended_device_family : string; + lpm_type : string + ); + port ( + noe : in std_logic + ); + end component; -BEGIN +begin - altserial_flash_loader_component : altserial_flash_loader - GENERIC MAP ( - enable_quad_spi_support => 0, - enable_shared_access => "OFF", - enhanced_mode => 1, - intended_device_family => "Cyclone IV E", - lpm_type => "altserial_flash_loader" - ) - PORT MAP ( - noe => noe_in - ); + altserial_flash_loader_component : altserial_flash_loader + generic map ( + enable_quad_spi_support => 0, + enable_shared_access => "OFF", + enhanced_mode => 1, + intended_device_family => "Cyclone IV E", + lpm_type => "altserial_flash_loader" + ) + port map ( + noe => noe_in + ); -END SYN; +end SYN; -- ============================================================ -- CNX file retrieval info diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl index f60e80e..15fe76f 100644 --- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl +++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl @@ -3,21 +3,14 @@ use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use work.all; --- on the cyclone iv --- i_clk/4 = 19.676158 --- the scope's pixel clock is 19.66080 --- (p-0.25)*19.66080 = p * 19.676158 ---p=1/[4*(1-(19.676158/19.66080))]=320.04 - - entity hp_lcd_driver is - generic (input_video_width : natural := 2; - video_width : natural :=2; - addr_width : natural := 18; - phase_slip : natural := 320; - i_clk_multiple : natural := 4; - use_pclk : natural := 0; - target : string := "artix7"); + generic (input_video_width : natural := 2; + video_width : natural := 2; + addr_width : natural := 18; + phase_slip : natural := 320; + i_clk_multiple : natural := 4; + use_pclk : natural := 0; + target : string := "artix7"); port (clk_50m : in std_logic; sys_rst_n : in std_logic; video : in std_logic_vector(input_video_width -1 downto 0); @@ -45,310 +38,43 @@ end hp_lcd_driver; architecture Behavioral of hp_lcd_driver is - signal video_lut : std_logic_vector (video_width-1 downto 0); - signal wr_addr : std_logic_vector(addr_width-1 downto 0); - signal wr_data : std_logic_vector(video_width-1 downto 0); - signal wr_data_b : std_logic_vector(video_width-1 downto 0); - signal wr_en : std_logic; - - signal rd_addr : std_logic_vector(addr_width-1 downto 0); - signal rd_data : std_logic_vector(video_width-1 downto 0); - signal rd_field : std_logic; - - signal r : std_logic_vector(7 downto 0); - signal g : std_logic_vector(7 downto 0); - signal b : std_logic_vector(7 downto 0); - - - signal clk_locked : std_logic; - - signal i_clk : std_logic; - - signal o_clk : std_logic; - signal o_clk_x2 : std_logic; - signal o_clk_phy : std_logic; - signal sys_rst : std_logic; - - signal pa : natural; - signal epk : std_logic; - signal ic : natural; - - - signal h : natural; - signal v : natural; - - - signal c : natural; - signal t : std_logic; - begin - --- clocking: --- i_clk is 4*(nominal) 20MHz to give us 4 choices of sampling position --- o_clk is the output pixel clock --- o_clk_x2 is used by the spartan serdes --- o_clk_phy is used the the hdmi phy (cylone4 it's o_clk x5, spartan 6 it's o_clk x 10) - - clkgen : entity work.clkgen - port map ( - sys_rst_n => sys_rst_n, - clk_in => clk_50m, - i_clk => i_clk, - o_clk => o_clk, - o_clk_x2 => o_clk_x2, - o_clk_phy => o_clk_phy, - locked => clk_locked - ); - - -video_lut<= (video(0),video(1),video(2) xor video(3),video(4),video(5),video(6) xor video(7)); - - - process (i_clk, sys_rst_n) - begin - if sys_rst_n = '0' then - ic <= 0; - pa <= phase_slip; - epk <= '0'; - elsif rising_edge(i_clk) then - - if ic = 0 then - epk <= '1'; - if pa = 0 then - pa <= phase_slip; - ic <= i_clk_multiple; - else - ic <= i_clk_multiple-1; - pa <= pa -1; - end if; - else - if epk = '1' then - epk <= '0'; - end if; - ic <= ic-1; - end if; - end if; - end process; - - - i_clk_out <= epk; - - - input0 : entity work.input_stage - generic map( - video_width => video_width, - addr_width => addr_width, - clk_multiple => i_clk_multiple, --- HP54502A --- phase => 1, --- h_front_porch => 200, --- h_active => 592, --- v_front_porch => 1, --- v_active => 384, --- frame_start => 383, --- h_stride => 384, --- v_stride => 262143, --- HP54522A - phase => 1, - h_front_porch => 190, - h_active => 640, - v_front_porch => 22, - v_active => 384, - frame_start => 383, - h_stride => 384, - v_stride => 524287, - phase_slip => phase_slip, - use_pclk => use_pclk - ) - port map ( - sys_rst_n => sys_rst_n, - clk => i_clk, - video_in => video_lut, - pclk_in => pclk_in, - hsync_in => not hsync_in, - vsync_in => not vsync_in, - - video_out => wr_data, - addr_out => wr_addr, - wren_out => wr_en - ); - --- --- process (i_clk) begin --- if sys_rst_n='0' then --- h<=0; --- v<=0; --- wr_addr <=(others =>'0'); --- elsif rising_edge(i_clk) then --- if h /= 383 then --- h<=h+1; --- wr_addr <= std_logic_vector(unsigned(wr_addr)+1); --- else --- h<=0; --- if v /= 591 then --- v<=v+1; --- wr_addr <= std_logic_vector(unsigned(wr_addr)+1); --- else --- v<=0; --- wr_addr <=(others =>'0'); --- end if; --- end if; --- end if; --- end process; --- --- wr_en <= '1'; --- --- wr_data <="01" when (h=0) or (h=383) or (v=0) or (v=591) --- else "00"; --- - - vram0 : entity work.vram - generic map ( - video_width => video_width, - addr_width => addr_width - ) - port map ( - wr_clk => i_clk, - wr_en => wr_en, - wr_addr => wr_addr, - wr_data => wr_data, - rd_clk => o_clk, - rd_addr => rd_addr, - rd_data => rd_data - ); - - - --- r<=x"00"; --- b<=x"00"; - - - r<= x"ff" when rd_data(0)='1' and rd_field='0' else - x"ff" when rd_data(3)='1' and rd_field='1' else - x"00"; - - g<= x"ff" when rd_data(1)='1' and rd_field='0' else - x"ff" when rd_data(4)='1' and rd_field='1' else - x"00"; - - b<= x"ff" when rd_data(2)='1' and rd_field='0' else - x"ff" when rd_data(5)='1' and rd_field='1' else - x"00"; - - - ---"ff" when rd_data(1) = '1' else --- x"80" when rd_data(0) = '1' else --- ix"00"; - - - - - output0 : entity work.output_stage - --- didn't work for me from this thing, only from mac, works at 60Hz xrandr --newmode "$M" 18.24 384 400 440 600 592 593 596 613 -HSync +Vsync --- Modeline "384x592_80.00" 25.40 384 408 448 512 592 593 596 620 -HSync +Vsync - + common_i : entity work.common generic map ( - target => target, - addr_width => addr_width, --- h_active => 384, --- h_sync_start => 400, --- h_sync_end => 440, --- h_total => 640, --- v_active => 592, --- v_sync_start => 593, --- v_sync_end => 596, --- v_total => 613, --- h_stride => 1, --- v_stride => 384 - --- HP54502A --- h_active => 384, --- h_sync_start => 400, --- h_sync_end => 440, --- h_total => 660, --- v_active => 592, --- v_sync_start => 593, --- v_sync_end => 596, --- v_total => 613, --- h_stride => 1, --- v_stride => 384 - --- HP54522A - h_active => 384, - h_sync_start => 400, - h_sync_end => 456, - h_total => 660, --- h_active => 417, --- h_sync_start => 440, --- h_sync_end => 480, --- h_total => 660, - v_active => 640, - v_sync_start => 641, - v_sync_end => 644, - v_total => 650, - h_stride => 1, - v_stride => 384 - --- h_active => 640, --- h_sync_start=>656, --- h_sync_end =>752, --- h_total=>800, --- --- v_active =>480, --- v_sync_start=>490, --- v_sync_end=>492, --- v_total=>525, --- h_stride=>1, --- v_stride=>384 - - ) - - port map( - clk_locked => clk_locked, - clk => o_clk, - clk_x2 => o_clk_x2, - clk_phy => o_clk_phy, - sys_rst_n => sys_rst_n, - vsync_in => not vsync_in, - r_in => r, - g_in => g, - b_in => b, - addr_out => rd_addr, - field_out => rd_field, - r_out => r_out, - g_out => g_out, - b_out => b_out, - hsync_out => hsync_out, - vsync_out => vsync_out, - hdmi_c_p => hdmi_c_p, - hdmi_c_n => hdmi_c_n, - hdmi_r_p => hdmi_r_p, - hdmi_r_n => hdmi_r_n, - hdmi_g_p => hdmi_g_p, - hdmi_g_n => hdmi_g_n, - hdmi_b_p => hdmi_b_p, - hdmi_b_n => hdmi_b_n - ); - - process (clk_50m, c) - begin - if rising_edge(clk_50m) then - - if c < 19999999 then - c <=c+1; - else - c <=0; - t <=not t; - end if; - end if; - end process; - - - led <= t; - - + input_video_width => input_video_width, + video_width => video_width, + addr_width => addr_width, + phase_slip => phase_slip, + i_clk_multiple => i_clk_multiple, + use_pclk => use_pclk, + target => target) + port map (clk_50m => clk_50m, + sys_rst_n => sys_rst_n, + video => video, + hsync_in => hsync_in, + vsync_in => vsync_in, + pclk_in => pclk_in, + r_out => r_out, + b_out => b_out, + g_out => g_out, + hsync_out => hsync_out, + vsync_out => vsync_out, + hdmi_c_p => hdmi_c_p, + hdmi_c_n => hdmi_c_n, + hdmi_r_p => hdmi_r_p, + hdmi_r_n => hdmi_r_n, + hdmi_g_p => hdmi_g_p, + hdmi_g_n => hdmi_g_n, + hdmi_b_p => hdmi_b_p, + hdmi_b_n => hdmi_b_n, + hdmi_vcc => hdmi_vcc, + i_clk_out => i_clk_out, + led => led, + video_out_clk => open, + video_out_index => open, + video_out_data => open, + video_out_valid => open + ); end Behavioral; diff --git a/fpga/hp_lcd_driver/input_formatter.vhdl b/fpga/hp_lcd_driver/input_formatter.vhdl index 7dbd07a..a2df32b 100644 --- a/fpga/hp_lcd_driver/input_formatter.vhdl +++ b/fpga/hp_lcd_driver/input_formatter.vhdl @@ -28,6 +28,7 @@ entity input_formatter is pclk : in std_logic; addr_out : out std_logic_vector(addr_width-1 downto 0); wren_out : out std_logic; + index_out : out std_logic; h_grid : out std_logic; v_grid : out std_logic ); @@ -37,6 +38,7 @@ end input_formatter; architecture beh of input_formatter is + signal row_addr : std_logic_vector(addr_width-1 downto 0); signal addr : std_logic_vector(addr_width-1 downto 0); signal wren : std_logic; @@ -45,6 +47,7 @@ architecture beh of input_formatter is signal hsync_ne : std_logic; signal hsync_pe : std_logic; + signal index : std_logic; signal v_fp_counter : natural; signal v_active_counter : natural; @@ -54,14 +57,6 @@ architecture beh of input_formatter is signal h_div : natural; signal phase_accum : natural; - signal ix:natural; - signal iy:natural; - signal ox:natural; - signal oy:natural; - signal oz:natural; - signal ow:natural; - - begin @@ -85,11 +80,14 @@ begin + addr_out <= addr; process (sys_rst_n, clk, hsync_pe, vsync) begin if sys_rst_n = '0' then + row_addr <= (others => '0'); + addr <= (others => '0'); h_div <= 0; h_active_counter <= 0; h_fp_counter <= 0; @@ -100,26 +98,26 @@ begin if hsync_pe = '1' then --if v_active_counter = 0 and v_fp_counter=0 then if vsync = '1' then + row_addr <= std_logic_vector(to_unsigned(frame_start, addr_width)); v_fp_counter <= v_front_porch; v_active_counter <= v_active; - iy<=0; + index <= '1'; elsif v_fp_counter /= 0 then v_fp_counter <= v_fp_counter -1; elsif v_active_counter /= 0 then v_active_counter <= v_active_counter -1; - iy<=iy+1; h_fp_counter <= h_front_porch * clk_multiple + phase; h_active_counter <= h_active; phase_accum <= phase_slip; h_div <= 0; - ix<=0; + addr <= row_addr; + row_addr <= std_logic_vector(unsigned(row_addr)+v_stride); end if; elsif h_fp_counter /= 0 then h_fp_counter <= h_fp_counter -1; elsif h_active_counter /= 0 then - if use_pclk = 0 then if h_div = 0 then wren <= '1'; @@ -135,44 +133,21 @@ begin wren <= '0'; end if; else - wren <= pclk_ne; + wren <= pclk_ne; end if; if wren = '1' then h_active_counter <= h_active_counter -1; - ix<=ix+1; + addr <= std_logic_vector(unsigned(addr)+h_stride); + index <= '0'; end if; end if; end if; end process; - - ow<=(ix+4*iy) mod 640; - oz<=0 when ow<320 - else 1; - ox<=ow mod 320; - oy<=iy*2 +oz; - - - - - process (sys_rst_n, clk, hsync_pe, vsync) - begin - if sys_rst_n = '0' then - addr<=( others =>'0'); - elsif rising_edge(clk) then - if oy<384 then - addr<= std_logic_vector(to_unsigned((ox*384) + (383-oy) ,addr'length)); - else - addr <= (others =>'0'); - end if; - end if; - end process; - - - - addr_out <= addr; - wren_out <= wren; + addr_out <= addr; + wren_out <= wren; + index_out <= index; h_grid <= '1' when ((h_active_counter mod 16) = (h_active mod 16)) or (h_Active_counter = 1) diff --git a/fpga/hp_lcd_driver/input_stage.vhdl b/fpga/hp_lcd_driver/input_stage.vhdl index 1316b6e..37cc8a7 100644 --- a/fpga/hp_lcd_driver/input_stage.vhdl +++ b/fpga/hp_lcd_driver/input_stage.vhdl @@ -31,7 +31,8 @@ entity input_stage is video_out : out std_logic_vector(video_width-1 downto 0); addr_out : out std_logic_vector(addr_width - 1 downto 0); - wren_out : out std_logic + wren_out : out std_logic; + index_out : out std_logic ); end input_stage; @@ -133,6 +134,7 @@ begin vsync => d_vsync, addr_out => addr, wren_out => wren, + index_out => index_out, h_grid => h_grid, v_grid => v_grid ); diff --git a/fpga/hp_lcd_driver/output_formatter.vhdl b/fpga/hp_lcd_driver/output_formatter.vhdl index 771c397..7a03c8a 100644 --- a/fpga/hp_lcd_driver/output_formatter.vhdl +++ b/fpga/hp_lcd_driver/output_formatter.vhdl @@ -26,8 +26,7 @@ entity output_formatter is blank_out : out std_logic; vsync_out : out std_logic; hsync_out : out std_logic; - grid_out : out std_logic; - field_out : out std_logic + grid_out : out std_logic ); end output_formatter; @@ -46,8 +45,7 @@ architecture beh of output_formatter is signal vblank : std_logic; signal vsync : std_logic; signal hsync : std_logic; - signal grid : std_logic; - signal field : std_logic; + signal grid : std_logic; begin @@ -90,8 +88,7 @@ begin vblank <= '1'; vsync <= '0'; hsync <= '0'; - grid <='0'; - field<='0'; + grid <= '0'; elsif rising_edge(clk) then if h = 0 then if v = 0 then @@ -100,8 +97,7 @@ begin --addr <= std_logic_vector(to_unsigned(h_stride, addr'length)); blank <= '0'; vblank <= '0'; - field <='0'; - elsif v = v_active then + elsif v = v_active then vblank <= '1'; elsif v = v_sync_start then vsync <= '1'; @@ -109,14 +105,9 @@ begin vsync <= '0'; else blank <= vblank; - addr <= row_addr; - if field='0' then - field<='1'; - else - row_addr <= std_logic_vector(unsigned(row_addr)+v_stride); - field <='0'; - end if; - --addr <= std_logic_vector(unsigned(row_addr)+h_stride); + row_addr <= std_logic_vector(unsigned(row_addr)+v_stride); + addr <= row_addr; + --addr <= std_logic_vector(unsigned(row_addr)+h_stride); end if; elsif h = h_active then blank <= '1'; @@ -128,15 +119,15 @@ begin addr <= std_logic_vector(unsigned(addr)+h_stride); end if; - grid <= '1' when h = 0 else - '1' when h=10 else - '1' when h=h_active-11 else - '1' when h=h_active-1 else - '1' when v=0 else - '1' when v=10 else - '1' when v=v_active-11 else - '1' when v=v_active-1 else - '0'; + grid <= '1' when h = 0 else + '1' when h = 10 else + '1' when h = h_active-11 else + '1' when h = h_active-1 else + '1' when v = 0 else + '1' when v = 10 else + '1' when v = v_active-11 else + '1' when v = v_active-1 else + '0'; end if; end process; @@ -147,8 +138,7 @@ begin blank_out <= blank; hsync_out <= hsync; vsync_out <= vsync; - grid_out <= grid; - field_out <= field; + grid_out <= grid; end beh; diff --git a/fpga/hp_lcd_driver/output_stage.vhdl b/fpga/hp_lcd_driver/output_stage.vhdl index 8583179..37ae297 100644 --- a/fpga/hp_lcd_driver/output_stage.vhdl +++ b/fpga/hp_lcd_driver/output_stage.vhdl @@ -30,7 +30,6 @@ entity output_stage is vsync_in : in std_logic; addr_out : out std_logic_vector(addr_width - 1 downto 0); - field_out : out std_logic; r_in : in std_logic_vector(7 downto 0); g_in : in std_logic_vector(7 downto 0); @@ -71,7 +70,6 @@ architecture beh of output_stage is signal grid_d : std_logic; signal addr : std_logic_vector(addr_width - 1 downto 0); - signal field: std_logic; signal r : std_logic_vector(7 downto 0); signal g : std_logic_vector(7 downto 0); @@ -126,23 +124,21 @@ begin blank_out => blank, vsync_out => vsync, hsync_out => hsync, - grid_out => grid, - field_out => field + grid_out => grid ); addr_out <= addr; - field_out <= field; dg : entity work.delay generic map(stages => 2) port map ( clk => clk, - i => grid, + i => grid, o => grid_d ); - r <= r_in; + r <= r_in; g <= g_in; b <= b_in; diff --git a/fpga/hp_lcd_driver/rando_a7.tcl b/fpga/hp_lcd_driver/rando_a7.tcl index 11ca3b0..cb14260 100644 --- a/fpga/hp_lcd_driver/rando_a7.tcl +++ b/fpga/hp_lcd_driver/rando_a7.tcl @@ -3,4 +3,4 @@ set part_num "xc7a35tfgg484-2" set normal_xdc "../rando_a7.xdc" set use_pclk 1 set input_video_width 8 -set video_width 6 +set video_width 4 diff --git a/fpga/hp_lcd_driver/spartan6.mk b/fpga/hp_lcd_driver/spartan6.mk index 6ea10d9..147e10f 100644 --- a/fpga/hp_lcd_driver/spartan6.mk +++ b/fpga/hp_lcd_driver/spartan6.mk @@ -5,7 +5,7 @@ export XILINXD_LICENSE_FILE PART=xc6slx9-2-tqg144 TOP=hp_lcd_driver BUILD=build_spartan6 -VSRCS=synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl serdes_n_to_1_spartan6.vhdl tmds_encoder.vhdl tmds_phy_spartan6.vhdl tmds_encode.vhdl tmds_output_spartan6.vhdl vram_spartan6.vhdl output_stage.vhdl clkgen_spartan6.vhdl hp_lcd_driver.vhdl +VSRCS=synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl serdes_n_to_1_spartan6.vhdl tmds_encoder.vhdl tmds_phy_spartan6.vhdl tmds_encode.vhdl tmds_output_spartan6.vhdl vram_spartan6.vhdl output_stage.vhdl clkgen_spartan6.vhdl hp_lcd_driver.vhdl common.vhdl UCF=hp_lcd_driver.ucf UT=hp_lcd_driver.ut IPSRCS=vram_spartan6_impl.xco diff --git a/fpga/hp_lcd_driver/tmds_output_artix7.vhdl b/fpga/hp_lcd_driver/tmds_output_artix7.vhdl index 7370bb7..8749d3f 100644 --- a/fpga/hp_lcd_driver/tmds_output_artix7.vhdl +++ b/fpga/hp_lcd_driver/tmds_output_artix7.vhdl @@ -35,7 +35,7 @@ end tmds_output; architecture beh of tmds_output is signal phy_reset : std_logic; - signal b : natural := 0; + signal b : natural range 0 to 9:= 0; begin @@ -60,7 +60,7 @@ begin reset => phy_reset, pix_clk => pclk, phy_clk => pclk_phy, - b =>b, + b => b, din => c_p10, tmds_out_p => tmds_c_out_p, tmds_out_n => tmds_c_out_n @@ -71,7 +71,7 @@ begin reset => phy_reset, pix_clk => pclk, phy_clk => pclk_phy, - b =>b, + b => b, din => r_p10, tmds_out_p => tmds_r_out_p, tmds_out_n => tmds_r_out_n @@ -83,7 +83,7 @@ begin reset => phy_reset, pix_clk => pclk, phy_clk => pclk_phy, - b =>b, + b => b, din => g_p10, tmds_out_p => tmds_g_out_p, tmds_out_n => tmds_g_out_n @@ -95,7 +95,7 @@ begin reset => phy_reset, pix_clk => pclk, phy_clk => pclk_phy, - b =>b, + b => b, din => b_p10, tmds_out_p => tmds_b_out_p, tmds_out_n => tmds_b_out_n diff --git a/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl b/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl index 8c8106e..604ec23 100644 --- a/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl +++ b/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl @@ -22,6 +22,7 @@ end tmds_phy_artix7; architecture beh of tmds_phy_artix7 is signal ld : std_logic_vector(9 downto 0); + signal ld2 : std_logic_vector(9 downto 0); signal sr : std_logic_vector(9 downto 0); signal s : std_logic; @@ -32,7 +33,7 @@ begin process(pix_clk) begin if rising_edge(pix_clk) then - ld <= din; + ld2 <= din; end if; end process; @@ -69,11 +70,14 @@ begin process(phy_clk) begin if rising_edge(phy_clk) then + if b=5 then + ld<=ld2; + end if; if b = 0 then sr <= ld; else sr(8 downto 0) <= sr (9 downto 1); - s <=sr(0); + s <= sr(0); end if; end if; end process; diff --git a/fpga/hp_lcd_driver/vnc_serializer.vhdl b/fpga/hp_lcd_driver/vnc_serializer.vhdl new file mode 100644 index 0000000..9ec89a8 --- /dev/null +++ b/fpga/hp_lcd_driver/vnc_serializer.vhdl @@ -0,0 +1,81 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.all; + +entity vnc_serializer is + generic ( + video_width : integer := 2 + ); + port ( + clk : in std_logic; + vnc_valid : in std_logic; + vnc_data : in std_logic_vector(video_width -1 downto 0); + vnc_index : in std_logic; + fifo_data : out std_logic_vector(64 downto 0); + fifo_wren : out std_logic); +end vnc_serializer; +architecture Behavioural of vnc_serializer is + + + --type REGS is array (0 to 7) of std_logic_vector(video_width-1 downto 0); + type REGS is array (0 to 7) of std_logic_vector(7 downto 0); + + signal reg : REGS; + signal i : natural := 0; + signal wren : std_logic; + signal next_index : std_logic; + signal index : std_logic; + signal rgb : std_logic_vector(7 downto 0); +begin + + rgb(2 downto 0) <= "111" when vnc_data(0)='1' else + "000"; + rgb(5 downto 3) <= "111" when vnc_data(1)='1' and vnc_data(3)='1' else + "100" when vnc_data(1)='1' else + "000"; + rgb(7 downto 6) <= "11" when vnc_data(2)='1' and vnc_data(3)='1' else + "10" when vnc_data(2)='1' else + "00"; + + + process (clk) + begin + if rising_edge(clk) then + if vnc_valid = '1' then + if vnc_index = '1' then + reg(0)<=rgb; + next_index <= '1'; + i <= 1; + wren <= '0'; + else + reg(i) <=rgb; + if i /= 7 then + i <= i+1; + wren <= '0'; + else + i <= 0; + wren <= '1'; + index <= next_index; + next_index <= '0'; + end if; + end if; + else + wren <= '0'; + end if; + end if; + end process; + + + + g_j : for j in 0 to 7 generate +-- fifo_data(((j*8)+video_width-1) downto (j*8)) <= reg(j); +-- fifo_data(((j*8)+7) downto ((j*8)+video_width)) <= (others => '0'); + fifo_data(((j*8)+7) downto (j*8)) <= reg(j); + end generate g_j; + + fifo_data(64) <= index; + + fifo_wren <= wren; + +end Behavioural; diff --git a/fpga/hp_lcd_driver/vram_artix7.vhdl b/fpga/hp_lcd_driver/vram_artix7.vhdl index 470895d..96733da 100644 --- a/fpga/hp_lcd_driver/vram_artix7.vhdl +++ b/fpga/hp_lcd_driver/vram_artix7.vhdl @@ -18,13 +18,13 @@ entity vram is end vram; architecture beh of vram is - signal wr_en_v : std_logic_vector(0 downto 0); --- signal wr_data_6 : std_logic_vector(5 downto 0); --- signal rd_data_6 : std_logic_vector(5 downto 0); + signal wr_en_v : std_logic_vector(0 downto 0); + signal wr_data_6 : std_logic_vector(5 downto 0); + signal rd_data_6 : std_logic_vector(5 downto 0); begin --- wr_data_6 <= "00" & wr_data; --- rd_data <= rd_data_6(3 downto 0); + wr_data_6 <= "00" & wr_data; + rd_data <= rd_data_6(3 downto 0); wr_en_v(0) <= wr_en; @@ -36,11 +36,9 @@ begin clka => wr_clk, wea => wr_en_v, addra => wr_addr, --- dina => wr_data_6, - dina => wr_data, + dina => wr_data_6, clkb => rd_clk, --- doutb => rd_data_6, - doutb => rd_data, + doutb => rd_data_6, addrb => rd_addr ); end beh; diff --git a/fpga/hp_lcd_driver/vram_cyclone4_impl.vhdl b/fpga/hp_lcd_driver/vram_cyclone4_impl.vhdl index 2c50527..adf479c 100644 --- a/fpga/hp_lcd_driver/vram_cyclone4_impl.vhdl +++ b/fpga/hp_lcd_driver/vram_cyclone4_impl.vhdl @@ -6,10 +6,10 @@ -- ============================================================ -- File Name: vram_cyclone4_impl.vhd -- Megafunction Name(s): --- altsyncram +-- altsyncram -- -- Simulation Library Files(s): --- +-- -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! @@ -33,101 +33,101 @@ --applicable agreement for further details. -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY vram_cyclone4_impl IS - PORT - ( - data : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - rdaddress : IN STD_LOGIC_VECTOR (17 DOWNTO 0); - rdclock : IN STD_LOGIC ; - wraddress : IN STD_LOGIC_VECTOR (17 DOWNTO 0); - wrclock : IN STD_LOGIC := '1'; - wren : IN STD_LOGIC := '0'; - q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) - ); -END vram_cyclone4_impl; - - -ARCHITECTURE SYN OF vram_cyclone4_impl IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_b : STRING; - address_reg_b : STRING; - clock_enable_input_a : STRING; - clock_enable_input_b : STRING; - clock_enable_output_b : STRING; - intended_device_family : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - numwords_b : NATURAL; - operation_mode : STRING; - outdata_aclr_b : STRING; - outdata_reg_b : STRING; - power_up_uninitialized : STRING; - widthad_a : NATURAL; - widthad_b : NATURAL; - width_a : NATURAL; - width_b : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - address_a : IN STD_LOGIC_VECTOR (17 DOWNTO 0); - clock0 : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); - wren_a : IN STD_LOGIC ; - address_b : IN STD_LOGIC_VECTOR (17 DOWNTO 0); - clock1 : IN STD_LOGIC - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_b => "NONE", - address_reg_b => "CLOCK1", - clock_enable_input_a => "BYPASS", - clock_enable_input_b => "BYPASS", - clock_enable_output_b => "BYPASS", - intended_device_family => "Cyclone IV E", - lpm_type => "altsyncram", - numwords_a => 245760, - numwords_b => 245760, - operation_mode => "DUAL_PORT", - outdata_aclr_b => "NONE", - outdata_reg_b => "UNREGISTERED", - power_up_uninitialized => "FALSE", - widthad_a => 18, - widthad_b => 18, - width_a => 2, - width_b => 2, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => wraddress, - clock0 => wrclock, - data_a => data, - wren_a => wren, - address_b => rdaddress, - clock1 => rdclock, - q_b => sub_wire0 - ); - - - -END SYN; +library ieee; +use ieee.std_logic_1164.all; + +library altera_mf; +use altera_mf.all; + +entity vram_cyclone4_impl is + port + ( + data : in std_logic_vector (1 downto 0); + rdaddress : in std_logic_vector (17 downto 0); + rdclock : in std_logic; + wraddress : in std_logic_vector (17 downto 0); + wrclock : in std_logic := '1'; + wren : in std_logic := '0'; + q : out std_logic_vector (1 downto 0) + ); +end vram_cyclone4_impl; + + +architecture SYN of vram_cyclone4_impl is + + signal sub_wire0 : std_logic_vector (1 downto 0); + + + + component altsyncram + generic ( + address_aclr_b : string; + address_reg_b : string; + clock_enable_input_a : string; + clock_enable_input_b : string; + clock_enable_output_b : string; + intended_device_family : string; + lpm_type : string; + numwords_a : natural; + numwords_b : natural; + operation_mode : string; + outdata_aclr_b : string; + outdata_reg_b : string; + power_up_uninitialized : string; + widthad_a : natural; + widthad_b : natural; + width_a : natural; + width_b : natural; + width_byteena_a : natural + ); + port ( + address_a : in std_logic_vector (17 downto 0); + clock0 : in std_logic; + data_a : in std_logic_vector (1 downto 0); + q_b : out std_logic_vector (1 downto 0); + wren_a : in std_logic; + address_b : in std_logic_vector (17 downto 0); + clock1 : in std_logic + ); + end component; + +begin + q <= sub_wire0(1 downto 0); + + altsyncram_component : altsyncram + generic map ( + address_aclr_b => "NONE", + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_b => "BYPASS", + intended_device_family => "Cyclone IV E", + lpm_type => "altsyncram", + numwords_a => 245760, + numwords_b => 245760, + operation_mode => "DUAL_PORT", + outdata_aclr_b => "NONE", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + widthad_a => 18, + widthad_b => 18, + width_a => 2, + width_b => 2, + width_byteena_a => 1 + ) + port map ( + address_a => wraddress, + clock0 => wrclock, + data_a => data, + wren_a => wren, + address_b => rdaddress, + clock1 => rdclock, + q_b => sub_wire0 + ); + + + +end SYN; -- ============================================================ -- CNX file retrieval info diff --git a/fpga/hp_lcd_driver/zynq7.mk b/fpga/hp_lcd_driver/zynq7.mk new file mode 100644 index 0000000..e6acad8 --- /dev/null +++ b/fpga/hp_lcd_driver/zynq7.mk @@ -0,0 +1,64 @@ +BUILD=build_${BOARD} + +IP= \ + zynq7_ip/mmcm_0.tcl \ + zynq7_ip/mmcm_1.tcl \ + zynq7_ip/blk_mem_gen_0.tcl \ + zynq7_ip/processing_system7_0.tcl \ + zynq7_ip/fifo_generator_0.tcl + + +BIT=${BUILD}/out/hp_lcd_driver.bit +BIN=${BUILD}/out/hp_lcd_driver.bin + +IP_STAMP=${IP:zynq7_ip/%.tcl=${BUILD}/ip/%/stamp} +SRCS= ${IP} \ + zynq7_config.tcl \ + zynq7_hp_lcd_driver.tcl \ + ${BOARD}.tcl \ + ${BOARD}.xdc \ + clkgen_artix7.vhdl \ + debounce.vhdl \ + delay.vhdl \ + edge_det.vhdl \ + common.vhdl \ + input_formatter.vhdl \ + input_stage.vhdl \ + output_analog.vhdl \ + output_formatter.vhdl \ + output_stage.vhdl \ + synchronizer.vhdl \ + tmds_encoder.vhdl \ + tmds_encode.vhdl \ + tmds_output_artix7.vhdl \ + tmds_phy_artix7.vhdl \ + vram_artix7.vhdl \ + zynq7_wrapper.vhdl \ + fifo_to_axi.vhdl \ + vnc_serializer.vhdl + + + +OPENOCD=openocd -f openocd/${BOARD}.cfg + +default: ${BUILD}/build.stamp + +${BIN} ${BIT}:${BUILD}/build.stamp + +${BUILD}/build.stamp:${SRCS} ${IP_STAMP} + mkdir -p ${BUILD} + (cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch -source ../zynq7_hp_lcd_driver.tcl) + #scripts/xilinx_bit_to_bin.pl ${BIT} ${BIN} + touch $@ + +${BUILD}/ip/%/stamp:zynq7_ip/%.tcl + mkdir -p ${BUILD}/ip + /bin/rm -rf $(dir $@) + (cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch -source ../$<) && touch $@ + + +${BIT}: ${BUILD}/build.stamp + +clean: + /bin/rm -rf ${BUILD} + diff --git a/fpga/hp_lcd_driver/zynq7_config.tcl b/fpga/hp_lcd_driver/zynq7_config.tcl new file mode 100644 index 0000000..d76719c --- /dev/null +++ b/fpga/hp_lcd_driver/zynq7_config.tcl @@ -0,0 +1,30 @@ +# +set board $::env(BOARD) +set board_tcl $source_dir/$board.tcl +set build_dir . +set ip_dir $build_dir/ip +set bd_dir $build_dir/bd +set ipl_dir $build_dir/ip_library +set output_dir $build_dir/out +source $board_tcl +create_project -in_memory -part $part_num + +file mkdir $build_dir +file mkdir $bd_dir +file mkdir $ip_dir +file mkdir $ipl_dir +file mkdir $output_dir + +#WARNING: [Vivado 12-13651] The IP file '/home/root/projects/hp_instrument_lcds/fpga/artix7/build-rando_a7/ip/mmcm_0/mmcm_0.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/root/projects/hp_instrument_lcds/fpga/artix7/build-rando_a7/ip/mmcm_0'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +set_msg_config -id 12-13651 -suppress + + +#WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 vram0/bmg0/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B has an input control pin vram0/bmg0/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B/ADDRBWRADDR[12] (net: vram0/bmg0/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[12]) which is driven by a register (output0/output_formatter/addr_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +set_msg_config -id REQP-1839 -suppress + + + +#WARNING: [Synth 8-3848] Net dma_axi_awid in module/entity pcie_tpm_widget does not have driver. [/root/projects/tpm_interposer/logic_analyzer/source/pcie_tpm_widget.vhdl:88] +#set_msg_config -id 8-3848 -new_severity ERROR + + diff --git a/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl b/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl new file mode 100644 index 0000000..1af332f --- /dev/null +++ b/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl @@ -0,0 +1,88 @@ +# +set source_dir [file dirname [file normalize [info script]]] + +source $source_dir/zynq7_config.tcl + +file mkdir $output_dir + +set files [glob -nocomplain "$output_dir/*"] +if {[llength $files] != 0} { + # clear folder contents + puts "deleting contents of $output_dir" + file delete -force {*}[glob -directory $output_dir *]; +} else { + puts "$output_dir is empty" +} + +#Reference HDL and constraint source files + +#read_xdc $early_xdc + +#read_verilog [ glob ../source/*.v ] +#read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ] +read_vhdl -vhdl2008 -library work { ../zynq7_wrapper.vhdl ../fifo_to_axi.vhdl ../clkgen_artix7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../common.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl ../vnc_serializer.vhdl } + +set generics {} +append generics { } "video_width=$video_width" +append generics { } "input_video_width=$input_video_width" +append generics { } "BOARD=\"$board\"" +append generics { } "use_pclk=$use_pclk" + +set_property generic "$generics" [current_fileset] +puts $generics + +read_ip $ip_dir/mmcm_0/mmcm_0.xci +read_ip $ip_dir/mmcm_1/mmcm_1.xci +read_ip $ip_dir/blk_mem_gen_0/blk_mem_gen_0.xci +read_ip $ip_dir/processing_system7_0/processing_system7_0.xci +read_ip $ip_dir/fifo_generator_0/fifo_generator_0.xci + +read_xdc $normal_xdc + +#Run Synthesis +synth_design -top zynq7_wrapper -part $part_num +write_checkpoint -force $output_dir/post_synth.dcp +report_timing_summary -file $output_dir/post_synth_timing_summary.rpt +report_utilization -file $output_dir/post_synth_util.rpt + +set crdl [get_param tcl.collectionResultDisplayLimit] +set_param tcl.collectionResultDisplayLimit 10000000 + +set f [open "$output_dir/cells.txt" w] +puts $f [get_cells -hierarchical] +close $f + +set f [open "$output_dir/nets.txt" w] +puts $f [get_nets -hierarchical] +close $f +set_param tcl.collectionResultDisplayLimit $crdl + +set f [open "$output_dir/pins.txt" w] +puts $f [get_pins -hierarchical] +close $f +set_param tcl.collectionResultDisplayLimit $crdl + +#run optimization +opt_design +place_design +report_clock_utilization -file $output_dir/clock_util.rpt + +#get timing violations and run optimizations if needed +if {[get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup]] < 0} { + puts "Found setup timing violations => running physical optimization" + phys_opt_design +} +write_checkpoint -force $output_dir/post_place.dcp +report_utilization -file $output_dir/post_place_util.rpt +report_timing_summary -file $output_dir/post_place_timing_summary.rpt + +#Route design and generate bitstream +route_design -directive Explore +write_checkpoint -force $output_dir/post_route.dcp +report_route_status -file $output_dir/post_route_status.rpt +report_timing_summary -file $output_dir/post_route_timing_summary.rpt +report_power -file $output_dir/post_route_power.rpt +report_drc -file $output_dir/post_imp_drc.rpt +report_io -file $output_dir/post_imp_placed.rpt +write_verilog -force $output_dir/cpu_impl_netlist.v -mode timesim -sdf_anno true +write_bitstream -force -bin_file $output_dir/hp_lcd_driver.bit diff --git a/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_0.tcl new file mode 100644 index 0000000..b3e3dce --- /dev/null +++ b/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_0.tcl @@ -0,0 +1,33 @@ + + +set source_dir [file dirname [file dirname [file normalize [info script]]]] + +source $source_dir/zynq7_config.tcl + +create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name blk_mem_gen_0 -dir $ip_dir + +set_property -dict [list \ + CONFIG.Memory_Type {Simple_Dual_Port_RAM} \ + CONFIG.Enable_32bit_Address {false} \ + CONFIG.Use_Byte_Write_Enable {false} \ + CONFIG.Byte_Size {9} \ + CONFIG.Write_Width_A {6} \ + CONFIG.Write_Depth_A {245760} \ + CONFIG.Read_Width_A {6} \ + CONFIG.Operating_Mode_A {NO_CHANGE} \ + CONFIG.Write_Width_B {6} \ + CONFIG.Read_Width_B {6} \ + CONFIG.Enable_B {Use_ENB_Pin} \ + CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ + CONFIG.Register_PortB_Output_of_Memory_Primitives {true} \ + CONFIG.Use_RSTB_Pin {false} \ + CONFIG.Port_B_Clock {22} \ + CONFIG.Port_B_Enable_Rate {22} \ + CONFIG.Disable_Collision_Warnings {false} \ + CONFIG.EN_SAFETY_CKT {false} \ + ] [get_ips blk_mem_gen_0] + +generate_target all [get_ips] + +synth_ip [get_ips] + diff --git a/fpga/hp_lcd_driver/zynq7_ip/fifo_generator_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/fifo_generator_0.tcl new file mode 100644 index 0000000..1c23ecb --- /dev/null +++ b/fpga/hp_lcd_driver/zynq7_ip/fifo_generator_0.tcl @@ -0,0 +1,30 @@ +set source_dir [file dirname [file dirname [file normalize [info script]]]] + +source $source_dir/zynq7_config.tcl + +create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name fifo_generator_0 -dir $ip_dir + +set_property -dict [list \ + CONFIG.Fifo_Implementation {Independent_Clocks_Builtin_FIFO} \ + CONFIG.Performance_Options {First_Word_Fall_Through} \ + CONFIG.Input_Data_Width {65} \ + CONFIG.Input_Depth {512} \ + CONFIG.Output_Data_Width {65} \ + CONFIG.Output_Depth {512} \ + CONFIG.Reset_Type {Asynchronous_Reset} \ + CONFIG.Use_Dout_Reset {false} \ + CONFIG.Data_Count_Width {9} \ + CONFIG.Write_Data_Count_Width {9} \ + CONFIG.Read_Data_Count_Width {9} \ + CONFIG.Read_Clock_Frequency {100} \ + CONFIG.Write_Clock_Frequency {100} \ + CONFIG.Full_Threshold_Assert_Value {505} \ + CONFIG.Full_Threshold_Negate_Value {504} \ + CONFIG.Empty_Threshold_Assert_Value {6} \ + CONFIG.Empty_Threshold_Negate_Value {7} \ +] [get_ips fifo_generator_0] + +generate_target all [get_ips] + +synth_ip [get_ips] + diff --git a/fpga/hp_lcd_driver/zynq7_ip/mmcm_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/mmcm_0.tcl new file mode 100644 index 0000000..089476d --- /dev/null +++ b/fpga/hp_lcd_driver/zynq7_ip/mmcm_0.tcl @@ -0,0 +1,38 @@ +set source_dir [file dirname [file dirname [file normalize [info script]]]] + +source $source_dir/zynq7_config.tcl + +create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name mmcm_0 -dir $ip_dir + +set_property -dict [list \ + CONFIG.PRIM_IN_FREQ {50} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {260} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {86.667} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {52} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {26} \ + CONFIG.CLKIN1_JITTER_PS {200.0} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {26.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {20.000} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {15} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {25} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {50} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.CLKOUT1_JITTER {120.627} \ + CONFIG.CLKOUT1_PHASE_ERROR {154.678} \ + CONFIG.CLKOUT2_JITTER {146.190} \ + CONFIG.CLKOUT2_PHASE_ERROR {154.678} \ + CONFIG.CLKOUT3_JITTER {165.425} \ + CONFIG.CLKOUT3_PHASE_ERROR {154.678} \ + CONFIG.CLKOUT4_JITTER {202.151} \ + CONFIG.CLKOUT4_PHASE_ERROR {154.678} \ + ] [get_ips mmcm_0] + +generate_target all [get_ips] + +synth_ip [get_ips] + diff --git a/fpga/hp_lcd_driver/zynq7_ip/mmcm_1.tcl b/fpga/hp_lcd_driver/zynq7_ip/mmcm_1.tcl new file mode 100644 index 0000000..6420887 --- /dev/null +++ b/fpga/hp_lcd_driver/zynq7_ip/mmcm_1.tcl @@ -0,0 +1,35 @@ +set source_dir [file dirname [file dirname [file normalize [info script]]]] + +source $source_dir/zynq7_config.tcl + +create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name mmcm_1 -dir $ip_dir + +set_property -dict [list \ + CONFIG.PRIM_IN_FREQ {50} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLKOUT5_USED {false} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {78.571} \ + CONFIG.USE_SAFE_CLOCK_STARTUP {false} \ + CONFIG.CLKIN1_JITTER_PS {100.0} \ + CONFIG.CLKOUT1_DRIVES {BUFG} \ + CONFIG.CLKOUT2_DRIVES {BUFG} \ + CONFIG.CLKOUT3_DRIVES {BUFG} \ + CONFIG.CLKOUT4_DRIVES {BUFG} \ + CONFIG.CLKOUT5_DRIVES {BUFG} \ + CONFIG.CLKOUT6_DRIVES {BUFG} \ + CONFIG.CLKOUT7_DRIVES {BUFG} \ + CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \ + CONFIG.MMCM_DIVCLK_DIVIDE {1} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {11.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {20.000} \ + CONFIG.MMCM_CLKIN2_PERIOD {20.000} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {7} \ + CONFIG.NUM_OUT_CLKS {1} \ + ] [get_ips mmcm_1] + +generate_target all [get_ips] + +synth_ip [get_ips] + diff --git a/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl new file mode 100644 index 0000000..4bd2319 --- /dev/null +++ b/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl @@ -0,0 +1,44 @@ +set source_dir [file dirname [file dirname [file normalize [info script]]]] + +source $source_dir/zynq7_config.tcl + +create_ip -name processing_system7 -vendor xilinx.com -library ip -version 5.5 -module_name processing_system7_0 -dir $ip_dir + + +set_property -dict [list \ + CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {20} \ + CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {25} \ + CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {250} \ + CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_USE_S_AXI_HP0 {1} \ + CONFIG.PCW_USE_HIGH_OCM {1} \ + CONFIG.PCW_EN_CLK0_PORT {1} \ + CONFIG.PCW_EN_CLK1_PORT {1} \ + CONFIG.PCW_EN_CLK2_PORT {1} \ + CONFIG.PCW_EN_CLK3_PORT {1} \ + CONFIG.PCW_EN_RST1_PORT {1} \ + CONFIG.PCW_EN_RST2_PORT {1} \ + CONFIG.PCW_EN_RST3_PORT {1} \ + CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \ + CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J128M16 HA-15E} \ + CONFIG.PCW_NAND_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_NAND_NAND_IO {MIO 0 2.. 14} \ + CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_ENET0_ENET0_IO {EMIO} \ + CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ + CONFIG.PCW_ENET0_GRP_MDIO_IO {EMIO} \ + CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART1_UART1_IO {MIO 24 .. 25} \ + CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_I2C0_I2C0_IO {MIO 26 .. 27} \ + CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ + CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {100 Mbps}] [get_ips processing_system7_0] + +generate_target all [get_ips] + +synth_ip [get_ips] + diff --git a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl new file mode 100644 index 0000000..529a1b1 --- /dev/null +++ b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl @@ -0,0 +1,391 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2020 - embed-me +-- +-- Lukas Lichtl <support@embed-me.com> +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License v2 as published by +-- the Free Software Foundation. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +-------------------------------------------------------------------------------- +-- Function description: +-- +-------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library UNISIM; +use UNISIM.vcomponents.all; + + +entity zynq7_wrapper is + generic (input_video_width : natural := 2; + video_width : natural := 2; + addr_width : natural := 18; + phase_slip : natural := 320; + i_clk_multiple : natural := 4; + use_pclk : natural := 0; + target : string := "zynq7"); + port ( + -- ddr + ddr_addr_io : inout std_logic_vector (14 downto 0); + ddr_ba_io : inout std_logic_vector (2 downto 0); + ddr_cas_n_io : inout std_logic; + ddr_ck_n_io : inout std_logic; + ddr_ck_p_io : inout std_logic; + ddr_cke_io : inout std_logic; + ddr_cs_n_io : inout std_logic; + ddr_dm_io : inout std_logic_vector (3 downto 0); + ddr_dq_io : inout std_logic_vector (31 downto 0); + ddr_dqs_n_io : inout std_logic_vector (3 downto 0); + ddr_dqs_p_io : inout std_logic_vector (3 downto 0); + ddr_odt_io : inout std_logic; + ddr_ras_n_io : inout std_logic; + ddr_reset_n_io : inout std_logic; + ddr_we_n_io : inout std_logic; + -- eth0 + eth0_clk_o : out std_logic; -- alternative clock, only used when Oscillator is missing on the PCB + eth0_gmii_rx_clk_i : in std_logic; + eth0_gmii_rx_dv_i : in std_logic; + eth0_gmii_rxd_i : in std_logic_vector (3 downto 0); + eth0_gmii_tx_clk_i : in std_logic; + eth0_gmii_tx_en_o : out std_logic_vector (0 to 0); + eth0_gmii_txd_o : out std_logic_vector (3 downto 0); + eth0_mdio_mdc_o : out std_logic; + eth0_mdio_mdio_io : inout std_logic; + -- ios + fixed_io_ddr_vrn_io : inout std_logic; + fixed_io_ddr_vrp_io : inout std_logic; + fixed_io_mio_io : inout std_logic_vector (53 downto 0); + fixed_io_ps_clk_io : inout std_logic; + fixed_io_ps_porb_io : inout std_logic; + fixed_io_ps_srstb_io : inout std_logic; + green_led : out std_logic; + red_led : out std_logic; + +--in + video : in std_logic_vector(input_video_width -1 downto 0); + hsync_in : in std_logic; + vsync_in : in std_logic; + pclk_in : in std_logic; +-- hdmi + hdmi_c_p : out std_logic; + hdmi_c_n : out std_logic; + hdmi_r_p : out std_logic; + hdmi_r_n : out std_logic; + hdmi_g_p : out std_logic; + hdmi_g_n : out std_logic; + hdmi_b_p : out std_logic; + hdmi_b_n : out std_logic; + hdmi_vcc : out std_logic + ); + +end entity zynq7_wrapper; + + + +architecture arch of zynq7_wrapper is + + signal eth0_gmii_txd : std_logic_vector(7 downto 0); + signal eth0_gmii_rxd : std_logic_vector(7 downto 0); + + signal emio_i : std_logic_vector(63 downto 0); + signal emio_o : std_logic_vector(63 downto 0); + signal emio_t : std_logic_vector(63 downto 0); + + + + signal gp0_aclk : std_logic; + signal gp0_nrst : std_logic; + + signal hp0_aclk : std_logic; + signal hp0_nrst : std_logic; + signal hp0_arvalid : std_logic; + signal hp0_araddr : std_logic_vector(31 downto 0); + signal hp0_arready : std_logic; + signal hp0_awaddr : std_logic_vector(31 downto 0); + signal hp0_awready : std_logic; + signal hp0_awvalid : std_logic; + signal hp0_bready : std_logic; + signal hp0_bvalid : std_logic; + signal hp0_rdata : std_logic_vector(63 downto 0); + signal hp0_wdata : std_logic_vector(63 downto 0); + signal hp0_rready : std_logic; + signal hp0_rvalid : std_logic; + signal hp0_wready : std_logic; + signal hp0_wvalid : std_logic; + signal hp0_wstrb : std_logic_vector(7 downto 0); + + + signal fifo_rst_cnt : natural; + signal fifo_rst : std_logic; + signal fifo_wr_en : std_logic; + signal fifo_wdata : std_logic_vector(64 downto 0); + signal fifo_rd_en : std_logic; + signal fifo_rdata : std_logic_vector(64 downto 0); + signal fifo_empty : std_logic; + + signal run : std_logic; + + signal eth0_mdio_mdio_i : std_logic; + signal eth0_mdio_mdio_o : std_logic; + signal eth0_mdio_mdio_t : std_logic; + + signal clk_50m : std_logic; + signal sys_rst_n : std_logic; + + signal vnc_clk : std_logic; + signal vnc_valid : std_logic; + signal vnc_data : std_logic_vector(video_width-1 downto 0); + signal vnc_index : std_logic; + + +begin + + + clk_50m <= hp0_aclk; + + common_i : entity work.common + generic map ( + input_video_width => input_video_width, + video_width => video_width, + addr_width => addr_width, + phase_slip => phase_slip, + i_clk_multiple => i_clk_multiple, + use_pclk => use_pclk, + target => target) + port map (clk_50m => clk_50m, + sys_rst_n => sys_rst_n, + video => video, + hsync_in => hsync_in, + vsync_in => vsync_in, + pclk_in => pclk_in, + r_out => open, + b_out => open, + g_out => open, + hsync_out => open, + vsync_out => open, + hdmi_c_p => hdmi_c_p, + hdmi_c_n => hdmi_c_n, + hdmi_r_p => hdmi_r_p, + hdmi_r_n => hdmi_r_n, + hdmi_g_p => hdmi_g_p, + hdmi_g_n => hdmi_g_n, + hdmi_b_p => hdmi_b_p, + hdmi_b_n => hdmi_b_n, + hdmi_vcc => hdmi_vcc, + i_clk_out => open, + led => open, + video_out_clk => vnc_clk, + video_out_valid => vnc_valid, + video_out_data => vnc_data, + video_out_index => vnc_index + ); + + processing_system7_0_i : entity work.processing_system7_0 + port map ( + DDR_Addr => ddr_addr_io, + DDR_BankAddr => ddr_ba_io, + DDR_CAS_n => ddr_cas_n_io, + DDR_Clk_n => ddr_ck_n_io, + DDR_Clk => ddr_ck_p_io, + DDR_CKE => ddr_cke_io, + DDR_CS_n => ddr_cs_n_io, + DDR_DM => ddr_dm_io, + DDR_DQ => ddr_dq_io, + DDR_DQS_n => ddr_dqs_n_io, + DDR_DQS => ddr_dqs_p_io, + DDR_ODT => ddr_odt_io, + DDR_RAS_n => ddr_ras_n_io, + DDR_DRSTB => ddr_reset_n_io, + DDR_WEB => ddr_we_n_io, + FCLK_CLK0 => eth0_clk_o, + FCLK_CLK1 => gp0_aclk, + FCLK_CLK2 => hp0_aclk, + FCLK_CLK2 => clk_50m, + FCLK_RESET1_N => gp0_nrst, + FCLK_RESET2_N => hp0_nrst, + FCLK_RESET3_N => sys_rst_n, + + ENET0_GMII_RX_CLK => eth0_gmii_rx_clk_i, + ENET0_GMII_RX_DV => eth0_gmii_rx_dv_i, + ENET0_GMII_RXD => eth0_gmii_rxd, + ENET0_GMII_RX_ER => '0', + ENET0_GMII_COL => '0', + ENET0_GMII_CRS => '0', + + + ENET0_GMII_TX_CLK => eth0_gmii_tx_clk_i, + ENET0_GMII_TX_EN => eth0_gmii_tx_en_o, + ENET0_GMII_TXD => eth0_gmii_txd, + + ENET0_MDIO_MDC => eth0_mdio_mdc_o, + ENET0_MDIO_O => eth0_mdio_mdio_o, + ENET0_MDIO_I => eth0_mdio_mdio_i, + ENET0_MDIO_T => eth0_mdio_mdio_t, + DDR_VRN => fixed_io_ddr_vrn_io, + DDR_VRP => fixed_io_ddr_vrp_io, + MIO(53 downto 0) => fixed_io_mio_io, + PS_CLK => fixed_io_ps_clk_io, + PS_PORB => fixed_io_ps_porb_io, + PS_SRSTB => fixed_io_ps_srstb_io, + GPIO_I => emio_i, + GPIO_O => emio_o, + GPIO_T => emio_t, + + M_AXI_GP0_ACLK => gp0_aclk, + M_AXI_GP0_ARREADY => '0', + M_AXI_GP0_AWREADY => '0', + M_AXI_GP0_BID => (others => '0'), + M_AXI_GP0_BRESP => (others => '0'), + M_AXI_GP0_BVALID => '0', + M_AXI_GP0_RDATA => (others => '0'), + M_AXI_GP0_RID => (others => '0'), + M_AXI_GP0_RLAST => '1', + M_AXI_GP0_RRESP => (others => '0'), + M_AXI_GP0_RVALID => '0', + M_AXI_GP0_WREADY => '0', + + + S_AXI_HP0_ACLK => hp0_aclk, + S_AXI_HP0_ARADDR => hp0_araddr, + S_AXI_HP0_ARBURST => "01", + S_AXI_HP0_ARCACHE => "0001", + S_AXI_HP0_ARID => (others => '0'), + S_AXI_HP0_ARLEN => "0000", + S_AXI_HP0_ARLOCK => "00", + S_AXI_HP0_ARPROT => "000", + S_AXI_HP0_ARQOS => "0000", -- not present in AXI3 which is this + S_AXI_HP0_ARREADY => hp0_arready, + S_AXI_HP0_ARSIZE => "011", -- 8 bytes ?? + S_AXI_HP0_ARVALID => hp0_arvalid, + S_AXI_HP0_AWADDR => hp0_awaddr, + S_AXI_HP0_AWBURST => "01", + S_AXI_HP0_AWCACHE => "0001", + S_AXI_HP0_AWID => (others => '0'), + S_AXI_HP0_AWLEN => "0000", + S_AXI_HP0_AWLOCK => "00", + S_AXI_HP0_AWPROT => "000", + S_AXI_HP0_AWQOS => "0000", -- not present in AXI3 which this is + S_AXI_HP0_AWREADY => hp0_awready, + S_AXI_HP0_AWSIZE => "011", -- 8 bytes? + S_AXI_HP0_AWVALID => hp0_awvalid, + S_AXI_HP0_BID => open, + S_AXI_HP0_BREADY => hp0_bready, + S_AXI_HP0_BRESP => open, + S_AXI_HP0_BVALID => hp0_bvalid, + S_AXI_HP0_RDATA => hp0_rdata, + S_AXI_HP0_RID => open, + S_AXI_HP0_RLAST => open, + S_AXI_HP0_RREADY => hp0_rready, + S_AXI_HP0_RRESP => open, + S_AXI_HP0_RVALID => hp0_rvalid, + S_AXI_HP0_WDATA => hp0_wdata, + S_AXI_HP0_WID => "000000", + S_AXI_HP0_WLAST => '1', + S_AXI_HP0_WREADY => hp0_wready, + S_AXI_HP0_WSTRB => hp0_wstrb, + S_AXI_HP0_WVALID => hp0_wvalid + ); + + eth0_mdio_mdio_iobuf : IOBUF + port map ( + I => eth0_mdio_mdio_o, + IO => eth0_mdio_mdio_io, + O => eth0_mdio_mdio_i, + T => eth0_mdio_mdio_t + ); + + + vnc_serializer_i : entity work.vnc_serializer + generic map ( + video_width => video_width + ) + port map ( + clk => vnc_clk, + vnc_valid => vnc_valid, + vnc_data => vnc_data, + vnc_index => vnc_index, + + fifo_data => fifo_wdata, + fifo_wren => fifo_wr_en); + + + process (clk_50m) + begin + if rising_edge(clk_50m) then + if sys_rst_n = '0' then + fifo_rst_cnt <= 20; + fifo_rst <= '1'; + elsif fifo_rst_cnt /= 0 then + fifo_rst_cnt <= fifo_rst_cnt -1; + else + fifo_rst <= '0'; + end if; + end if; + end process; + + fifo_i : entity work.fifo_generator_0 + port map ( + rst => fifo_rst, + wr_clk => vnc_clk, + din => fifo_wdata, + wr_en => fifo_wr_en, + rd_clk => hp0_aclk, + rd_en => fifo_rd_en, + dout => fifo_rdata, + empty => fifo_empty + ); + + + + fifo_to_axi_i : entity work.fifo_to_axi + port map( + aclk => hp0_aclk, + aresetn => hp0_nrst, + axi_awaddr => hp0_awaddr, + axi_awvalid => hp0_awvalid, + axi_awready => hp0_awready, + axi_wdata => hp0_wdata, + axi_wstrb => hp0_wstrb, + axi_wvalid => hp0_wvalid, + axi_wready => hp0_wready, + axi_bvalid => hp0_bvalid, + axi_bready => hp0_bready, + + run => run, + + fifo_empty => fifo_empty, + fifo_rdata => fifo_rdata, + fifo_rd_en => fifo_rd_en + ); + + + hp0_araddr <= (others => '0'); + hp0_arvalid <= '0'; + hp0_rready <= '0'; + + ----------------------------------------------------------------------------- + -- IOs + ----------------------------------------------------------------------------- + + eth0_gmii_txd_o <= eth0_gmii_txd(eth0_gmii_txd_o'range); + eth0_gmii_rxd <= b"0000" & eth0_gmii_rxd_i; + + red_led <= emio_o(0); + green_led <= emio_o(1); + run <= emio_o(2); + + +end architecture arch; |