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-rw-r--r--fpga/hp_lcd_driver/hp_lcd_driver.vhdl40
-rw-r--r--fpga/hp_lcd_driver/input_formatter.vhdl45
-rw-r--r--fpga/hp_lcd_driver/output_formatter.vhdl14
-rw-r--r--fpga/hp_lcd_driver/output_stage.vhdl6
-rw-r--r--fpga/hp_lcd_driver/rando_a7.tcl2
-rw-r--r--fpga/hp_lcd_driver/vram_artix7.vhdl14
-rw-r--r--pcbs/bt475-interface/bt475-interface.kicad_pcb32
-rw-r--r--pcbs/bt475-interface/bt475-interface.kicad_prl2
8 files changed, 95 insertions, 60 deletions
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
index 94199b9..f60e80e 100644
--- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -53,6 +53,7 @@ architecture Behavioral of hp_lcd_driver is
signal rd_addr : std_logic_vector(addr_width-1 downto 0);
signal rd_data : std_logic_vector(video_width-1 downto 0);
+ signal rd_field : std_logic;
signal r : std_logic_vector(7 downto 0);
signal g : std_logic_vector(7 downto 0);
@@ -101,15 +102,7 @@ begin
);
-video_lut <= "1111" when video(0)='1' else
- "1011" when video(1)='1' else
- "1100" when video(2)='1' else
- "1010" when video(3)='1' else
- "0011" when video(4)='1' else
- "1110" when video(5)='1' else
- "1001" when video(6)='1' else
- "1101" when video(7)='1' else
- "0000";
+video_lut<= (video(0),video(1),video(2) xor video(3),video(4),video(5),video(6) xor video(7));
process (i_clk, sys_rst_n)
@@ -231,22 +224,18 @@ video_lut <= "1111" when video(0)='1' else
-- b<=x"00";
-
-
- r<=x"ff" when rd_data(0)='1' else
- x"00";
-
--- r<=x"ff" when rd_data(0)='1' and rd_data(3)='1' else
--- x"80" when rd_data(0)='1' else
--- x"00";
-
- g<=x"ff" when rd_data(1)='1' and rd_data(3)='1' else
- x"80" when rd_data(1)='1' else
- x"00";
- b<=x"ff" when rd_data(2)='1' and rd_data(3)='1' else
- x"80" when rd_data(2)='1' else
- x"00";
-
+ r<= x"ff" when rd_data(0)='1' and rd_field='0' else
+ x"ff" when rd_data(3)='1' and rd_field='1' else
+ x"00";
+
+ g<= x"ff" when rd_data(1)='1' and rd_field='0' else
+ x"ff" when rd_data(4)='1' and rd_field='1' else
+ x"00";
+
+ b<= x"ff" when rd_data(2)='1' and rd_field='0' else
+ x"ff" when rd_data(5)='1' and rd_field='1' else
+ x"00";
+
--"ff" when rd_data(1) = '1' else
@@ -328,6 +317,7 @@ video_lut <= "1111" when video(0)='1' else
g_in => g,
b_in => b,
addr_out => rd_addr,
+ field_out => rd_field,
r_out => r_out,
g_out => g_out,
b_out => b_out,
diff --git a/fpga/hp_lcd_driver/input_formatter.vhdl b/fpga/hp_lcd_driver/input_formatter.vhdl
index f8b27c2..7dbd07a 100644
--- a/fpga/hp_lcd_driver/input_formatter.vhdl
+++ b/fpga/hp_lcd_driver/input_formatter.vhdl
@@ -37,7 +37,6 @@ end input_formatter;
architecture beh of input_formatter is
- signal row_addr : std_logic_vector(addr_width-1 downto 0);
signal addr : std_logic_vector(addr_width-1 downto 0);
signal wren : std_logic;
@@ -55,6 +54,14 @@ architecture beh of input_formatter is
signal h_div : natural;
signal phase_accum : natural;
+ signal ix:natural;
+ signal iy:natural;
+ signal ox:natural;
+ signal oy:natural;
+ signal oz:natural;
+ signal ow:natural;
+
+
begin
@@ -78,14 +85,11 @@ begin
- addr_out <= addr;
process (sys_rst_n, clk, hsync_pe, vsync)
begin
if sys_rst_n = '0' then
- row_addr <= (others => '0');
- addr <= (others => '0');
h_div <= 0;
h_active_counter <= 0;
h_fp_counter <= 0;
@@ -96,21 +100,21 @@ begin
if hsync_pe = '1' then
--if v_active_counter = 0 and v_fp_counter=0 then
if vsync = '1' then
- row_addr <= std_logic_vector(to_unsigned(frame_start, addr_width));
v_fp_counter <= v_front_porch;
v_active_counter <= v_active;
+ iy<=0;
elsif v_fp_counter /= 0 then
v_fp_counter <= v_fp_counter -1;
elsif v_active_counter /= 0 then
v_active_counter <= v_active_counter -1;
+ iy<=iy+1;
h_fp_counter <= h_front_porch * clk_multiple + phase;
h_active_counter <= h_active;
phase_accum <= phase_slip;
h_div <= 0;
+ ix<=0;
- addr <= row_addr;
- row_addr <= std_logic_vector(unsigned(row_addr)+v_stride);
end if;
elsif h_fp_counter /= 0 then
h_fp_counter <= h_fp_counter -1;
@@ -136,12 +140,37 @@ begin
if wren = '1' then
h_active_counter <= h_active_counter -1;
- addr <= std_logic_vector(unsigned(addr)+h_stride);
+ ix<=ix+1;
end if;
end if;
end if;
end process;
+
+ ow<=(ix+4*iy) mod 640;
+ oz<=0 when ow<320
+ else 1;
+ ox<=ow mod 320;
+ oy<=iy*2 +oz;
+
+
+
+
+ process (sys_rst_n, clk, hsync_pe, vsync)
+ begin
+ if sys_rst_n = '0' then
+ addr<=( others =>'0');
+ elsif rising_edge(clk) then
+ if oy<384 then
+ addr<= std_logic_vector(to_unsigned((ox*384) + (383-oy) ,addr'length));
+ else
+ addr <= (others =>'0');
+ end if;
+ end if;
+ end process;
+
+
+
addr_out <= addr;
wren_out <= wren;
diff --git a/fpga/hp_lcd_driver/output_formatter.vhdl b/fpga/hp_lcd_driver/output_formatter.vhdl
index 1f9e89f..771c397 100644
--- a/fpga/hp_lcd_driver/output_formatter.vhdl
+++ b/fpga/hp_lcd_driver/output_formatter.vhdl
@@ -26,7 +26,8 @@ entity output_formatter is
blank_out : out std_logic;
vsync_out : out std_logic;
hsync_out : out std_logic;
- grid_out : out std_logic
+ grid_out : out std_logic;
+ field_out : out std_logic
);
end output_formatter;
@@ -46,6 +47,7 @@ architecture beh of output_formatter is
signal vsync : std_logic;
signal hsync : std_logic;
signal grid : std_logic;
+ signal field : std_logic;
begin
@@ -89,6 +91,7 @@ begin
vsync <= '0';
hsync <= '0';
grid <='0';
+ field<='0';
elsif rising_edge(clk) then
if h = 0 then
if v = 0 then
@@ -97,6 +100,7 @@ begin
--addr <= std_logic_vector(to_unsigned(h_stride, addr'length));
blank <= '0';
vblank <= '0';
+ field <='0';
elsif v = v_active then
vblank <= '1';
elsif v = v_sync_start then
@@ -105,8 +109,13 @@ begin
vsync <= '0';
else
blank <= vblank;
- row_addr <= std_logic_vector(unsigned(row_addr)+v_stride);
addr <= row_addr;
+ if field='0' then
+ field<='1';
+ else
+ row_addr <= std_logic_vector(unsigned(row_addr)+v_stride);
+ field <='0';
+ end if;
--addr <= std_logic_vector(unsigned(row_addr)+h_stride);
end if;
elsif h = h_active then
@@ -139,6 +148,7 @@ begin
hsync_out <= hsync;
vsync_out <= vsync;
grid_out <= grid;
+ field_out <= field;
end beh;
diff --git a/fpga/hp_lcd_driver/output_stage.vhdl b/fpga/hp_lcd_driver/output_stage.vhdl
index b43dc50..8583179 100644
--- a/fpga/hp_lcd_driver/output_stage.vhdl
+++ b/fpga/hp_lcd_driver/output_stage.vhdl
@@ -30,6 +30,7 @@ entity output_stage is
vsync_in : in std_logic;
addr_out : out std_logic_vector(addr_width - 1 downto 0);
+ field_out : out std_logic;
r_in : in std_logic_vector(7 downto 0);
g_in : in std_logic_vector(7 downto 0);
@@ -70,6 +71,7 @@ architecture beh of output_stage is
signal grid_d : std_logic;
signal addr : std_logic_vector(addr_width - 1 downto 0);
+ signal field: std_logic;
signal r : std_logic_vector(7 downto 0);
signal g : std_logic_vector(7 downto 0);
@@ -124,11 +126,13 @@ begin
blank_out => blank,
vsync_out => vsync,
hsync_out => hsync,
- grid_out => grid
+ grid_out => grid,
+ field_out => field
);
addr_out <= addr;
+ field_out <= field;
dg : entity work.delay
generic map(stages => 2)
diff --git a/fpga/hp_lcd_driver/rando_a7.tcl b/fpga/hp_lcd_driver/rando_a7.tcl
index cb14260..11ca3b0 100644
--- a/fpga/hp_lcd_driver/rando_a7.tcl
+++ b/fpga/hp_lcd_driver/rando_a7.tcl
@@ -3,4 +3,4 @@ set part_num "xc7a35tfgg484-2"
set normal_xdc "../rando_a7.xdc"
set use_pclk 1
set input_video_width 8
-set video_width 4
+set video_width 6
diff --git a/fpga/hp_lcd_driver/vram_artix7.vhdl b/fpga/hp_lcd_driver/vram_artix7.vhdl
index 6e4c171..470895d 100644
--- a/fpga/hp_lcd_driver/vram_artix7.vhdl
+++ b/fpga/hp_lcd_driver/vram_artix7.vhdl
@@ -19,12 +19,12 @@ end vram;
architecture beh of vram is
signal wr_en_v : std_logic_vector(0 downto 0);
- signal wr_data_6 : std_logic_vector(5 downto 0);
- signal rd_data_6 : std_logic_vector(5 downto 0);
+-- signal wr_data_6 : std_logic_vector(5 downto 0);
+-- signal rd_data_6 : std_logic_vector(5 downto 0);
begin
- wr_data_6 <= "00" & wr_data;
- rd_data <= rd_data_6(3 downto 0);
+-- wr_data_6 <= "00" & wr_data;
+-- rd_data <= rd_data_6(3 downto 0);
wr_en_v(0) <= wr_en;
@@ -36,9 +36,11 @@ begin
clka => wr_clk,
wea => wr_en_v,
addra => wr_addr,
- dina => wr_data_6,
+-- dina => wr_data_6,
+ dina => wr_data,
clkb => rd_clk,
- doutb => rd_data_6,
+-- doutb => rd_data_6,
+ doutb => rd_data,
addrb => rd_addr
);
end beh;
diff --git a/pcbs/bt475-interface/bt475-interface.kicad_pcb b/pcbs/bt475-interface/bt475-interface.kicad_pcb
index 8472e19..8329367 100644
--- a/pcbs/bt475-interface/bt475-interface.kicad_pcb
+++ b/pcbs/bt475-interface/bt475-interface.kicad_pcb
@@ -5823,6 +5823,14 @@
(uuid "dbb69ca7-9938-481d-96b1-684c2925500f")
)
(segment
+ (start 179.7 65.4)
+ (end 179.9 65.2)
+ (width 0.6)
+ (layer "B.Cu")
+ (net 2)
+ (uuid "0402bd79-348b-4266-b561-ac540bb19aa1")
+ )
+ (segment
(start 185.2 57)
(end 183.5 58.7)
(width 0.6)
@@ -5831,12 +5839,12 @@
(uuid "0544136b-4447-4f58-ada8-11d042fde1d1")
)
(segment
- (start 179.9 65.2)
- (end 179.7 65.4)
+ (start 179.9 58.6)
+ (end 180.3 58.6)
(width 0.6)
(layer "B.Cu")
(net 2)
- (uuid "30993ada-2b58-4518-a419-1b3b6c4754d3")
+ (uuid "27826678-470d-4116-aefc-4e2c072045d6")
)
(segment
(start 183.6928 78.613)
@@ -5847,20 +5855,12 @@
(uuid "52411acc-323c-4bf2-807a-faf6efb121e5")
)
(segment
- (start 179.5 58.6)
- (end 179.9 59)
- (width 0.6)
- (layer "B.Cu")
- (net 2)
- (uuid "57d794d4-74f3-4102-9291-7113ba5428cf")
- )
- (segment
- (start 179.9 59)
- (end 179.9 65.2)
+ (start 179.9 65.2)
+ (end 179.9 58.6)
(width 0.6)
(layer "B.Cu")
(net 2)
- (uuid "6005d06b-e369-4b4b-934a-28916aba3c99")
+ (uuid "77e75ed5-3cc0-43fa-85d8-ad018133638a")
)
(segment
(start 180.3 58.6)
@@ -5880,11 +5880,11 @@
)
(segment
(start 179.5 58.6)
- (end 180.3 58.6)
+ (end 179.9 58.6)
(width 0.6)
(layer "B.Cu")
(net 2)
- (uuid "f5207ee2-1bf0-45c5-9e5e-bc18aad67fed")
+ (uuid "d2a1a98d-8977-4fdc-b213-ed2df3cad9bb")
)
(segment
(start 183.5 58.7)
diff --git a/pcbs/bt475-interface/bt475-interface.kicad_prl b/pcbs/bt475-interface/bt475-interface.kicad_prl
index 99354e4..9ae878f 100644
--- a/pcbs/bt475-interface/bt475-interface.kicad_prl
+++ b/pcbs/bt475-interface/bt475-interface.kicad_prl
@@ -1,6 +1,6 @@
{
"board": {
- "active_layer": 0,
+ "active_layer": 31,
"active_layer_preset": "All Layers",
"auto_track_width": true,
"hidden_netclasses": [],
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-06 07:44:10 +0000