diff options
| -rw-r--r-- | fpga/hp_lcd_driver/ebaz4205.xdc | 7 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/tmds_phy_artix7.vhdl | 9 |
2 files changed, 12 insertions, 4 deletions
diff --git a/fpga/hp_lcd_driver/ebaz4205.xdc b/fpga/hp_lcd_driver/ebaz4205.xdc index 9c13036..64660eb 100644 --- a/fpga/hp_lcd_driver/ebaz4205.xdc +++ b/fpga/hp_lcd_driver/ebaz4205.xdc @@ -147,6 +147,13 @@ set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] +set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[*]/D}] 9 +set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[*]/D}] 9 +set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[*]/D}] 9 +set_max_delay -from [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[*]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[*]/D}] 9 + + + #set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[0]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[0]/D}] #set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[0]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[0]/D}] #set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[0]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[0]/D}] diff --git a/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl b/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl index 26f29c0..604ec23 100644 --- a/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl +++ b/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl @@ -22,6 +22,7 @@ end tmds_phy_artix7; architecture beh of tmds_phy_artix7 is signal ld : std_logic_vector(9 downto 0); + signal ld2 : std_logic_vector(9 downto 0); signal sr : std_logic_vector(9 downto 0); signal s : std_logic; @@ -32,7 +33,7 @@ begin process(pix_clk) begin if rising_edge(pix_clk) then - ld <= din; + ld2 <= din; end if; end process; @@ -69,9 +70,9 @@ begin process(phy_clk) begin if rising_edge(phy_clk) then --- if b=5 then --- ld2<=ld; --- end if; + if b=5 then + ld<=ld2; + end if; if b = 0 then sr <= ld; else |