zynq build works

9 files changed, 196 insertions, 54 deletions

diff --git a/fpga/hp_lcd_driver/Makefile b/fpga/hp_lcd_driver/Makefile
index 5089f5c..d7b3eca 100644
--- a/fpga/hp_lcd_driver/Makefile
+++ b/fpga/hp_lcd_driver/Makefile
@@ -4,8 +4,8 @@ TARGETS= ebaz4205 #rando_a7 #smh-ac415b  #spartan6 #ep4ce6 smh-ac415
 #better_default: build_rando_a7/hp_lcd_driver.svf
 #	./prog_a7
 
-better_default: build_ebaz4205/out/hp_lcd_driver.bin
-	scp build_ebaz4205/out/hp_lcd_driver.bin 10.16.66.163:/boot/uboot/hp_lcd_driver.bin
+#better_default: build_ebaz4205/out/hp_lcd_driver.bin
+#	scp build_ebaz4205/out/hp_lcd_driver.bin 10.16.66.163:/boot/uboot/hp_lcd_driver.bin
 
 default: ${TARGETS:%=build_%/hp_lcd_driver.svf} 
 
diff --git a/fpga/hp_lcd_driver/ebaz4205.xdc b/fpga/hp_lcd_driver/ebaz4205.xdc
index 903334c..93da55b 100644
--- a/fpga/hp_lcd_driver/ebaz4205.xdc
+++ b/fpga/hp_lcd_driver/ebaz4205.xdc
@@ -27,31 +27,30 @@ set_property PACKAGE_PIN W14 [get_ports {red_led}]
 
 set_property IOSTANDARD LVCMOS33 [get_ports *_led]
 
-
 #set_property IOSTANDARD LVCMOS33 [get_ports clk_50m]
 #set_property PACKAGE_PIN R4 [get_ports clk_50m]
 
 #set_property PACKAGE_PIN T1 [get_ports {led_1}]
 #set_property IOSTANDARD LVCMOS33 [get_ports {led_1}]
 
-#set_property PACKAGE_PIN U3 [get_ports {hdmi_r_p}]
-#set_property PACKAGE_PIN V3 [get_ports {hdmi_r_n}]
-#set_property PACKAGE_PIN R6 [get_ports {hdmi_g_p}]
-#set_property PACKAGE_PIN T6 [get_ports {hdmi_g_n}]
-#set_property PACKAGE_PIN R3 [get_ports {hdmi_b_p}]
-#set_property PACKAGE_PIN R2 [get_ports {hdmi_b_n}]
-#set_property PACKAGE_PIN Y3 [get_ports {hdmi_c_p}]
-#set_property PACKAGE_PIN AA3 [get_ports {hdmi_c_n}]
-#
-#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_p}]
-#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_n}]
-#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_p}]
-#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_n}]
-#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_p}]
-#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_n}]
-#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_p}]
-#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_n}]
-#
+set_property PACKAGE_PIN G19 [get_ports {hdmi_r_p}]; #data2-5
+set_property PACKAGE_PIN G20 [get_ports {hdmi_r_n}]; #data2-7
+set_property PACKAGE_PIN K19 [get_ports {hdmi_g_p}]; #data2-13
+set_property PACKAGE_PIN J19 [get_ports {hdmi_g_n}]; #data2-9
+set_property PACKAGE_PIN L19 [get_ports {hdmi_b_p}]; #data2-16
+set_property PACKAGE_PIN L20 [get_ports {hdmi_b_n}]; #data2-18
+set_property PACKAGE_PIN L16 [get_ports {hdmi_c_p}]; #data2-15
+set_property PACKAGE_PIN L17 [get_ports {hdmi_c_n}]; #data2-20
+
+set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_p}]
+set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_n}]
+set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_p}]
+set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_n}]
+set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_p}]
+set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_n}]
+set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_p}]
+set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_n}]
+
 ##set_property DRIVE 16 [get_ports {hdmi_c_p}]
 ##set_property DRIVE 16 [get_ports {hdmi_c_n}]
 ##set_property DRIVE 16 [get_ports {hdmi_r_p}]
@@ -60,8 +59,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports *_led]
 ##set_property DRIVE 16 [get_ports {hdmi_g_n}]
 ##set_property DRIVE 16 [get_ports {hdmi_b_p}]
 #
-#set_property PACKAGE_PIN W1 [get_ports {hdmi_vcc}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_vcc}]
+set_property PACKAGE_PIN H20 [get_ports {hdmi_vcc}]; #data2-8
+set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_vcc}]
 #
 # 
 ##set_property PACKAGE_PIN P20 [get_ports rxd]
@@ -72,27 +71,28 @@ set_property IOSTANDARD LVCMOS33 [get_ports *_led]
 ##set_property PACKAGE_PIN T3 [get_ports key]
 ##set_property IOSTANDARD LVCMOS33 [get_ports key]
 #
-#set_property PACKAGE_PIN N22 [get_ports {video[0]}]
-#set_property PACKAGE_PIN N20 [get_ports {video[1]}]
-#set_property PACKAGE_PIN N18 [get_ports {video[2]}]
-#set_property PACKAGE_PIN K18 [get_ports {video[3]}]
-#set_property PACKAGE_PIN M18 [get_ports {video[4]}]
-#set_property PACKAGE_PIN M15 [get_ports {video[5]}]
-#set_property PACKAGE_PIN U20 [get_ports {video[6]}]
-#set_property PACKAGE_PIN T21 [get_ports {video[7]}]
+set_property PACKAGE_PIN A20 [get_ports {video[0]}]; #data1-5
+set_property PACKAGE_PIN B19 [get_ports {video[1]}]; #data1-7
+set_property PACKAGE_PIN C20 [get_ports {video[2]}]; #data1-9
+set_property PACKAGE_PIN H17 [get_ports {video[3]}]; #data1-11
+set_property PACKAGE_PIN D20 [get_ports {video[4]}]; #data1-13
+set_property PACKAGE_PIN H18 [get_ports {video[5]}]; #data1-15
+set_property PACKAGE_PIN F20 [get_ports {video[6]}]; #data1-17
+set_property PACKAGE_PIN F19 [get_ports {video[7]}]; #data1-19
+#
+set_property IOSTANDARD LVCMOS33 [get_ports {video[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {video[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {video[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {video[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {video[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {video[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {video[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {video[7]}]
 #
-#set_property IOSTANDARD LVCMOS33 [get_ports {video[0]}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {video[1]}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {video[2]}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {video[3]}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {video[4]}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {video[5]}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {video[6]}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {video[7]}]
+set_property PACKAGE_PIN H16 [get_ports {pclk_in}]; #data1-6
+set_property PACKAGE_PIN D18 [get_ports {vsync_in}]; #data1-14
+set_property PACKAGE_PIN D19 [get_ports {hsync_in}]; #data1-16
 #
-#set_property PACKAGE_PIN W19 [get_ports {pclk_in}]
-#set_property PACKAGE_PIN R18 [get_ports {vsync_in}]
-#set_property PACKAGE_PIN Y18 [get_ports {hsync_in}]
 #set_property PACKAGE_PIN P16 [get_ports {r_out}]
 #set_property PACKAGE_PIN V18 [get_ports {g_out}]
 #set_property PACKAGE_PIN P15 [get_ports {b_out}]
@@ -101,9 +101,9 @@ set_property IOSTANDARD LVCMOS33 [get_ports *_led]
 #set_property PACKAGE_PIN N13 [get_ports {vsync_out}]
 #
 #
-#set_property IOSTANDARD LVCMOS33 [get_ports {pclk_in}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {vsync_in}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {hsync_in}]
+set_property IOSTANDARD LVCMOS33 [get_ports {pclk_in}] 
+set_property IOSTANDARD LVCMOS33 [get_ports {vsync_in}]
+set_property IOSTANDARD LVCMOS33 [get_ports {hsync_in}]
 #set_property IOSTANDARD LVCMOS33 [get_ports {r_out}]
 #set_property IOSTANDARD LVCMOS33 [get_ports {g_out}]
 #set_property IOSTANDARD LVCMOS33 [get_ports {b_out}]
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
index f60e80e..ec170c9 100644
--- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -104,6 +104,8 @@ begin
 
 video_lut<= (video(0),video(1),video(2) xor video(3),video(4),video(5),video(6) xor video(7));
 
+hdmi_vcc <='1';
+
 
     process (i_clk, sys_rst_n)
     begin
diff --git a/fpga/hp_lcd_driver/zynq7.mk b/fpga/hp_lcd_driver/zynq7.mk
index d04e7ec..db9630a 100644
--- a/fpga/hp_lcd_driver/zynq7.mk
+++ b/fpga/hp_lcd_driver/zynq7.mk
@@ -1,6 +1,8 @@
 BUILD=build_${BOARD}
 
 IP= \
+	zynq7_ip/mmcm_0.tcl \
+	zynq7_ip/mmcm_1.tcl \
 	zynq7_ip/blk_mem_gen_0.tcl \
 	zynq7_ip/processing_system7_0.tcl 
 
diff --git a/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl b/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl
index 2b6d45f..3e97f4a 100644
--- a/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl
+++ b/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl
@@ -31,10 +31,10 @@ append generics { } "use_pclk=$use_pclk"
 set_property generic "$generics" [current_fileset]
 puts $generics
 
+read_ip $ip_dir/mmcm_0/mmcm_0.xci
+read_ip $ip_dir/mmcm_1/mmcm_1.xci
 read_ip $ip_dir/blk_mem_gen_0/blk_mem_gen_0.xci
 read_ip $ip_dir/processing_system7_0/processing_system7_0.xci
-#read_ip $ip_dir/mmcm_0/mmcm_0.xci
-#read_ip $ip_dir/mmcm_1/mmcm_1.xci
 
 read_xdc $normal_xdc
 
diff --git a/fpga/hp_lcd_driver/zynq7_ip/mmcm_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/mmcm_0.tcl
new file mode 100644
index 0000000..089476d
--- /dev/null
+++ b/fpga/hp_lcd_driver/zynq7_ip/mmcm_0.tcl
@@ -0,0 +1,38 @@
+set source_dir [file dirname [file dirname [file normalize [info script]]]]
+
+source $source_dir/zynq7_config.tcl
+
+create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name mmcm_0 -dir $ip_dir
+
+set_property -dict [list \
+	CONFIG.PRIM_IN_FREQ {50} \
+	CONFIG.CLKOUT2_USED {true} \
+	CONFIG.CLKOUT3_USED {true} \
+	CONFIG.CLKOUT4_USED {true} \
+	CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {260} \
+	CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {86.667} \
+	CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {52} \
+	CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {26} \
+	CONFIG.CLKIN1_JITTER_PS {200.0} \
+	CONFIG.MMCM_CLKFBOUT_MULT_F {26.000} \
+	CONFIG.MMCM_CLKIN1_PERIOD {20.000} \
+	CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
+	CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} \
+	CONFIG.MMCM_CLKOUT1_DIVIDE {15} \
+	CONFIG.MMCM_CLKOUT2_DIVIDE {25} \
+	CONFIG.MMCM_CLKOUT3_DIVIDE {50} \
+	CONFIG.NUM_OUT_CLKS {4} \
+	CONFIG.CLKOUT1_JITTER {120.627} \
+	CONFIG.CLKOUT1_PHASE_ERROR {154.678} \
+	CONFIG.CLKOUT2_JITTER {146.190} \
+	CONFIG.CLKOUT2_PHASE_ERROR {154.678} \
+	CONFIG.CLKOUT3_JITTER {165.425} \
+	CONFIG.CLKOUT3_PHASE_ERROR {154.678} \
+	CONFIG.CLKOUT4_JITTER {202.151} \
+	CONFIG.CLKOUT4_PHASE_ERROR {154.678} \
+	] [get_ips mmcm_0]
+
+generate_target all [get_ips]
+
+synth_ip [get_ips]
+
diff --git a/fpga/hp_lcd_driver/zynq7_ip/mmcm_1.tcl b/fpga/hp_lcd_driver/zynq7_ip/mmcm_1.tcl
new file mode 100644
index 0000000..6420887
--- /dev/null
+++ b/fpga/hp_lcd_driver/zynq7_ip/mmcm_1.tcl
@@ -0,0 +1,35 @@
+set source_dir [file dirname [file dirname [file normalize [info script]]]]
+
+source $source_dir/zynq7_config.tcl
+
+create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name mmcm_1 -dir $ip_dir
+
+set_property -dict [list \
+	CONFIG.PRIM_IN_FREQ {50} \
+	CONFIG.CLKOUT2_USED {true} \
+	CONFIG.CLKOUT3_USED {true} \
+	CONFIG.CLKOUT4_USED {true} \
+	CONFIG.CLKOUT5_USED {false} \
+	CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {78.571} \
+	CONFIG.USE_SAFE_CLOCK_STARTUP {false} \
+	CONFIG.CLKIN1_JITTER_PS {100.0} \
+	CONFIG.CLKOUT1_DRIVES {BUFG} \
+	CONFIG.CLKOUT2_DRIVES {BUFG} \
+	CONFIG.CLKOUT3_DRIVES {BUFG} \
+	CONFIG.CLKOUT4_DRIVES {BUFG} \
+	CONFIG.CLKOUT5_DRIVES {BUFG} \
+	CONFIG.CLKOUT6_DRIVES {BUFG} \
+	CONFIG.CLKOUT7_DRIVES {BUFG} \
+	CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \
+	CONFIG.MMCM_DIVCLK_DIVIDE {1} \
+	CONFIG.MMCM_CLKFBOUT_MULT_F {11.000} \
+	CONFIG.MMCM_CLKIN1_PERIOD {20.000} \
+	CONFIG.MMCM_CLKIN2_PERIOD {20.000} \
+	CONFIG.MMCM_CLKOUT0_DIVIDE_F {7} \
+	CONFIG.NUM_OUT_CLKS {1} \
+	] [get_ips mmcm_1]
+
+generate_target all [get_ips]
+
+synth_ip [get_ips]
+
diff --git a/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl
index 67c5eda..4bd2319 100644
--- a/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl
+++ b/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl
@@ -10,12 +10,16 @@ set_property -dict [list \
 	CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {25} \
 	CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {250} \
 	CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {100} \
+	CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
 	CONFIG.PCW_USE_S_AXI_HP0 {1} \
 	CONFIG.PCW_USE_HIGH_OCM {1} \
+	CONFIG.PCW_EN_CLK0_PORT {1} \
 	CONFIG.PCW_EN_CLK1_PORT {1} \
 	CONFIG.PCW_EN_CLK2_PORT {1} \
+	CONFIG.PCW_EN_CLK3_PORT {1} \
 	CONFIG.PCW_EN_RST1_PORT {1} \
 	CONFIG.PCW_EN_RST2_PORT {1} \
+	CONFIG.PCW_EN_RST3_PORT {1} \
 	CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
 	CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J128M16 HA-15E} \
 	CONFIG.PCW_NAND_PERIPHERAL_ENABLE {1} \
diff --git a/fpga/hp_lcd_driver/zynq_wrapper.vhdl b/fpga/hp_lcd_driver/zynq_wrapper.vhdl
index 4323aca..8e3bcf4 100644
--- a/fpga/hp_lcd_driver/zynq_wrapper.vhdl
+++ b/fpga/hp_lcd_driver/zynq_wrapper.vhdl
@@ -30,7 +30,13 @@ use UNISIM.vcomponents.all;
 
 
 entity zynq_wrapper is
-
+    generic (input_video_width    : natural := 2;
+	     video_width : natural :=2;
+             addr_width     : natural := 18;
+             phase_slip     : natural := 320;
+             i_clk_multiple : natural := 4;
+             use_pclk       : natural := 0;
+             target         : string  := "zynq7");
   port (
     -- ddr
     ddr_addr_io          : inout std_logic_vector (14 downto 0);
@@ -66,8 +72,25 @@ entity zynq_wrapper is
     fixed_io_ps_porb_io  : inout std_logic;
     fixed_io_ps_srstb_io : inout std_logic;
     green_led            : out   std_logic;
-    red_led              : out   std_logic);
-
+    red_led              : out   std_logic;
+
+--in
+          video     : in  std_logic_vector(input_video_width -1 downto 0);
+          hsync_in  : in  std_logic;
+          vsync_in  : in  std_logic;
+          pclk_in   : in  std_logic;
+-- hdmi
+          hdmi_c_p  : out std_logic;
+          hdmi_c_n  : out std_logic;
+          hdmi_r_p  : out std_logic;
+          hdmi_r_n  : out std_logic;
+          hdmi_g_p  : out std_logic;
+          hdmi_g_n  : out std_logic;
+          hdmi_b_p  : out std_logic;
+          hdmi_b_n  : out std_logic;
+          hdmi_vcc  : out std_logic
+);
+ 
 end entity zynq_wrapper;
 
 
@@ -114,15 +137,48 @@ signal run:std_logic;
 
 signal eth0_mdio_mdio_i:std_logic;
 signal eth0_mdio_mdio_o:std_logic;
-Signal eth0_mdio_mdio_t:std_logic;
+signal eth0_mdio_mdio_t:std_logic;
 
+signal clk_50m:std_logic;
+signal sys_rst_n:std_logic;
 
 
 begin
 
-  -----------------------------------------------------------------------------
-  -- Component Instatiations
-  -----------------------------------------------------------------------------
+
+clk_50m <= hp0_aclk;
+
+hp_lcd_driver_i: entity work.hp_lcd_driver 
+    generic map (
+	input_video_width => input_video_width,
+	video_width => video_width,
+	addr_width => addr_width,
+	phase_slip => phase_slip,
+	i_clk_multiple => i_clk_multiple,
+	use_pclk => use_pclk,
+	target => target)
+    port map  (clk_50m =>clk_50m,
+          sys_rst_n  => sys_rst_n,
+          video   => video,
+          hsync_in =>hsync_in,
+          vsync_in =>vsync_in,
+          pclk_in  =>pclk_in,
+          r_out =>open,
+          b_out   =>open,
+          g_out    =>open,
+          hsync_out =>open,
+          vsync_out => open,
+          hdmi_c_p  =>hdmi_c_p,
+          hdmi_c_n =>hdmi_c_n,
+          hdmi_r_p  => hdmi_r_p,
+          hdmi_r_n => hdmi_r_n,
+          hdmi_g_p => hdmi_g_p,
+          hdmi_g_n => hdmi_g_n,
+          hdmi_b_p => hdmi_b_p,
+          hdmi_b_n => hdmi_b_n,
+          hdmi_vcc => hdmi_vcc,
+          i_clk_out => open,
+	led =>open);
 
   processing_system7_0_i : entity work.processing_system7_0
     port map (
@@ -144,13 +200,18 @@ begin
       FCLK_CLK0          => eth0_clk_o,
       FCLK_CLK1		 => gp0_aclk,
       FCLK_CLK2		 => hp0_aclk,
+      FCLK_CLK2		 => clk_50m,
       FCLK_RESET1_N  =>     gp0_nrst,
       FCLK_RESET2_N  =>     hp0_nrst,
+      FCLK_RESET3_N  =>     sys_rst_n,
 
       ENET0_GMII_RX_CLK  => eth0_gmii_rx_clk_i,
       ENET0_GMII_RX_DV   => eth0_gmii_rx_dv_i,
       ENET0_GMII_RXD     => eth0_gmii_rxd,
       ENET0_GMII_RX_ER => '0',
+      ENET0_GMII_COL => '0',
+      ENET0_GMII_CRS => '0',
+
 
       ENET0_GMII_TX_CLK  => eth0_gmii_tx_clk_i,
       ENET0_GMII_TX_EN   => eth0_gmii_tx_en_o,