sync, and alternate tmds_encoders

4 files changed, 68 insertions, 0 deletions

diff --git a/fpga/ebaz4205/doc/DOC/EM6GD16EWKG.pdf b/fpga/ebaz4205/doc/DOC/EM6GD16EWKG.pdf
new file mode 100644
index 0000000..232d4ce
--- /dev/null
+++ b/fpga/ebaz4205/doc/DOC/EM6GD16EWKG.pdf
diff --git a/fpga/ebaz4205/ebaz4205_fpga/.gitignore b/fpga/ebaz4205/ebaz4205_fpga/.gitignore
index 336fdb9..237b1b4 100644
--- a/fpga/ebaz4205/ebaz4205_fpga/.gitignore
+++ b/fpga/ebaz4205/ebaz4205_fpga/.gitignore
@@ -1,2 +1,4 @@
 build/
 hdlmake/
+LICENSE
+NOT/
diff --git a/fpga/ebaz4205/ebaz4205_fpga/README.md b/fpga/ebaz4205/ebaz4205_fpga/README.md
new file mode 100644
index 0000000..892164f
--- /dev/null
+++ b/fpga/ebaz4205/ebaz4205_fpga/README.md
@@ -0,0 +1,45 @@
+# ebaz4205_fpga
+
+The EBAZ4205 was originally developed as cryptomining control board.
+Due to it's low price on the marked it is also perfect to learn
+the Zynq platform. This repo provides a minimal FPGA Design.
+
+## Maintainer
+
+	Lukas Lichtl (admin@embed-me.com)
+
+## Hardware Support
+
+There seem to be two hardware versions currently sold, one with a
+PHY oscillator mounted and one where it is missing.
+This design current supports both versions.
+
+## Dependencies
+
+The configuration/makefile generation depends on:
+
+* [hdlmake](https://hdlmake.readthedocs.io/en/master/)
+
+The build depends on:
+
+* [Xilinx Vivado](https://www.xilinx.com/products/design-tools/vivado.html)
+
+## Configure
+
+In order to generate the Makefile for the build, make sure that hdlmake
+is in the path and run the following commands:
+
+	cd build
+	hdlmake
+
+## Build
+
+The build process requires Xilinx Vivado. To generate a bitstream run:
+
+	make
+
+## Vivado GUI
+
+To open the design in the Vivado GUI once the build is done:
+
+	vivado ebaz4205_top.xpr
\ No newline at end of file
diff --git a/fpga/ebaz4205/src/uboot-debug.patch b/fpga/ebaz4205/src/uboot-debug.patch
new file mode 100644
index 0000000..b645fba
--- /dev/null
+++ b/fpga/ebaz4205/src/uboot-debug.patch
@@ -0,0 +1,21 @@
+diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
+index e5f55771..489f71f5 100644
+--- a/arch/arm/mach-zynq/cpu.c
++++ b/arch/arm/mach-zynq/cpu.c
+@@ -137,8 +137,16 @@ int print_cpuinfo(void)
+ 	if (version > (PCW_SILICON_VERSION_3 << 1))
+ 		version += 1;
+ 
++
++
+ 	printf("CPU:   Zynq %s\n", zynq_fpga_descs[cpu_id].devicename);
+ 	printf("Silicon: v%d.%d\n", version >> 1, version & 1);
++
++	zynq_slcr_unlock();
++	version=readl(&slcr_base->ocm_cfg);
++	zynq_slcr_lock();
++
++	printf("SCLR_BASE=%p, &OCM_CFG=%p, OCM_CFG=0x%08x\n",slcr_base,&slcr_base->ocm_cfg,version);
+ 	return 0;
+ }
+ #endif