good, but not getting timing closure

8 files changed, 120 insertions, 27 deletions

diff --git a/fpga/ebaz4205/src/ebaz4205-zynq7.dts b/fpga/ebaz4205/src/ebaz4205-zynq7.dts
index 0d3a7c1..9283b09 100644
--- a/fpga/ebaz4205/src/ebaz4205-zynq7.dts
+++ b/fpga/ebaz4205/src/ebaz4205-zynq7.dts
@@ -24,6 +24,7 @@
         compatible = "jmm,video-capture-device";
         status = "okay";
 	gpios = <&gpio0 56 0>;
+	reg = <0xfffc0000 0x40000>;
 };
 
 
diff --git a/fpga/hp_lcd_driver/Makefile b/fpga/hp_lcd_driver/Makefile
index 8c0c55d..6b72967 100644
--- a/fpga/hp_lcd_driver/Makefile
+++ b/fpga/hp_lcd_driver/Makefile
@@ -1,11 +1,13 @@
-TARGETS= ebaz4205 rando_a7 #smh-ac415b  #spartan6 #ep4ce6 smh-ac415
+DIP=10.16.66.113
+TARGETS= ebaz4205 #rando_a7 #smh-ac415b  #spartan6 #ep4ce6 smh-ac415
 #fish:smh-ac415
 
 #better_default: build_rando_a7/hp_lcd_driver.svf
 #	./prog_a7
 
-#better_default: build_ebaz4205/out/hp_lcd_driver.bin
-#	scp build_ebaz4205/out/hp_lcd_driver.bin 10.16.66.163:/boot/uboot/hp_lcd_driver.bin
+better_default: ${TARGETS:%=build_%/hp_lcd_driver.svf}
+	scp build_ebaz4205/out/hp_lcd_driver.bin ${DIP}:/boot/uboot/hp_lcd_driver.bin
+	ssh -n ${DIP} reboot < /dev/null & 
 
 default: ${TARGETS:%=build_%/hp_lcd_driver.svf} 
 
diff --git a/fpga/hp_lcd_driver/artix7.mk b/fpga/hp_lcd_driver/artix7.mk
index 218797c..c20c11d 100644
--- a/fpga/hp_lcd_driver/artix7.mk
+++ b/fpga/hp_lcd_driver/artix7.mk
@@ -51,3 +51,6 @@ ${BUILD}/ip/%/stamp:artix7_ip/%.tcl
 
 
 ${BIT}: ${BUILD}/build.stamp
+
+clean:
+	/bin/rm -rf ${BUILD}
diff --git a/fpga/hp_lcd_driver/ebaz4205.xdc b/fpga/hp_lcd_driver/ebaz4205.xdc
index f5e5c93..9c13036 100644
--- a/fpga/hp_lcd_driver/ebaz4205.xdc
+++ b/fpga/hp_lcd_driver/ebaz4205.xdc
@@ -33,14 +33,18 @@ set_property IOSTANDARD LVCMOS33 [get_ports *_led]
 #set_property PACKAGE_PIN T1 [get_ports {led_1}]
 #set_property IOSTANDARD LVCMOS33 [get_ports {led_1}]
 
-set_property PACKAGE_PIN G19 [get_ports {hdmi_r_p}]; #data2-5
-set_property PACKAGE_PIN G20 [get_ports {hdmi_r_n}]; #data2-7
+set_property PACKAGE_PIN G19 [get_ports {hdmi_b_p}]; #data2-5 
+set_property PACKAGE_PIN G20 [get_ports {hdmi_b_n}]; #data2-7
 set_property PACKAGE_PIN K19 [get_ports {hdmi_g_p}]; #data2-13
 set_property PACKAGE_PIN J19 [get_ports {hdmi_g_n}]; #data2-9
-set_property PACKAGE_PIN L19 [get_ports {hdmi_b_p}]; #data2-16
-set_property PACKAGE_PIN L20 [get_ports {hdmi_b_n}]; #data2-18
+#set_property PACKAGE_PIN T20 [get_ports {hdmi_g_p}]; #data3-16
+#set_property PACKAGE_PIN U20 [get_ports {hdmi_g_n}]; #data3-17
+set_property PACKAGE_PIN L19 [get_ports {hdmi_r_p}]; #data2-16
+set_property PACKAGE_PIN L20 [get_ports {hdmi_r_n}]; #data2-18
 set_property PACKAGE_PIN L16 [get_ports {hdmi_c_p}]; #data2-15
 set_property PACKAGE_PIN L17 [get_ports {hdmi_c_n}]; #data2-20
+#set_property PACKAGE_PIN N17 [get_ports {hdmi_c_p}]; #data3-9
+#set_property PACKAGE_PIN P18 [get_ports {hdmi_c_n}]; #data3-7
 
 set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_p}]
 set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_n}]
@@ -59,7 +63,7 @@ set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_n}]
 ##set_property DRIVE 16 [get_ports {hdmi_g_n}]
 ##set_property DRIVE 16 [get_ports {hdmi_b_p}]
 #
-set_property PACKAGE_PIN H20 [get_ports {hdmi_vcc}]; #data2-8
+set_property PACKAGE_PIN K18 [get_ports {hdmi_vcc}]; #data2-11 (12 is gnd)
 set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_vcc}]
 #
 # 
@@ -72,14 +76,14 @@ set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_vcc}]
 ##set_property IOSTANDARD LVCMOS33 [get_ports key]
 #
 set_property PACKAGE_PIN A20 [get_ports {video[0]}]; #data1-5
-set_property PACKAGE_PIN B19 [get_ports {video[1]}]; #data1-7
-set_property PACKAGE_PIN C20 [get_ports {video[2]}]; #data1-9
-set_property PACKAGE_PIN H17 [get_ports {video[3]}]; #data1-11
+set_property PACKAGE_PIN H16 [get_ports {video[1]}]; #data1-6
+set_property PACKAGE_PIN B19 [get_ports {video[2]}]; #data1-7
+set_property PACKAGE_PIN B20 [get_ports {video[3]}]; #data1-8
 set_property PACKAGE_PIN D20 [get_ports {video[4]}]; #data1-13
-set_property PACKAGE_PIN H18 [get_ports {video[5]}]; #data1-15
-set_property PACKAGE_PIN F20 [get_ports {video[6]}]; #data1-17
-set_property PACKAGE_PIN F19 [get_ports {video[7]}]; #data1-19
-#
+set_property PACKAGE_PIN D18 [get_ports {video[5]}]; #data1-14
+set_property PACKAGE_PIN H18 [get_ports {video[6]}]; #data1-15
+set_property PACKAGE_PIN D19 [get_ports {video[7]}]; #data1-16
+##
 set_property IOSTANDARD LVCMOS33 [get_ports {video[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {video[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {video[2]}]
@@ -89,9 +93,10 @@ set_property IOSTANDARD LVCMOS33 [get_ports {video[5]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {video[6]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {video[7]}]
 #
-set_property PACKAGE_PIN H16 [get_ports {pclk_in}]; #data1-6
-set_property PACKAGE_PIN D18 [get_ports {vsync_in}]; #data1-14
-set_property PACKAGE_PIN D19 [get_ports {hsync_in}]; #data1-16
+set_property PACKAGE_PIN H17 [get_ports {pclk_in}]; #data1-11 (12 is gnd)
+
+set_property PACKAGE_PIN F19 [get_ports {vsync_in}]; #data1-19
+set_property PACKAGE_PIN K17 [get_ports {hsync_in}]; #data1-20
 #
 #set_property PACKAGE_PIN P16 [get_ports {r_out}]
 #set_property PACKAGE_PIN V18 [get_ports {g_out}]
@@ -119,7 +124,11 @@ set_property IOSTANDARD LVCMOS33 [get_ports {hsync_in}]
 ##set_false_path -from [get_ports pci_exp_rst_n]
 #
 
-set_false_path -from [get_clocks clk_out4_mmcm_0] -to [get_clocks clk_out1_mmcm_0]
+#set_false_path -from [get_clocks clk_out4_mmcm_0] -to [get_clocks clk_out1_mmcm_0]
+#
+
+
+exit
 
 
 
@@ -138,5 +147,63 @@ set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property CFGBVS VCCO [current_design]
 
 
-
-
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[0]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[0]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[0]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[0]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[0]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[0]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[0]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[0]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[1]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[1]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[1]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[1]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[1]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[1]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[1]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[1]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[2]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[2]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[2]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[2]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[2]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[2]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[2]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[2]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[3]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[3]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[3]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[3]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[3]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[3]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[3]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[3]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[4]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[4]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[4]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[4]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[4]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[4]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[4]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[4]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[5]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[5]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[5]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[5]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[5]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[5]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[5]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[5]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[6]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[6]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[6]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[6]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[6]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[6]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[6]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[6]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[7]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[7]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[7]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[7]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[7]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[7]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[7]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[7]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[8]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[8]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[8]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[8]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[8]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[8]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[8]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[8]/D}]
+#
+#
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_r/ld_reg[9]/C}] -to [get_pins {common_i/output0/tmds_o/phy_r/ld2_reg[9]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_g/ld_reg[9]/C}] -to [get_pins {common_i/output0/tmds_o/phy_g/ld2_reg[9]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_b/ld_reg[9]/C}] -to [get_pins {common_i/output0/tmds_o/phy_b/ld2_reg[9]/D}]
+#set_multicycle_path 5 -setup -from [get_pins {common_i/output0/tmds_o/phy_c/ld_reg[9]/C}] -to [get_pins {common_i/output0/tmds_o/phy_c/ld2_reg[9]/D}]
+#
+#
diff --git a/fpga/hp_lcd_driver/tmds_output_artix7.vhdl b/fpga/hp_lcd_driver/tmds_output_artix7.vhdl
index 6c91041..8749d3f 100644
--- a/fpga/hp_lcd_driver/tmds_output_artix7.vhdl
+++ b/fpga/hp_lcd_driver/tmds_output_artix7.vhdl
@@ -35,7 +35,7 @@ end tmds_output;
 architecture beh of tmds_output is
 
     signal phy_reset : std_logic;
-    signal b         : natural := 0;
+    signal b         : natural range 0 to 9:= 0;
 
 
 begin
diff --git a/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl b/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl
index 722467b..26f29c0 100644
--- a/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl
+++ b/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl
@@ -69,6 +69,9 @@ begin
     process(phy_clk)
     begin
         if rising_edge(phy_clk) then
+--	    if b=5 then
+--		ld2<=ld;
+--		end if;
             if b = 0 then
                 sr <= ld;
             else
diff --git a/fpga/hp_lcd_driver/vnc_serializer.vhdl b/fpga/hp_lcd_driver/vnc_serializer.vhdl
index 855c2d7..9ec89a8 100644
--- a/fpga/hp_lcd_driver/vnc_serializer.vhdl
+++ b/fpga/hp_lcd_driver/vnc_serializer.vhdl
@@ -18,26 +18,38 @@ end vnc_serializer;
 architecture Behavioural of vnc_serializer is
 
 
-    type REGS is array (0 to 7) of std_logic_vector(video_width -1 downto 0);
+    --type REGS is array (0 to 7) of std_logic_vector(video_width-1 downto 0);
+    type REGS is array (0 to 7) of std_logic_vector(7 downto 0);
 
     signal reg        : REGS;
     signal i          : natural := 0;
     signal wren       : std_logic;
     signal next_index : std_logic;
     signal index      : std_logic;
+    signal rgb	      : std_logic_vector(7 downto 0);
 begin
 
+    rgb(2 downto 0)   <= "111" when vnc_data(0)='1' else
+                        "000";
+    rgb(5 downto 3)   <= "111" when vnc_data(1)='1' and vnc_data(3)='1' else
+                         "100" when vnc_data(1)='1'  else
+                         "000";
+    rgb(7 downto 6)   <= "11" when vnc_data(2)='1' and vnc_data(3)='1' else
+                         "10" when vnc_data(2)='1'  else
+                         "00";
+
+
     process (clk)
     begin
         if rising_edge(clk) then
             if vnc_valid = '1' then
                 if vnc_index = '1' then
-                    reg(0)     <= vnc_data;
+                    reg(0)<=rgb;
                     next_index <= '1';
                     i          <= 1;
                     wren       <= '0';
                 else
-                    reg(i) <= vnc_data;
+		    reg(i) <=rgb;
                     if i /= 7 then
                         i    <= i+1;
                         wren <= '0';
@@ -57,8 +69,9 @@ begin
 
 
     g_j : for j in 0 to 7 generate
-        fifo_data(((j*8)+video_width-1) downto (j*8))   <= reg(j);
-        fifo_data(((j*8)+7) downto ((j*8)+video_width)) <= (others => '0');
+--        fifo_data(((j*8)+video_width-1) downto (j*8))   <= reg(j);
+--        fifo_data(((j*8)+7) downto ((j*8)+video_width)) <= (others => '0');
+        fifo_data(((j*8)+7) downto (j*8))   <= reg(j);
     end generate g_j;
 
     fifo_data(64) <= index;
diff --git a/fpga/hp_lcd_driver/zynq7.mk b/fpga/hp_lcd_driver/zynq7.mk
index c99e325..e6acad8 100644
--- a/fpga/hp_lcd_driver/zynq7.mk
+++ b/fpga/hp_lcd_driver/zynq7.mk
@@ -58,3 +58,7 @@ ${BUILD}/ip/%/stamp:zynq7_ip/%.tcl
 
 
 ${BIT}: ${BUILD}/build.stamp
+
+clean:
+	/bin/rm -rf ${BUILD}
+