diff options
Diffstat (limited to 'boiler-monster/stm32/app/main.c')
| -rw-r--r-- | boiler-monster/stm32/app/main.c | 134 |
1 files changed, 134 insertions, 0 deletions
diff --git a/boiler-monster/stm32/app/main.c b/boiler-monster/stm32/app/main.c new file mode 100644 index 0000000..5ceb4af --- /dev/null +++ b/boiler-monster/stm32/app/main.c @@ -0,0 +1,134 @@ +#include "project.h" +extern uint32_t dfu_flag; + +extern volatile uint32_t vector_table[]; + + +void reset_hardware (void) +{ + int i; + + rcc_periph_reset_pulse (RST_OTGFS); + rcc_periph_reset_pulse (RST_ETHMAC); + rcc_periph_reset_pulse (RST_AFIO); + rcc_periph_reset_pulse (RST_GPIOA); + rcc_periph_reset_pulse (RST_GPIOB); + rcc_periph_reset_pulse (RST_GPIOC); + rcc_periph_reset_pulse (RST_GPIOD); + rcc_periph_reset_pulse (RST_GPIOE); + rcc_periph_reset_pulse (RST_GPIOF); + rcc_periph_reset_pulse (RST_GPIOG); + rcc_periph_reset_pulse (RST_ADC1); + rcc_periph_reset_pulse (RST_ADC2); + rcc_periph_reset_pulse (RST_TIM1); + rcc_periph_reset_pulse (RST_SPI1); + rcc_periph_reset_pulse (RST_TIM8); + rcc_periph_reset_pulse (RST_USART1); + rcc_periph_reset_pulse (RST_ADC3); + rcc_periph_reset_pulse (RST_TIM15); + rcc_periph_reset_pulse (RST_TIM16); + rcc_periph_reset_pulse (RST_TIM17); + rcc_periph_reset_pulse (RST_TIM9); + rcc_periph_reset_pulse (RST_TIM10); + rcc_periph_reset_pulse (RST_TIM11); + rcc_periph_reset_pulse (RST_TIM2); + rcc_periph_reset_pulse (RST_TIM3); + rcc_periph_reset_pulse (RST_TIM4); + rcc_periph_reset_pulse (RST_TIM5); + rcc_periph_reset_pulse (RST_TIM6); + rcc_periph_reset_pulse (RST_TIM7); + rcc_periph_reset_pulse (RST_TIM12); + rcc_periph_reset_pulse (RST_TIM13); + rcc_periph_reset_pulse (RST_TIM14); + rcc_periph_reset_pulse (RST_WWDG); + rcc_periph_reset_pulse (RST_SPI2); + rcc_periph_reset_pulse (RST_SPI3); + rcc_periph_reset_pulse (RST_USART2); + rcc_periph_reset_pulse (RST_USART3); + rcc_periph_reset_pulse (RST_UART4); + rcc_periph_reset_pulse (RST_UART5); + rcc_periph_reset_pulse (RST_I2C1); + rcc_periph_reset_pulse (RST_I2C2); + rcc_periph_reset_pulse (RST_USB); + rcc_periph_reset_pulse (RST_CAN); + rcc_periph_reset_pulse (RST_CAN1); + rcc_periph_reset_pulse (RST_CAN2); + rcc_periph_reset_pulse (RST_BKP); + rcc_periph_reset_pulse (RST_PWR); + rcc_periph_reset_pulse (RST_DAC); + rcc_periph_reset_pulse (RST_CEC); + + + for (i = 0; i < NVIC_IRQ_COUNT; ++i) + nvic_disable_irq (i); + +} + + +int +main (void) +{ + + SCB_VTOR = (uint32_t) &vector_table; + asm volatile ("msr msp, %0"::"g" (vector_table[0])); + + reset_hardware(); + + + + // rcc_clock_setup_in_hsi_out_48mhz (); + //nvic_set_priority_grouping(NVIC_PriorityGroup_4); + + /*set up pll */ + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + + /*turn on clocks to periferals */ + rcc_periph_clock_enable (RCC_GPIOA); + rcc_periph_clock_enable (RCC_GPIOB); + rcc_periph_clock_enable (RCC_GPIOC); + rcc_periph_clock_enable (RCC_AFIO); + rcc_periph_clock_enable (RCC_USART1); + rcc_periph_clock_enable (RCC_USART2); + rcc_periph_clock_enable (RCC_USART3); + rcc_periph_clock_enable (RCC_ADC1); + + dwt_enable_cycle_counter(); + + /*Change interrupt priorities so that USART trumps Timer trumps ATKBD */ + nvic_set_priority (NVIC_USART1_IRQ, 0x40); + nvic_set_priority (NVIC_USART2_IRQ, 0x40); + nvic_set_priority (NVIC_USART3_IRQ, 0x40); + nvic_set_priority (NVIC_SYSTICK_IRQ, 0x80); + nvic_set_priority (NVIC_EXTI9_5_IRQ, 0xc0); + + gpio_primary_remap (AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON, 0); + + led_init(); + + usart_init(); + ticker_init(); + + pic_init(); + ot_init(); + + onewire_init(); + + pressure_init(); + adc_init(); + + + printf ("STARTUP\r\n"); + printf ("%s\r\n", scm_version); + + + for (;;) { + if (!ring_empty (&rx1_ring)) + cmd_usart_dispatch(); + + temp_dispatch(); + + } + + + return 0; +} |