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-rw-r--r--polycom_xmit/gpio.c105
1 files changed, 103 insertions, 2 deletions
diff --git a/polycom_xmit/gpio.c b/polycom_xmit/gpio.c
index 394f794..8a595ac 100644
--- a/polycom_xmit/gpio.c
+++ b/polycom_xmit/gpio.c
@@ -1,5 +1,77 @@
#include "project.h"
+
+
+static struct gpio
+{
+ int id;
+ uint32_t pin;
+ uint32_t func;
+ uint32_t bit;
+} gpios[] =
+{
+ {
+ 0, PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0, BIT0},
+ {
+ 2, PERIPHS_IO_MUX_GPIO2_U, FUNC_GPIO2, BIT2},
+ {
+ 12, PERIPHS_IO_MUX_MTDI_U, FUNC_GPIO12, BIT12},
+ {
+ 13, PERIPHS_IO_MUX_MTCK_U, FUNC_GPIO13, BIT13},
+ {
+ 14, PERIPHS_IO_MUX_MTMS_U, FUNC_GPIO14, BIT14},
+ {
+ 15, PERIPHS_IO_MUX_MTDO_U, FUNC_GPIO15, BIT15}
+};
+
+#define N_GPIOS (sizeof(gpios)/sizeof(gpios[0]))
+
+static os_timer_t gpio_timer;
+static os_timer_t gpio_intr_timer;
+
+
+void ICACHE_FLASH_ATTR
+gpio_dispatch (void)
+{
+ uint32_t v = gpio_input_get ();
+ msg_send (v);
+}
+
+
+static void ICACHE_FLASH_ATTR
+gpio_intr_timer_cb (void *arg)
+{
+ gpio_dispatch ();
+}
+
+
+static void ICACHE_FLASH_ATTR
+gpio_timer_cb (void *arg)
+{
+ gpio_dispatch ();
+}
+
+
+/* Docs say you can't call os_timer_arm in an interrupt, yet the examples do */
+
+static void
+gpio_intr_handler (void *arg)
+{
+ int i;
+ uint32 status = GPIO_REG_READ (GPIO_STATUS_ADDRESS);
+
+
+/* Clear any interrupts */
+ for (i = 0; i < N_GPIOS; ++i)
+ if (status & gpios[i].bit)
+ GPIO_REG_WRITE (GPIO_STATUS_W1TC_ADDRESS, status & gpios[i].bit);
+
+/*Arm the timer*/
+ os_timer_disarm (&gpio_intr_timer);
+ os_timer_setfn (&gpio_intr_timer, gpio_intr_timer_cb, NULL);
+ os_timer_arm (&gpio_intr_timer, 5, 0);
+}
+
void ICACHE_FLASH_ATTR
gpio_page (struct espconn *conn)
{
@@ -48,11 +120,40 @@ gpio_page (struct espconn *conn)
+
+
+
void ICACHE_FLASH_ATTR
-gpio_init(void)
+gpio_init (void)
{
+ int i;
+ ETS_GPIO_INTR_DISABLE ();
+ ETS_GPIO_INTR_ATTACH (gpio_intr_handler, NULL);
-}
+ for (i = 0; i < N_GPIOS; ++i)
+ {
+ PIN_FUNC_SELECT (gpios[i].pin, gpios[i].func);
+ PIN_PULLUP_EN (gpios[i].pin);
+
+/* disable drivers */
+ gpio_output_set (0, 0, 0, gpios[i].bit);
+
+ gpio_register_set (GPIO_PIN_ADDR (gpios[i].id),
+ GPIO_PIN_INT_TYPE_SET (GPIO_PIN_INTR_DISABLE) |
+ GPIO_PIN_PAD_DRIVER_SET (GPIO_PAD_DRIVER_DISABLE) |
+ GPIO_PIN_SOURCE_SET (GPIO_AS_PIN_SOURCE));
+ GPIO_REG_WRITE (GPIO_STATUS_W1TC_ADDRESS, gpios[i].bit);
+
+ gpio_pin_intr_state_set (GPIO_ID_PIN (gpios[i].id),
+ GPIO_PIN_INTR_ANYEDGE);
+ }
+
+ ETS_GPIO_INTR_ENABLE ();
+
+ os_timer_disarm (&gpio_timer);
+ os_timer_setfn (&gpio_timer, (os_timer_func_t *) gpio_timer_cb, NULL);
+ os_timer_arm (&gpio_timer, 10000, 1);
+}