connectbot-yubikey/open-keychain - open-keychain with patches to support ssh authentication

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author	Dominik Schürmann <dominik@dominikschuermann.de>	2014-03-30 18:04:43 +0200
committer	Dominik Schürmann <dominik@dominikschuermann.de>	2014-03-30 18:04:43 +0200
commit	6b5d60e1f4889fabf8277c0720a60e3a24ec8caf (patch)
tree	ed65b0f6204ceaed0d121b6d0238ad5afb8d7004 /OpenKeychain-API/example-app
parent	b2342744b5f8e5bce62db18f93468fc0781a2c05 (diff)
parent	be007ecc56809cc0b6d489ab09be656e2ced9c32 (diff)
download	open-keychain-6b5d60e1f4889fabf8277c0720a60e3a24ec8caf.tar.gz open-keychain-6b5d60e1f4889fabf8277c0720a60e3a24ec8caf.tar.bz2 open-keychain-6b5d60e1f4889fabf8277c0720a60e3a24ec8caf.zip

Merge pull request #491 from openpgp-keychain/edit-key

Edit key changes

Diffstat (limited to 'OpenKeychain-API/example-app')

0 files changed, 0 insertions, 0 deletions

/* drivers/net/tulip/tulip.h Copyright 2000,2001 The Linux Kernel Team Written/copyright 1994-2001 by Donald Becker. This software may be used and distributed according to the terms of the GNU General Public License, incorporated herein by reference. Please refer to Documentation/DocBook/tulip.{pdf,ps,html} for more information on this driver, or visit the project Web page at http://sourceforge.net/projects/tulip/ */ #ifndef __NET_TULIP_H__ #define __NET_TULIP_H__ #include <linux/config.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/spinlock.h> #include <linux/netdevice.h> #include <linux/timer.h> #include <linux/delay.h> #include <asm/io.h> #include <asm/irq.h> /* undefine, or define to various debugging levels (>4 == obscene levels) */ #define TULIP_DEBUG 1 /* undefine USE_IO_OPS for MMIO, define for PIO */ #ifdef CONFIG_TULIP_MMIO # undef USE_IO_OPS #else # define USE_IO_OPS 1 #endif struct tulip_chip_table { char *chip_name; int io_size; int valid_intrs; /* CSR7 interrupt enable settings */ int flags; void (*media_timer) (unsigned long data); }; enum tbl_flag { HAS_MII = 0x0001, HAS_MEDIA_TABLE = 0x0002, CSR12_IN_SROM = 0x0004, ALWAYS_CHECK_MII = 0x0008, HAS_ACPI = 0x0010, MC_HASH_ONLY = 0x0020, /* Hash-only multicast filter. */ HAS_PNICNWAY = 0x0080, HAS_NWAY = 0x0040, /* Uses internal NWay xcvr. */ HAS_INTR_MITIGATION = 0x0100, IS_ASIX = 0x0200, HAS_8023X = 0x0400, COMET_MAC_ADDR = 0x0800, HAS_PCI_MWI = 0x1000, HAS_PHY_IRQ = 0x2000, }; /* chip types. careful! order is VERY IMPORTANT here, as these * are used throughout the driver as indices into arrays */ /* Note 21142 == 21143. */ enum chips { DC21040 = 0, DC21041 = 1, DC21140 = 2, DC21142 = 3, DC21143 = 3, LC82C168, MX98713, MX98715, MX98725, AX88140, PNIC2, COMET, COMPEX9881, I21145, DM910X, CONEXANT, }; enum MediaIs { MediaIsFD = 1, MediaAlwaysFD = 2, MediaIsMII = 4, MediaIsFx = 8, MediaIs100 = 16 }; /* Offsets to the Command and Status Registers, "CSRs". All accesses must be longword instructions and quadword aligned. */ enum tulip_offsets { CSR0 = 0, CSR1 = 0x08, CSR2 = 0x10, CSR3 = 0x18, CSR4 = 0x20, CSR5 = 0x28, CSR6 = 0x30, CSR7 = 0x38, CSR8 = 0x40, CSR9 = 0x48, CSR10 = 0x50, CSR11 = 0x58, CSR12 = 0x60, CSR13 = 0x68, CSR14 = 0x70, CSR15 = 0x78, }; /* register offset and bits for CFDD PCI config reg */ enum pci_cfg_driver_reg { CFDD = 0x40, CFDD_Sleep = (1 << 31), CFDD_Snooze = (1 << 30), }; /* The bits in the CSR5 status registers, mostly interrupt sources. */ enum status_bits { TimerInt = 0x800, SytemError = 0x2000, TPLnkFail = 0x1000, TPLnkPass = 0x10, NormalIntr = 0x10000, AbnormalIntr = 0x8000, RxJabber = 0x200, RxDied = 0x100, RxNoBuf = 0x80, RxIntr = 0x40, TxFIFOUnderflow = 0x20, TxJabber = 0x08, TxNoBuf = 0x04, TxDied = 0x02, TxIntr = 0x01, }; enum tulip_mode_bits { TxThreshold = (1 << 22), FullDuplex = (1 << 9), TxOn = 0x2000, AcceptBroadcast = 0x0100, AcceptAllMulticast = 0x0080, AcceptAllPhys = 0x0040, AcceptRunt = 0x0008, RxOn = 0x0002, RxTx = (TxOn | RxOn), }; enum tulip_busconfig_bits { MWI = (1 << 24), MRL = (1 << 23), MRM = (1 << 21), CALShift = 14, BurstLenShift = 8, }; /* The Tulip Rx and Tx buffer descriptors. */ struct tulip_rx_desc { s32 status; s32 length; u32 buffer1; u32 buffer2; }; struct tulip_tx_desc { s32 status; s32 length; u32 buffer1; u32 buffer2; /* We use only buffer 1. */ }; enum desc_status_bits { DescOwned = 0x80000000, RxDescFatalErr = 0x8000, RxWholePkt = 0x0300, }; enum t21041_csr13_bits { csr13_eng = (0xEF0<<4), /* for eng. purposes only, hardcode at EF0h */ csr13_aui = (1<<3), /* clear to force 10bT, set to force AUI/BNC */ csr13_cac = (1<<2), /* CSR13/14/15 autoconfiguration */ csr13_srl = (1<<0), /* When reset, resets all SIA functions, machines */ csr13_mask_auibnc = (csr13_eng | csr13_aui | csr13_srl), csr13_mask_10bt = (csr13_eng | csr13_srl), }; enum t21143_csr6_bits { csr6_sc = (1<<31), csr6_ra = (1<<30), csr6_ign_dest_msb = (1<<26), csr6_mbo = (1<<25), csr6_scr = (1<<24), /* scramble mode flag: can't be set */ csr6_pcs = (1<<23), /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */ csr6_ttm = (1<<22), /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */ csr6_sf = (1<<21), /* Store and forward. If set ignores TR bits */ csr6_hbd = (1<<19), /* Heart beat disable. Disables SQE function in 10baseT */ csr6_ps = (1<<18), /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */ csr6_ca = (1<<17), /* Collision Offset Enable. If set uses special algorithm in low collision situations */ csr6_trh = (1<<15), /* Transmit Threshold high bit */ csr6_trl = (1<<14), /* Transmit Threshold low bit */ /*************************************************************** * This table shows transmit threshold values based on media * * and these two registers (from PNIC1 & 2 docs) Note: this is * * all meaningless if sf is set. * ***************************************************************/ /*********************************** * (trh,trl) * 100BaseTX * 10BaseT * *********************************** * (0,0) * 128 * 72 * * (0,1) * 256 * 96 * * (1,0) * 512 * 128 * * (1,1) * 1024 * 160 * ***********************************/ csr6_fc = (1<<12), /* Forces a collision in next transmission (for testing in loopback mode) */ csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */ csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */ /* set both and you get (PHY) loopback */ csr6_fd = (1<<9), /* Full duplex mode, disables hearbeat, no loopback */ csr6_pm = (1<<7), /* Pass All Multicast */ csr6_pr = (1<<6), /* Promiscuous mode */ csr6_sb = (1<<5), /* Start(1)/Stop(0) backoff counter */ csr6_if = (1<<4), /* Inverse Filtering, rejects only addresses in address table: can't be set */ csr6_pb = (1<<3), /* Pass Bad Frames, (1) causes even bad frames to be passed on */ csr6_ho = (1<<2), /* Hash-only filtering mode: can't be set */ csr6_hp = (1<<0), /* Hash/Perfect Receive Filtering Mode: can't be set */ csr6_mask_capture = (csr6_sc | csr6_ca), csr6_mask_defstate = (csr6_mask_capture | csr6_mbo), csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps), csr6_mask_hdcaptt = (csr6_mask_hdcap | csr6_trh | csr6_trl), csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd), csr6_mask_fullpromisc = (csr6_pr | csr6_pm), csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if), csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd), }; /* Keep the ring sizes a power of two for efficiency. Making the Tx ring too large decreases the effectiveness of channel bonding and packet priority. There are no ill effects from too-large receive rings. */ #undef TX_RING_SIZE #undef RX_RING_SIZE #define TX_RING_SIZE 16 #define RX_RING_SIZE 32 #define MEDIA_MASK 31 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */ #define TULIP_MIN_CACHE_LINE 8 /* in units of 32-bit words */ #if defined(__sparc__) || defined(__hppa__) /* The UltraSparc PCI controllers will disconnect at every 64-byte * crossing anyways so it makes no sense to tell Tulip to burst * any more than that. */ #define TULIP_MAX_CACHE_LINE 16 /* in units of 32-bit words */ #else #define TULIP_MAX_CACHE_LINE 32 /* in units of 32-bit words */ #endif /* Ring-wrap flag in length field, use for last ring entry.


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