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| author | Mike Stirling <opensource@mikestirling.co.uk> | 2011-08-02 22:32:14 +0100 |
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| committer | Mike Stirling <opensource@mikestirling.co.uk> | 2011-08-02 22:32:14 +0100 |
| commit | e28e9f3ac11db036e1b3c71493ecbd14a8d59eac (patch) | |
| tree | 78d3eb0c743da146bdd5a552e332a627d57f3fb8 /vidproc.vhd | |
| parent | b8eed4413b7d093d8df73dc2c5ffc83462a4a2ed (diff) | |
| download | fpga-bbc-e28e9f3ac11db036e1b3c71493ecbd14a8d59eac.tar.gz fpga-bbc-e28e9f3ac11db036e1b3c71493ecbd14a8d59eac.tar.bz2 fpga-bbc-e28e9f3ac11db036e1b3c71493ecbd14a8d59eac.zip | |
Fixed missing gate in DISEN which meant that blank lines in modes 3 and 6 weren't blank. Hopefully fixed handling of interlaced sync+video mode in CRTC ready for SAA5050 implementation.
Diffstat (limited to 'vidproc.vhd')
0 files changed, 0 insertions, 0 deletions