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| author | Mike Stirling <opensource@mikestirling.co.uk> | 2011-07-16 19:05:29 +0100 |
|---|---|---|
| committer | Mike Stirling <opensource@mikestirling.co.uk> | 2011-07-16 19:05:29 +0100 |
| commit | 3eee5c973d8373cf0735a6af1d818440b56dd4e2 (patch) | |
| tree | cda643ffb5d2ab83309795b4aa2073fbaefc0cc2 /bbc_micro_de1_tb.vhd | |
| parent | d69daefa9348fcf8fae41c99bfedcb9ce5d38ce7 (diff) | |
| download | fpga-bbc-3eee5c973d8373cf0735a6af1d818440b56dd4e2.tar.gz fpga-bbc-3eee5c973d8373cf0735a6af1d818440b56dd4e2.tar.bz2 fpga-bbc-3eee5c973d8373cf0735a6af1d818440b56dd4e2.zip | |
Fixed SRAM routing logic
Diffstat (limited to 'bbc_micro_de1_tb.vhd')
| -rw-r--r-- | bbc_micro_de1_tb.vhd | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/bbc_micro_de1_tb.vhd b/bbc_micro_de1_tb.vhd index 39df39b..29a1cc3 100644 --- a/bbc_micro_de1_tb.vhd +++ b/bbc_micro_de1_tb.vhd @@ -150,7 +150,7 @@ signal gpio_0 : std_logic_vector(35 downto 0); signal gpio_1 : std_logic_vector(35 downto 0);
signal n_reset : std_logic := '0';
-signal slow : std_logic := '0';
+signal n_slow : std_logic := '1';
type ram_t is array(0 to 65535) of std_logic_vector(15 downto 0);
signal ram : ram_t;
@@ -215,7 +215,7 @@ begin gpio_1
);
- sw <= n_reset & slow & "00000000";
+ sw <= n_reset & n_slow & "00000101";
clock_50 <= not clock_50 after 10 ns;
clock_27(0) <= not clock_27(0) after 18.5 ns;
clock_27(1) <= not clock_27(1) after 18.5 ns;
|