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author | Mike Stirling <opensource@mikestirling.co.uk> | 2011-08-06 13:32:49 +0100 |
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committer | Mike Stirling <opensource@mikestirling.co.uk> | 2011-08-06 13:32:49 +0100 |
commit | 730ace054246139c69f3aa508983c453fd4b874a (patch) | |
tree | 181ce5af59f542d81675acc83a44eb705a0fc771 | |
parent | e3e37956449ece7134b0386a3f67c304a159373b (diff) | |
download | fpga-bbc-730ace054246139c69f3aa508983c453fd4b874a.tar.gz fpga-bbc-730ace054246139c69f3aa508983c453fd4b874a.tar.bz2 fpga-bbc-730ace054246139c69f3aa508983c453fd4b874a.zip |
Added utility to generate character ROM for SAA5050. Small fix to video ULA. Added MMBEEB SD card DFS ROM.
-rw-r--r-- | vidproc.vhd | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/vidproc.vhd b/vidproc.vhd index 0825081..799e159 100644 --- a/vidproc.vhd +++ b/vidproc.vhd @@ -226,9 +226,9 @@ begin G <= (green_val and delayed_disen) xor cursor_invert;
B <= (blue_val and delayed_disen) xor cursor_invert;
else
- R <= R_IN;
- G <= G_IN;
- B <= B_IN;
+ R <= R_IN xor cursor_invert;
+ G <= G_IN xor cursor_invert;
+ B <= B_IN xor cursor_invert;
end if;
-- Display enable signal delayed by one clock
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