blob: 2eb6ee7ba94a87362898bf8b40d7f67e9f5ff8d0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
|
diff --git a/bbc_micro_de1.vhd b/bbc_micro_de1.vhd
index fa7b2e8..991fb40 100644
--- a/bbc_micro_de1.vhd
+++ b/bbc_micro_de1.vhd
@@ -781,6 +781,8 @@ begin
LEDR(2) -- WATCHPOINT
);
+ debug_aux <= (others => '0');
+
-- 6502 CPU
cpu : T65 port map (
cpu_mode,
@@ -929,7 +931,10 @@ begin
mhz4_clken,
clock
);
-
+
+ user_via_ca2_in <='0';
+ user_via_pa_in <=(others => '0');
+
--LEDG(0) <= not PS2_CLK;
--LEDG(1) <= not PS2_DAT;
@@ -972,6 +977,12 @@ begin
LEDR(5), -- IS_DONE
LEDR(4) -- IS_ERROR
);
+ AUD_ADCLRCK <= '1';
+
+ UART_TXD <= '0';
+ DRAM_ADDR <= (others => '1');
+ LEDR(9 downto 6) <= (others => '0');
+ sys_via_pb_in(3 downto 0) <= (others => '1');
-- Asynchronous reset
-- PLL is reset by external reset switch
@@ -1123,6 +1134,8 @@ begin
end case;
end if;
end process;
+
+ FL_DQ <= (others =>'Z');
-- CPU data bus mux and interrupts
cpu_di <=
@@ -1325,5 +1338,9 @@ begin
GPIO_0(0) <= not (crtc_hsync xor crtc_vsync);
GPIO_0(1) <= crtc_de;
+ GPIO_0(2) <= ld_vsync;
+ GPIO_0(3) <= ld_hsync;
+ GPIO_0(35 downto 4) <= (others => '0');
+ GPIO_1 <= (others => '0');
end architecture;
|