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diff --git a/bbc_micro_de1.vhd b/bbc_micro_de1.vhd
index 194f93a..25b3b43 100644
--- a/bbc_micro_de1.vhd
+++ b/bbc_micro_de1.vhd
@@ -1012,7 +1012,7 @@ begin
end if;
end process;
- cycle_stretch: process(clock,reset_n)
+ cycle_stretch: process(clock,reset_n,mhz2_clken)
begin
if reset_n = '0' then
cpu_cycle_mask <= '0';
@@ -1170,7 +1170,7 @@ begin
video_data <= SRAM_DQ(7 downto 0);
-- Synchronous outputs to SRAM
- process(clock,reset_n)
+ process(clock,reset_n,ram_enable,cpu_r_nw)
variable ram_write : std_logic;
begin
ram_write := ram_enable and not cpu_r_nw;
@@ -1290,9 +1290,10 @@ begin
SD_nCS <= '0'; -- CS
user_via_cb2_in <= SD_MISO; -- SDI
user_via_pb_in <= user_via_pb_out;
+
-- ROM select latch
- process(clock,reset_n)
+ process(clock,reset_n,romsel_enable)
begin
if reset_n = '0' then
romsel <= (others => '0');
@@ -1313,7 +1314,7 @@ begin
shift_lock_led_n <= ic32(7);
- process(clock,reset_n)
+ process(clock,reset_n,sys_via_pb_out)
variable bit_num : integer;
begin
bit_num := to_integer(unsigned(sys_via_pb_out(2 downto 0)));
diff --git a/debugger.vhd b/debugger.vhd
index a7a9d7d..5431b47 100644
--- a/debugger.vhd
+++ b/debugger.vhd
@@ -213,7 +213,7 @@ begin
end process;
-- Set watchpoint address
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,mode)
begin
if nRESET = '0' then
watchpoint <= (others => '1');
@@ -232,7 +232,7 @@ begin
end process;
-- Set breakpoint address
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,mode)
begin
if nRESET = '0' then
breakpoint <= (others => '1');
diff --git a/i2c_loader.vhd b/i2c_loader.vhd
index e0a7115..5152c7b 100644
--- a/i2c_loader.vhd
+++ b/i2c_loader.vhd
@@ -132,7 +132,7 @@ begin
end process;
-- The I2C loader process
- process(nRESET,CLK)
+ process(nRESET,CLK,clken)
begin
if nRESET = '0' then
scl_out <= '1';
diff --git a/mc6845.vhd b/mc6845.vhd
index c102501..c28152d 100644
--- a/mc6845.vhd
+++ b/mc6845.vhd
@@ -231,7 +231,7 @@ begin
end process; -- registers
-- Horizontal, vertical and address counters
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN)
variable ma_row_start : unsigned(13 downto 0);
variable max_scan_line : unsigned(4 downto 0);
begin
@@ -318,7 +318,7 @@ begin
-- Signals to mark hsync and half way points for generating
-- vsync in even and odd fields
- process(h_counter)
+ process(h_counter,r02_h_sync_pos)
begin
h_sync_start <= '0';
h_half_way <= '0';
@@ -332,7 +332,7 @@ begin
end process;
-- Video timing and sync counters
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN)
begin
if nRESET = '0' then
-- H
@@ -399,7 +399,7 @@ begin
end process;
-- Address generation
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN)
variable slv_line : std_logic_vector(4 downto 0);
begin
if nRESET = '0' then
@@ -423,7 +423,7 @@ begin
end process;
-- Cursor control
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN)
variable cursor_line : std_logic;
begin
-- Internal cursor enable signal delayed by 1 clock to line up
@@ -459,7 +459,7 @@ begin
end process;
-- Light pen capture
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN)
begin
if nRESET = '0' then
lpstb_i <= '0';
diff --git a/saa5050.vhd b/saa5050.vhd
index 573aaa3..d082339 100644
--- a/saa5050.vhd
+++ b/saa5050.vhd
@@ -155,7 +155,7 @@ begin
flash <= flash_counter(5) and flash_counter(4);
-- Sync inputs
- process(DI_CLOCK,nRESET)
+ process(DI_CLOCK,nRESET,DI_CLKEN)
begin
if nRESET = '0' then
di_r <= (others => '0');
@@ -169,7 +169,7 @@ begin
end process;
-- Register data into pixel clock domain
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN)
begin
if nRESET = '0' then
code <= (others => '0');
@@ -188,7 +188,7 @@ begin
gfx & code & std_logic_vector(line_addr);
-- Character row and pixel counters
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN)
begin
if nRESET = '0' then
dew_latch <= '0';
@@ -260,7 +260,7 @@ begin
end process;
-- Shift register
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN)
begin
if nRESET = '0' then
shift_reg <= (others => '0');
@@ -292,7 +292,7 @@ begin
end process;
-- Control character handling
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN)
begin
if nRESET = '0' then
fg <= (others => '1');
@@ -363,7 +363,7 @@ begin
end process;
-- Output
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN,shift_reg,flash,conceal,is_flash)
variable pixel : std_logic;
begin
pixel := shift_reg(5) and not ((flash and is_flash) or conceal);
diff --git a/vidproc.vhd b/vidproc.vhd
index 25f3d75..e53bb46 100644
--- a/vidproc.vhd
+++ b/vidproc.vhd
@@ -165,7 +165,7 @@ begin
clken_fetch <= CLKEN and not (clken_counter(0) or clken_counter(1) or clken_counter(2) or
(clken_counter(3) and not r0_crtc_2mhz));
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN)
begin
if nRESET = '0' then
clken_counter <= (others => '0');
@@ -176,7 +176,7 @@ begin
end process;
-- Fetch control
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,clken_pixel)
begin
if nRESET = '0' then
shiftreg <= (others => '0');
@@ -197,7 +197,7 @@ begin
((r0_cursor0 and not (cursor_counter(0) or cursor_counter(1))) or
(r0_cursor1 and cursor_counter(0) and not cursor_counter(1)) or
(r0_cursor2 and cursor_counter(1)));
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,clken_fetch)
begin
if nRESET = '0' then
cursor_active <= '0';
@@ -231,7 +231,7 @@ begin
-- the pixel rate we ensure that the resulting delay is minimal and
-- constant (running this at the pixel rate would cause
-- the display to move slightly depending on which mode was selected).
- process(CLOCK,nRESET)
+ process(CLOCK,nRESET,CLKEN)
variable palette_a : std_logic_vector(3 downto 0);
variable dot_val : std_logic_vector(3 downto 0);
variable red_val : std_logic;
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