1 files changed, 64 insertions, 0 deletions
diff --git a/de1/fpga-flash-nor/protocol.txt b/de1/fpga-flash-nor/protocol.txt
new file mode 100644
index 0000000..d7a1968
--- /dev/null
+++ b/de1/fpga-flash-nor/protocol.txt
@@ -0,0 +1,64 @@
+Virtual IR register (4 bits):
+
+0	- bypass
+1	- read fifo
+2	- write fifo space query
+3	- write fifo
+4	- read ready (single bit)
+5	- write reset flag (single bit; write 1 then 0)
+F	- bypass
+
+Virtual DR register 1:
+
+READ FIFO
+
+72 bits:
+-binary- -------hex-------
+VNNNCCCC DDDDDDD DDDDDDDDD		- V = valid
+	 				- N = sequence counter
+	 				- C = top 4 bits of command
+
+Read transactions can be streamed by shifting out a multiple of 72 bits.
+
+Virtual DR register 2:
+
+Reads the amount of space in the write FIFO as an 8-bit number.
+
+
+Virtual DR register 3:
+
+WRITE FIFO
+
+72 bits:
+-binary- -------hex-------
+
+000XXXXX XXXXXXXX XXXXXXXX		- noop
+
+0010XXXX XXXXXXXX CCCCCCCC		- delay for C cycles @ 20 MHz
+
+0101XXXX AAAAAAAA CCCCCCCC		- zero check
+	 Returns last address read in [63:32]
+	 Returns last datum 1's extended in [31:0] - FFFFFFFF on success
+
+0110XXXX XXXXXXXX TTTTTTTT		- read back address register, token
+	 Returns address register in [63:32]
+	 Returns token in [31:0]
+
+0111XXXX AAAAAAAA CCCCCCCC		- compute CRC32
+	 Returns last address read in [63:32]
+	 Returns Ethernet CRC32 of the region in [31:0]
+
+100SEEEE AAAAAAAA DDDDDDDD		- write cycle (address, data)
+   				          address register set to A if S=1
+					  E is byte enables; for a byte flash
+					  E should be set to 0001
+
+1011CCCC DDDDDDDD DDDDDDDD		- program bytes (C = byte count)
+
+1101XXXX AAAAAAAA CCCCCCCC		- set address register to A
+   				          read C bytes (pad output to 64 bits)
+					  if C=0 no read is done
+
+111XXXXX XXXXXXXX XXXXXXXX		- noop
+
+For vestigial writes the data should be right-justified (LSB valid)