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authorChristian Starkjohann <cs+github@obdev.at>2008-10-18 14:08:20 +0000
committerChristian Starkjohann <cs+github@obdev.at>2008-10-18 14:08:20 +0000
commit89e5d02eac39326915228b69dac0f4bcc305ff96 (patch)
tree92adcb27234b4391f15e949157fd24e7a2360333 /usbdrv
parentf095d94eddf27b2addf77eafbf466614980a3190 (diff)
downloadv-usb-89e5d02eac39326915228b69dac0f4bcc305ff96.tar.gz
v-usb-89e5d02eac39326915228b69dac0f4bcc305ff96.tar.bz2
v-usb-89e5d02eac39326915228b69dac0f4bcc305ff96.zip
- updated general comments
Diffstat (limited to 'usbdrv')
-rw-r--r--usbdrv/usbdrvasm128.inc13
1 files changed, 13 insertions, 0 deletions
diff --git a/usbdrv/usbdrvasm128.inc b/usbdrv/usbdrvasm128.inc
index 6144cbf..f300865 100644
--- a/usbdrv/usbdrvasm128.inc
+++ b/usbdrv/usbdrvasm128.inc
@@ -22,6 +22,19 @@ slight clock rate deviations of up to +/- 1%.
See usbdrv.h for a description of the entire driver.
+LIMITATIONS
+===========
+Although it may seem very handy to save the crystal and use the internal
+RC oscillator of the CPU, this method (and this module) has some serious
+limitations:
+(1) The guaranteed calibration range of the oscillator is only 8.1 MHz.
+They typical range is 14.5 MHz and most AVRs can actually reach this rate.
+(2) Writing EEPROM and Flash may be unreliable (short data lifetime) since
+the write procedure is timed from the RC oscillator.
+(3) End Of Packet detection is between bit 0 and bit 1 where the EOP condition
+may not be reliable when a hub is used. It should be in bit 1.
+(4) Code size is much larger than that of the other modules.
+
Since almost all of this code is timing critical, don't change unless you
really know what you are doing! Many parts require not only a maximum number
of CPU cycles, but even an exact number of cycles!