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| author | Christian Starkjohann <cs+github@obdev.at> | 2009-08-06 10:12:54 +0000 |
|---|---|---|
| committer | Christian Starkjohann <cs+github@obdev.at> | 2009-08-06 10:12:54 +0000 |
| commit | 7292ac41755b6c13726d71d364b5a481f5d3b80e (patch) | |
| tree | cccd8a5a3fec153b0ece3cd3966603a6ac942ccc | |
| parent | b6a66c5058b8f646f9544582da8c330887ab6bd7 (diff) | |
| download | v-usb-7292ac41755b6c13726d71d364b5a481f5d3b80e.tar.gz v-usb-7292ac41755b6c13726d71d364b5a481f5d3b80e.tar.bz2 v-usb-7292ac41755b6c13726d71d364b5a481f5d3b80e.zip | |
- minor code optimization
| -rw-r--r-- | usbdrv/usbdrvasm128.inc | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/usbdrv/usbdrvasm128.inc b/usbdrv/usbdrvasm128.inc index ff23a22..122cc75 100644 --- a/usbdrv/usbdrvasm128.inc +++ b/usbdrv/usbdrvasm128.inc @@ -218,19 +218,21 @@ unstuff0s: ifioclr USBIN, USBMINUS ;[00] ifioset USBIN, USBPLUS ;[01] rjmp bit0IsClr ;[02] executed if first expr false or second true -jumpToSe0AndStore: - rjmp se0AndStore ;[03] executed only if both bits 0 +se0AndStore: ; executed only if both bits 0 + st y+, x1 ;[15/17] cycles after start of byte + rjmp se0 ;[17/19] + bit0IsClr: ifrset phase, USBMINUS ;[04] check phase only if D- changed lpm ;[05] in phase, USBIN ;[06] <- phase (one cycle too late) ori shift, 1 << 0 ;[07] bit1AfterClr: - andi shift, ~(7 << 1) ;[08] compensated by "ori shift, 1<<1" if bit1IsSet + andi phase, USBMASK ;[08] ifioset USBIN, USBMINUS ;[09] <--- sample 1 rjmp bit1IsSet ;[10] - ifrclr phase, USBPLUS ;[11] if D- was 0 in bits 0 AND 1 and D+ was 0 in between, we have SE0 - rjmp se0AndStore ;[12] + breq se0AndStore ;[11] if D- was 0 in bits 0 AND 1 and D+ was 0 in between, we have SE0 + andi shift, ~(7 << 1) ;[12] in phase, USBIN ;[13] <- phase breq unstuff1c ;[14] rjmp bit2AfterClr ;[15] @@ -356,10 +358,6 @@ unstuff7c: nop ;[59] rjmp bit7IsSet ;[60] -se0AndStore: - st y+, x1 ;[15/17] cycles after start of byte - rjmp se0 ;[17/19] - bit7IsClr: ifrset phase, USBMINUS ;[62] check phase only if D- changed lpm ;[63] |