diff options
Diffstat (limited to 'boards/base/STM32F469i-Discovery')
7 files changed, 266 insertions, 266 deletions
diff --git a/boards/base/STM32F469i-Discovery/CubeHAL/board_STM32LTDC.h b/boards/base/STM32F469i-Discovery/CubeHAL/board_STM32LTDC.h index 59555bba..1571966b 100644 --- a/boards/base/STM32F469i-Discovery/CubeHAL/board_STM32LTDC.h +++ b/boards/base/STM32F469i-Discovery/CubeHAL/board_STM32LTDC.h @@ -118,7 +118,7 @@ static GFXINLINE void init_board(GDisplay *g) { dsiHandle.Instance = DSI; // There is only one DSI interface dsiHandle.Init.AutomaticClockLaneControl = DSI_AUTO_CLK_LANE_CTRL_ENABLE; // Automatic clock lane control: powers down the clock lane when not in use /* Highest speed = 500MHz. */ - uint16_t laneByteClk_kHz = 62500; /* 500 MHz / 8 = 62.5 MHz = 62500 kHz */ + gU16 laneByteClk_kHz = 62500; /* 500 MHz / 8 = 62.5 MHz = 62500 kHz */ /* TXEscapeCkdiv = f(LaneByteClk)/15.62 = 4 -> 500MHz/4 = 25MHz datasheet says around 20MHz */ dsiHandle.Init.TXEscapeCkdiv = laneByteClk_kHz/15620; // Low power clock relative to the laneByteClock dsiHandle.Init.NumberOfLanes = DSI_TWO_DATA_LANES; // Two data lines for the fastest transfer speed @@ -201,7 +201,7 @@ static GFXINLINE void init_board(GDisplay *g) { BSP_SDRAM_Init(); } -static GFXINLINE void set_backlight(GDisplay* g, uint8_t percent) +static GFXINLINE void set_backlight(GDisplay* g, gU8 percent) { (void)g; (void)percent; @@ -287,7 +287,7 @@ static GFXINLINE void post_init_board(GDisplay* g) * @param pParams: Pointer to parameter values table. * @retval HAL status */ -void DSI_IO_WriteCmd(uint32_t NbrParams, uint8_t *pParams) +void DSI_IO_WriteCmd(gU32 NbrParams, gU8 *pParams) { if(NbrParams <= 1) { @@ -304,7 +304,7 @@ void DSI_IO_WriteCmd(uint32_t NbrParams, uint8_t *pParams) * * @param Delay: The requested delay in ms. */ -void OTM8009A_IO_Delay(uint32_t Delay) +void OTM8009A_IO_Delay(gU32 Delay) { gfxSleepMilliseconds(Delay); } diff --git a/boards/base/STM32F469i-Discovery/CubeHAL/gmouse_lld_FT6x06_board.h b/boards/base/STM32F469i-Discovery/CubeHAL/gmouse_lld_FT6x06_board.h index c51514a5..d185f3ad 100644 --- a/boards/base/STM32F469i-Discovery/CubeHAL/gmouse_lld_FT6x06_board.h +++ b/boards/base/STM32F469i-Discovery/CubeHAL/gmouse_lld_FT6x06_board.h @@ -82,26 +82,26 @@ static GFXINLINE void release_bus(GMouse* m) { (void)m;
}
-static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
+static void write_reg(GMouse* m, gU8 reg, gU8 val) {
(void)m;
- HAL_I2C_Mem_Write(&i2cHandle, FT6x06_SLAVE_ADDR, (uint16_t)reg, I2C_MEMADD_SIZE_8BIT, &val, 1, 1000);
+ HAL_I2C_Mem_Write(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, &val, 1, 1000);
}
-static uint8_t read_byte(GMouse* m, uint8_t reg) {
+static gU8 read_byte(GMouse* m, gU8 reg) {
(void)m;
- uint8_t result;
+ gU8 result;
- HAL_I2C_Mem_Read(&i2cHandle, FT6x06_SLAVE_ADDR, (uint16_t)reg, I2C_MEMADD_SIZE_8BIT, &result, 1, 1000);
+ HAL_I2C_Mem_Read(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, &result, 1, 1000);
return result;
}
-static uint16_t read_word(GMouse* m, uint8_t reg) {
+static gU16 read_word(GMouse* m, gU8 reg) {
(void)m;
- uint8_t result[2];
+ gU8 result[2];
- HAL_I2C_Mem_Read(&i2cHandle, FT6x06_SLAVE_ADDR, (uint16_t)reg, I2C_MEMADD_SIZE_8BIT, result, 2, 1000);
+ HAL_I2C_Mem_Read(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, result, 2, 1000);
return (result[0]<<8 | result[1]);
diff --git a/boards/base/STM32F469i-Discovery/otm8009a.c b/boards/base/STM32F469i-Discovery/otm8009a.c index d408efe6..e830d53a 100644 --- a/boards/base/STM32F469i-Discovery/otm8009a.c +++ b/boards/base/STM32F469i-Discovery/otm8009a.c @@ -64,31 +64,31 @@ * @brief Constant tables of register settings used to transmit DSI
* command packets as power up initialization sequence of the KoD LCD (OTM8009A LCD Driver)
*/
-const uint8_t lcdRegData1[] = {0x80,0x09,0x01,0xFF};
-const uint8_t lcdRegData2[] = {0x80,0x09,0xFF};
-const uint8_t lcdRegData3[] = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE1};
-const uint8_t lcdRegData4[] = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE2};
-const uint8_t lcdRegData5[] = {0x79,0x79,0xD8};
-const uint8_t lcdRegData6[] = {0x00,0x01,0xB3};
-const uint8_t lcdRegData7[] = {0x85,0x01,0x00,0x84,0x01,0x00,0xCE};
-const uint8_t lcdRegData8[] = {0x18,0x04,0x03,0x39,0x00,0x00,0x00,0x18,0x03,0x03,0x3A,0x00,0x00,0x00,0xCE};
-const uint8_t lcdRegData9[] = {0x18,0x02,0x03,0x3B,0x00,0x00,0x00,0x18,0x01,0x03,0x3C,0x00,0x00,0x00,0xCE};
-const uint8_t lcdRegData10[] = {0x01,0x01,0x20,0x20,0x00,0x00,0x01,0x02,0x00,0x00,0xCF};
-const uint8_t lcdRegData11[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
-const uint8_t lcdRegData12[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
-const uint8_t lcdRegData13[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
-const uint8_t lcdRegData14[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
-const uint8_t lcdRegData15[] = {0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
-const uint8_t lcdRegData16[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0xCB};
-const uint8_t lcdRegData17[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
-const uint8_t lcdRegData18[] = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xCB};
-const uint8_t lcdRegData19[] = {0x00,0x26,0x09,0x0B,0x01,0x25,0x00,0x00,0x00,0x00,0xCC};
-const uint8_t lcdRegData20[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x26,0x0A,0x0C,0x02,0xCC};
-const uint8_t lcdRegData21[] = {0x25,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
-const uint8_t lcdRegData22[] = {0x00,0x25,0x0C,0x0A,0x02,0x26,0x00,0x00,0x00,0x00,0xCC};
-const uint8_t lcdRegData23[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0x0B,0x09,0x01,0xCC};
-const uint8_t lcdRegData24[] = {0x26,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
-const uint8_t lcdRegData25[] = {0xFF,0xFF,0xFF,0xFF};
+const gU8 lcdRegData1[] = {0x80,0x09,0x01,0xFF};
+const gU8 lcdRegData2[] = {0x80,0x09,0xFF};
+const gU8 lcdRegData3[] = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE1};
+const gU8 lcdRegData4[] = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE2};
+const gU8 lcdRegData5[] = {0x79,0x79,0xD8};
+const gU8 lcdRegData6[] = {0x00,0x01,0xB3};
+const gU8 lcdRegData7[] = {0x85,0x01,0x00,0x84,0x01,0x00,0xCE};
+const gU8 lcdRegData8[] = {0x18,0x04,0x03,0x39,0x00,0x00,0x00,0x18,0x03,0x03,0x3A,0x00,0x00,0x00,0xCE};
+const gU8 lcdRegData9[] = {0x18,0x02,0x03,0x3B,0x00,0x00,0x00,0x18,0x01,0x03,0x3C,0x00,0x00,0x00,0xCE};
+const gU8 lcdRegData10[] = {0x01,0x01,0x20,0x20,0x00,0x00,0x01,0x02,0x00,0x00,0xCF};
+const gU8 lcdRegData11[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const gU8 lcdRegData12[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const gU8 lcdRegData13[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const gU8 lcdRegData14[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const gU8 lcdRegData15[] = {0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const gU8 lcdRegData16[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0xCB};
+const gU8 lcdRegData17[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const gU8 lcdRegData18[] = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xCB};
+const gU8 lcdRegData19[] = {0x00,0x26,0x09,0x0B,0x01,0x25,0x00,0x00,0x00,0x00,0xCC};
+const gU8 lcdRegData20[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x26,0x0A,0x0C,0x02,0xCC};
+const gU8 lcdRegData21[] = {0x25,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
+const gU8 lcdRegData22[] = {0x00,0x25,0x0C,0x0A,0x02,0x26,0x00,0x00,0x00,0x00,0xCC};
+const gU8 lcdRegData23[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0x0B,0x09,0x01,0xCC};
+const gU8 lcdRegData24[] = {0x26,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
+const gU8 lcdRegData25[] = {0xFF,0xFF,0xFF,0xFF};
/*
* CASET value (Column Address Set) : X direction LCD GRAM boundaries
* depending on LCD orientation mode and PASET value (Page Address Set) : Y direction
@@ -96,65 +96,65 @@ const uint8_t lcdRegData25[] = {0xFF,0xFF,0xFF,0xFF}; * XS[15:0] = 0x000 = 0, XE[15:0] = 0x31F = 799 for landscape mode : apply to CASET
* YS[15:0] = 0x000 = 0, YE[15:0] = 0x31F = 799 for portrait mode : : apply to PASET
*/
-const uint8_t lcdRegData27[] = {0x00, 0x00, 0x03, 0x1F, OTM8009A_CMD_CASET};
+const gU8 lcdRegData27[] = {0x00, 0x00, 0x03, 0x1F, OTM8009A_CMD_CASET};
/*
* XS[15:0] = 0x000 = 0, XE[15:0] = 0x1DF = 479 for portrait mode : apply to CASET
* YS[15:0] = 0x000 = 0, YE[15:0] = 0x1DF = 479 for landscape mode : apply to PASET
*/
-const uint8_t lcdRegData28[] = {0x00, 0x00, 0x01, 0xDF, OTM8009A_CMD_PASET};
-
-
-const uint8_t ShortRegData1[] = {OTM8009A_CMD_NOP, 0x00};
-const uint8_t ShortRegData2[] = {OTM8009A_CMD_NOP, 0x80};
-const uint8_t ShortRegData3[] = {0xC4, 0x30};
-const uint8_t ShortRegData4[] = {OTM8009A_CMD_NOP, 0x8A};
-const uint8_t ShortRegData5[] = {0xC4, 0x40};
-const uint8_t ShortRegData6[] = {OTM8009A_CMD_NOP, 0xB1};
-const uint8_t ShortRegData7[] = {0xC5, 0xA9};
-const uint8_t ShortRegData8[] = {OTM8009A_CMD_NOP, 0x91};
-const uint8_t ShortRegData9[] = {0xC5, 0x34};
-const uint8_t ShortRegData10[] = {OTM8009A_CMD_NOP, 0xB4};
-const uint8_t ShortRegData11[] = {0xC0, 0x50};
-const uint8_t ShortRegData12[] = {0xD9, 0x4E};
-const uint8_t ShortRegData13[] = {OTM8009A_CMD_NOP, 0x81};
-const uint8_t ShortRegData14[] = {0xC1, 0x66};
-const uint8_t ShortRegData15[] = {OTM8009A_CMD_NOP, 0xA1};
-const uint8_t ShortRegData16[] = {0xC1, 0x08};
-const uint8_t ShortRegData17[] = {OTM8009A_CMD_NOP, 0x92};
-const uint8_t ShortRegData18[] = {0xC5, 0x01};
-const uint8_t ShortRegData19[] = {OTM8009A_CMD_NOP, 0x95};
-const uint8_t ShortRegData20[] = {OTM8009A_CMD_NOP, 0x94};
-const uint8_t ShortRegData21[] = {0xC5, 0x33};
-const uint8_t ShortRegData22[] = {OTM8009A_CMD_NOP, 0xA3};
-const uint8_t ShortRegData23[] = {0xC0, 0x1B};
-const uint8_t ShortRegData24[] = {OTM8009A_CMD_NOP, 0x82};
-const uint8_t ShortRegData25[] = {0xC5, 0x83};
-const uint8_t ShortRegData26[] = {0xC4, 0x83};
-const uint8_t ShortRegData27[] = {0xC1, 0x0E};
-const uint8_t ShortRegData28[] = {OTM8009A_CMD_NOP, 0xA6};
-const uint8_t ShortRegData29[] = {OTM8009A_CMD_NOP, 0xA0};
-const uint8_t ShortRegData30[] = {OTM8009A_CMD_NOP, 0xB0};
-const uint8_t ShortRegData31[] = {OTM8009A_CMD_NOP, 0xC0};
-const uint8_t ShortRegData32[] = {OTM8009A_CMD_NOP, 0xD0};
-const uint8_t ShortRegData33[] = {OTM8009A_CMD_NOP, 0x90};
-const uint8_t ShortRegData34[] = {OTM8009A_CMD_NOP, 0xE0};
-const uint8_t ShortRegData35[] = {OTM8009A_CMD_NOP, 0xF0};
-const uint8_t ShortRegData36[] = {OTM8009A_CMD_SLPOUT, 0x00};
-const uint8_t ShortRegData37[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB565};
-const uint8_t ShortRegData38[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB888};
-const uint8_t ShortRegData39[] = {OTM8009A_CMD_MADCTR, OTM8009A_MADCTR_MODE_LANDSCAPE};
-const uint8_t ShortRegData40[] = {OTM8009A_CMD_WRDISBV, 0x7F};
-const uint8_t ShortRegData41[] = {OTM8009A_CMD_WRCTRLD, 0x2C};
-const uint8_t ShortRegData42[] = {OTM8009A_CMD_WRCABC, 0x02};
-const uint8_t ShortRegData43[] = {OTM8009A_CMD_WRCABCMB, 0xFF};
-const uint8_t ShortRegData44[] = {OTM8009A_CMD_DISPON, 0x00};
-const uint8_t ShortRegData45[] = {OTM8009A_CMD_RAMWR, 0x00};
-const uint8_t ShortRegData46[] = {0xCF, 0x00};
-const uint8_t ShortRegData47[] = {0xC5, 0x66};
-const uint8_t ShortRegData48[] = {OTM8009A_CMD_NOP, 0xB6};
-const uint8_t ShortRegData49[] = {0xF5, 0x06};
-const uint8_t ShortRegData50[] = {OTM8009A_CMD_NOP, 0xB1};
-const uint8_t ShortRegData51[] = {0xC6, 0x06};
+const gU8 lcdRegData28[] = {0x00, 0x00, 0x01, 0xDF, OTM8009A_CMD_PASET};
+
+
+const gU8 ShortRegData1[] = {OTM8009A_CMD_NOP, 0x00};
+const gU8 ShortRegData2[] = {OTM8009A_CMD_NOP, 0x80};
+const gU8 ShortRegData3[] = {0xC4, 0x30};
+const gU8 ShortRegData4[] = {OTM8009A_CMD_NOP, 0x8A};
+const gU8 ShortRegData5[] = {0xC4, 0x40};
+const gU8 ShortRegData6[] = {OTM8009A_CMD_NOP, 0xB1};
+const gU8 ShortRegData7[] = {0xC5, 0xA9};
+const gU8 ShortRegData8[] = {OTM8009A_CMD_NOP, 0x91};
+const gU8 ShortRegData9[] = {0xC5, 0x34};
+const gU8 ShortRegData10[] = {OTM8009A_CMD_NOP, 0xB4};
+const gU8 ShortRegData11[] = {0xC0, 0x50};
+const gU8 ShortRegData12[] = {0xD9, 0x4E};
+const gU8 ShortRegData13[] = {OTM8009A_CMD_NOP, 0x81};
+const gU8 ShortRegData14[] = {0xC1, 0x66};
+const gU8 ShortRegData15[] = {OTM8009A_CMD_NOP, 0xA1};
+const gU8 ShortRegData16[] = {0xC1, 0x08};
+const gU8 ShortRegData17[] = {OTM8009A_CMD_NOP, 0x92};
+const gU8 ShortRegData18[] = {0xC5, 0x01};
+const gU8 ShortRegData19[] = {OTM8009A_CMD_NOP, 0x95};
+const gU8 ShortRegData20[] = {OTM8009A_CMD_NOP, 0x94};
+const gU8 ShortRegData21[] = {0xC5, 0x33};
+const gU8 ShortRegData22[] = {OTM8009A_CMD_NOP, 0xA3};
+const gU8 ShortRegData23[] = {0xC0, 0x1B};
+const gU8 ShortRegData24[] = {OTM8009A_CMD_NOP, 0x82};
+const gU8 ShortRegData25[] = {0xC5, 0x83};
+const gU8 ShortRegData26[] = {0xC4, 0x83};
+const gU8 ShortRegData27[] = {0xC1, 0x0E};
+const gU8 ShortRegData28[] = {OTM8009A_CMD_NOP, 0xA6};
+const gU8 ShortRegData29[] = {OTM8009A_CMD_NOP, 0xA0};
+const gU8 ShortRegData30[] = {OTM8009A_CMD_NOP, 0xB0};
+const gU8 ShortRegData31[] = {OTM8009A_CMD_NOP, 0xC0};
+const gU8 ShortRegData32[] = {OTM8009A_CMD_NOP, 0xD0};
+const gU8 ShortRegData33[] = {OTM8009A_CMD_NOP, 0x90};
+const gU8 ShortRegData34[] = {OTM8009A_CMD_NOP, 0xE0};
+const gU8 ShortRegData35[] = {OTM8009A_CMD_NOP, 0xF0};
+const gU8 ShortRegData36[] = {OTM8009A_CMD_SLPOUT, 0x00};
+const gU8 ShortRegData37[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB565};
+const gU8 ShortRegData38[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB888};
+const gU8 ShortRegData39[] = {OTM8009A_CMD_MADCTR, OTM8009A_MADCTR_MODE_LANDSCAPE};
+const gU8 ShortRegData40[] = {OTM8009A_CMD_WRDISBV, 0x7F};
+const gU8 ShortRegData41[] = {OTM8009A_CMD_WRCTRLD, 0x2C};
+const gU8 ShortRegData42[] = {OTM8009A_CMD_WRCABC, 0x02};
+const gU8 ShortRegData43[] = {OTM8009A_CMD_WRCABCMB, 0xFF};
+const gU8 ShortRegData44[] = {OTM8009A_CMD_DISPON, 0x00};
+const gU8 ShortRegData45[] = {OTM8009A_CMD_RAMWR, 0x00};
+const gU8 ShortRegData46[] = {0xCF, 0x00};
+const gU8 ShortRegData47[] = {0xC5, 0x66};
+const gU8 ShortRegData48[] = {OTM8009A_CMD_NOP, 0xB6};
+const gU8 ShortRegData49[] = {0xF5, 0x06};
+const gU8 ShortRegData50[] = {OTM8009A_CMD_NOP, 0xB1};
+const gU8 ShortRegData51[] = {0xC6, 0x06};
/**
* @}
*/
@@ -178,7 +178,7 @@ const uint8_t ShortRegData51[] = {0xC6, 0x06}; * @brief DSI IO write short/long command.
* @note : Can be surcharged by application code implementation of the function.
*/
-__weak void DSI_IO_WriteCmd(uint32_t NbrParams, uint8_t *pParams)
+__weak void DSI_IO_WriteCmd(gU32 NbrParams, gU8 *pParams)
{
/* NOTE : This function Should not be modified, when it is needed,
the DSI_IO_WriteCmd could be implemented in the user file
@@ -192,194 +192,194 @@ __weak void DSI_IO_WriteCmd(uint32_t NbrParams, uint8_t *pParams) * @param hdsivideo_handle : pointer on DSI video mode configuration structure
* @retval Status
*/
-uint8_t OTM8009A_Init(uint32_t ColorCoding, uint32_t orientation)
+gU8 OTM8009A_Init(gU32 ColorCoding, gU32 orientation)
{
/* Enable CMD2 to access vendor specific commands */
/* Enter in command 2 mode and set EXTC to enable address shift function (0x00) */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
- DSI_IO_WriteCmd( 3, (uint8_t *)lcdRegData1);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
+ DSI_IO_WriteCmd( 3, (gU8 *)lcdRegData1);
/* Enter ORISE Command 2 */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData2); /* Shift address to 0x80 */
- DSI_IO_WriteCmd( 2, (uint8_t *)lcdRegData2);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2); /* Shift address to 0x80 */
+ DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData2);
/////////////////////////////////////////////////////////////////////
/* SD_PCH_CTRL - 0xC480h - 129th parameter - Default 0x00 */
/* Set SD_PT */
/* -> Source output level during porch and non-display area to GND */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData2);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData3);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData3);
OTM8009A_IO_Delay(10);
/* Not documented */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData4);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData5);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData4);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData5);
OTM8009A_IO_Delay(10);
/////////////////////////////////////////////////////////////////////
/* PWR_CTRL4 - 0xC4B0h - 178th parameter - Default 0xA8 */
/* Set gvdd_en_test */
/* -> enable GVDD test mode !!! */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData6);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData7);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData6);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData7);
/* PWR_CTRL2 - 0xC590h - 146th parameter - Default 0x79 */
/* Set pump 4 vgh voltage */
/* -> from 15.0v down to 13.0v */
/* Set pump 5 vgh voltage */
/* -> from -12.0v downto -9.0v */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData8);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData9);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData8);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData9);
/* P_DRV_M - 0xC0B4h - 181th parameter - Default 0x00 */
/* -> Column inversion */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData10);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData11);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData10);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData11);
/* VCOMDC - 0xD900h - 1st parameter - Default 0x39h */
/* VCOM Voltage settings */
/* -> from -1.0000v downto -1.2625v */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData12);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData12);
/* Oscillator adjustment for Idle/Normal mode (LPDT only) set to 65Hz (default is 60Hz) */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData13);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData14);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData14);
/* Video mode internal */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData15);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData16);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData15);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData16);
/* PWR_CTRL2 - 0xC590h - 147h parameter - Default 0x00 */
/* Set pump 4&5 x6 */
/* -> ONLY VALID when PUMP4_EN_ASDM_HV = "0" */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData17);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData18);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData17);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData18);
/* PWR_CTRL2 - 0xC590h - 150th parameter - Default 0x33h */
/* Change pump4 clock ratio */
/* -> from 1 line to 1/2 line */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData19);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData9);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData19);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData9);
/* GVDD/NGVDD settings */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
- DSI_IO_WriteCmd( 2, (uint8_t *)lcdRegData5);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
+ DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData5);
/* PWR_CTRL2 - 0xC590h - 149th parameter - Default 0x33h */
/* Rewrite the default value ! */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData20);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData21);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData20);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData21);
/* Panel display timing Setting 3 */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData22);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData23);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData22);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData23);
/* Power control 1 */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData24);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData25);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData24);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData25);
/* Source driver precharge */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData13);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData26);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData26);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData15);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData27);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData15);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData27);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData28);
- DSI_IO_WriteCmd( 2, (uint8_t *)lcdRegData6);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData28);
+ DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData6);
/* GOAVST */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData2);
- DSI_IO_WriteCmd( 6, (uint8_t *)lcdRegData7);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
+ DSI_IO_WriteCmd( 6, (gU8 *)lcdRegData7);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData29);
- DSI_IO_WriteCmd( 14, (uint8_t *)lcdRegData8);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
+ DSI_IO_WriteCmd( 14, (gU8 *)lcdRegData8);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData30);
- DSI_IO_WriteCmd( 14, (uint8_t *)lcdRegData9);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
+ DSI_IO_WriteCmd( 14, (gU8 *)lcdRegData9);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData31);
- DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData10);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
+ DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData10);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData32);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData46);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData46);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData2);
- DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData11);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
+ DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData11);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData33);
- DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData12);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData33);
+ DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData12);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData29);
- DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData13);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
+ DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData13);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData30);
- DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData14);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
+ DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData14);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData31);
- DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData15);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
+ DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData15);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData32);
- DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData16);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
+ DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData16);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData34);
- DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData17);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData34);
+ DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData17);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData35);
- DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData18);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData35);
+ DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData18);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData2);
- DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData19);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
+ DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData19);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData33);
- DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData20);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData33);
+ DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData20);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData29);
- DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData21);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
+ DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData21);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData30);
- DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData22);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
+ DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData22);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData31);
- DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData23);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
+ DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData23);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData32);
- DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData24);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
+ DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData24);
/////////////////////////////////////////////////////////////////////////////
/* PWR_CTRL1 - 0xc580h - 130th parameter - default 0x00 */
/* Pump 1 min and max DM */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData13);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData47);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData48);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData49);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData47);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData48);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData49);
/////////////////////////////////////////////////////////////////////////////
/* CABC LEDPWM frequency adjusted to 19,5kHz */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData50);
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData51);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData50);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData51);
/* Exit CMD2 mode */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
- DSI_IO_WriteCmd( 3, (uint8_t *)lcdRegData25);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
+ DSI_IO_WriteCmd( 3, (gU8 *)lcdRegData25);
/*************************************************************************** */
/* Standard DCS Initialization TO KEEP CAN BE DONE IN HSDT */
/*************************************************************************** */
/* NOP - goes back to DCS std command ? */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
/* Gamma correction 2.2+ table (HSDT possible) */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
- DSI_IO_WriteCmd( 16, (uint8_t *)lcdRegData3);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
+ DSI_IO_WriteCmd( 16, (gU8 *)lcdRegData3);
/* Gamma correction 2.2- table (HSDT possible) */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
- DSI_IO_WriteCmd( 16, (uint8_t *)lcdRegData4);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
+ DSI_IO_WriteCmd( 16, (gU8 *)lcdRegData4);
/* Send Sleep Out command to display : no parameter */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData36);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData36);
/* Wait for sleep out exit */
OTM8009A_IO_Delay(120);
@@ -388,11 +388,11 @@ uint8_t OTM8009A_Init(uint32_t ColorCoding, uint32_t orientation) {
case OTM8009A_FORMAT_RBG565 :
/* Set Pixel color format to RGB565 */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData37);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData37);
break;
case OTM8009A_FORMAT_RGB888 :
/* Set Pixel color format to RGB888 */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData38);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData38);
break;
default :
break;
@@ -402,35 +402,35 @@ uint8_t OTM8009A_Init(uint32_t ColorCoding, uint32_t orientation) the orientation mode is portrait */
if(orientation == OTM8009A_ORIENTATION_LANDSCAPE)
{
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData39);
- DSI_IO_WriteCmd( 4, (uint8_t *)lcdRegData27);
- DSI_IO_WriteCmd( 4, (uint8_t *)lcdRegData28);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData39);
+ DSI_IO_WriteCmd( 4, (gU8 *)lcdRegData27);
+ DSI_IO_WriteCmd( 4, (gU8 *)lcdRegData28);
}
/** CABC : Content Adaptive Backlight Control section start >> */
/* Note : defaut is 0 (lowest Brightness), 0xFF is highest Brightness, try 0x7F : intermediate value */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData40);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData40);
/* defaut is 0, try 0x2C - Brightness Control Block, Display Dimming & BackLight on */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData41);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData41);
/* defaut is 0, try 0x02 - image Content based Adaptive Brightness [Still Picture] */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData42);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData42);
/* defaut is 0 (lowest Brightness), 0xFF is highest Brightness */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData43);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData43);
/** CABC : Content Adaptive Backlight Control section end << */
/* Send Command Display On */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData44);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData44);
/* NOP command */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
/* Send Command GRAM memory write (no parameters) : this initiates frame write via other DSI commands sent by */
/* DSI host from LTDC incoming pixels in video mode */
- DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData45);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData45);
return 0;
}
diff --git a/boards/base/STM32F469i-Discovery/otm8009a.h b/boards/base/STM32F469i-Discovery/otm8009a.h index 417d9b9b..52fc107c 100644 --- a/boards/base/STM32F469i-Discovery/otm8009a.h +++ b/boards/base/STM32F469i-Discovery/otm8009a.h @@ -73,37 +73,37 @@ * @brief LCD_OrientationTypeDef
* Possible values of Display Orientation
*/
-#define OTM8009A_ORIENTATION_PORTRAIT ((uint32_t)0x00) /* Portrait orientation choice of LCD screen */
-#define OTM8009A_ORIENTATION_LANDSCAPE ((uint32_t)0x01) /* Landscape orientation choice of LCD screen */
+#define OTM8009A_ORIENTATION_PORTRAIT ((gU32)0x00) /* Portrait orientation choice of LCD screen */
+#define OTM8009A_ORIENTATION_LANDSCAPE ((gU32)0x01) /* Landscape orientation choice of LCD screen */
/**
* @brief Possible values of
* pixel data format (ie color coding) transmitted on DSI Data lane in DSI packets
*/
-#define OTM8009A_FORMAT_RGB888 ((uint32_t)0x00) /* Pixel format chosen is RGB888 : 24 bpp */
-#define OTM8009A_FORMAT_RBG565 ((uint32_t)0x02) /* Pixel format chosen is RGB565 : 16 bpp */
+#define OTM8009A_FORMAT_RGB888 ((gU32)0x00) /* Pixel format chosen is RGB888 : 24 bpp */
+#define OTM8009A_FORMAT_RBG565 ((gU32)0x02) /* Pixel format chosen is RGB565 : 16 bpp */
/**
* @brief otm8009a_480x800 Size
*/
/* Width and Height in Portrait mode */
-#define OTM8009A_480X800_WIDTH ((uint16_t)480) /* LCD PIXEL WIDTH */
-#define OTM8009A_480X800_HEIGHT ((uint16_t)800) /* LCD PIXEL HEIGHT */
+#define OTM8009A_480X800_WIDTH ((gU16)480) /* LCD PIXEL WIDTH */
+#define OTM8009A_480X800_HEIGHT ((gU16)800) /* LCD PIXEL HEIGHT */
/* Width and Height in Landscape mode */
-#define OTM8009A_800X480_WIDTH ((uint16_t)800) /* LCD PIXEL WIDTH */
-#define OTM8009A_800X480_HEIGHT ((uint16_t)480) /* LCD PIXEL HEIGHT */
+#define OTM8009A_800X480_WIDTH ((gU16)800) /* LCD PIXEL WIDTH */
+#define OTM8009A_800X480_HEIGHT ((gU16)480) /* LCD PIXEL HEIGHT */
/**
* @brief OTM8009A_480X800 Timing parameters for Portrait orientation mode
*/
-#define OTM8009A_480X800_HSYNC ((uint16_t)2) /* Horizontal synchronization */
-#define OTM8009A_480X800_HBP ((uint16_t)34) /* Horizontal back porch */
-#define OTM8009A_480X800_HFP ((uint16_t)34) /* Horizontal front porch */
-#define OTM8009A_480X800_VSYNC ((uint16_t)1) /* Vertical synchronization */
-#define OTM8009A_480X800_VBP ((uint16_t)15) /* Vertical back porch */
-#define OTM8009A_480X800_VFP ((uint16_t)16) /* Vertical front porch */
+#define OTM8009A_480X800_HSYNC ((gU16)2) /* Horizontal synchronization */
+#define OTM8009A_480X800_HBP ((gU16)34) /* Horizontal back porch */
+#define OTM8009A_480X800_HFP ((gU16)34) /* Horizontal front porch */
+#define OTM8009A_480X800_VSYNC ((gU16)1) /* Vertical synchronization */
+#define OTM8009A_480X800_VBP ((gU16)15) /* Vertical back porch */
+#define OTM8009A_480X800_VFP ((gU16)16) /* Vertical front porch */
/**
* @brief OTM8009A_800X480 Timing parameters for Landscape orientation mode
@@ -198,9 +198,9 @@ /** @addtogroup OTM8009A_Exported_Functions
* @{
*/
-void DSI_IO_WriteCmd(uint32_t NbrParams, uint8_t *pParams);
-uint8_t OTM8009A_Init(uint32_t ColorCoding, uint32_t orientation);
-void OTM8009A_IO_Delay(uint32_t Delay);
+void DSI_IO_WriteCmd(gU32 NbrParams, gU8 *pParams);
+gU8 OTM8009A_Init(gU32 ColorCoding, gU32 orientation);
+void OTM8009A_IO_Delay(gU32 Delay);
/**
* @}
*/
diff --git a/boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.c b/boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.c index 8068db36..eeda4fdd 100644 --- a/boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.c +++ b/boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.c @@ -147,9 +147,9 @@ static FMC_SDRAM_CommandTypeDef Command; * @brief Initializes the SDRAM device.
* @retval SDRAM status
*/
-uint8_t BSP_SDRAM_Init(void)
+gU8 BSP_SDRAM_Init(void)
{
- static uint8_t sdramstatus = SDRAM_ERROR;
+ static gU8 sdramstatus = SDRAM_ERROR;
/* SDRAM device configuration */
sdramHandle.Instance = FMC_SDRAM_DEVICE;
@@ -196,9 +196,9 @@ uint8_t BSP_SDRAM_Init(void) * @brief DeInitializes the SDRAM device.
* @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
*/
-uint8_t BSP_SDRAM_DeInit(void)
+gU8 BSP_SDRAM_DeInit(void)
{
- static uint8_t sdramstatus = SDRAM_ERROR;
+ static gU8 sdramstatus = SDRAM_ERROR;
/* SDRAM device configuration */
sdramHandle.Instance = FMC_SDRAM_DEVICE;
@@ -219,9 +219,9 @@ uint8_t BSP_SDRAM_DeInit(void) * @brief Programs the SDRAM device.
* @param RefreshCount: SDRAM refresh counter value
*/
-void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
+void BSP_SDRAM_Initialization_sequence(gU32 RefreshCount)
{
- __IO uint32_t tmpmrd = 0;
+ __IO gU32 tmpmrd = 0;
/* Step 1: Configure a clock configuration enable command */
Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
@@ -255,7 +255,7 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
/* Step 5: Program the external memory mode register */
- tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
+ tmpmrd = (gU32)SDRAM_MODEREG_BURST_LENGTH_1 |\
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
SDRAM_MODEREG_CAS_LATENCY_3 |\
SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
@@ -281,9 +281,9 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) * @param uwDataSize: Size of read data from the memory
* @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
*/
-uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
+gU8 BSP_SDRAM_ReadData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
{
- if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
+ if(HAL_SDRAM_Read_32b(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SDRAM_ERROR;
}
@@ -300,9 +300,9 @@ uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uw * @param uwDataSize: Size of read data from the memory
* @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
*/
-uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
+gU8 BSP_SDRAM_ReadData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
{
- if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
+ if(HAL_SDRAM_Read_DMA(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SDRAM_ERROR;
}
@@ -319,9 +319,9 @@ uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_ * @param uwDataSize: Size of written data from the memory
* @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
*/
-uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
+gU8 BSP_SDRAM_WriteData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
{
- if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
+ if(HAL_SDRAM_Write_32b(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SDRAM_ERROR;
}
@@ -338,9 +338,9 @@ uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t u * @param uwDataSize: Size of written data from the memory
* @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
*/
-uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
+gU8 BSP_SDRAM_WriteData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
{
- if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
+ if(HAL_SDRAM_Write_DMA(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SDRAM_ERROR;
}
@@ -355,7 +355,7 @@ uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32 * @param SdramCmd: Pointer to SDRAM command structure
* @retval HAL status : SDRAM_OK or SDRAM_ERROR.
*/
-uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
+gU8 BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
{
if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
{
diff --git a/boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.h b/boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.h index 6068644f..de731a2d 100644 --- a/boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.h +++ b/boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.h @@ -66,8 +66,8 @@ /**
* @brief SDRAM status structure definition
*/
-#define SDRAM_OK ((uint8_t)0x00)
-#define SDRAM_ERROR ((uint8_t)0x01)
+#define SDRAM_OK ((gU8)0x00)
+#define SDRAM_ERROR ((gU8)0x01)
/**
* @}
@@ -76,17 +76,17 @@ /** @defgroup STM32469I-Discovery_SDRAM_Exported_Constants STM32469I Discovery SDRAM Exported Constants
* @{
*/
-#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000)
+#define SDRAM_DEVICE_ADDR ((gU32)0xC0000000)
/* SDRAM device size in Bytes */
- #define SDRAM_DEVICE_SIZE ((uint32_t)0x1000000)
+ #define SDRAM_DEVICE_SIZE ((gU32)0x1000000)
#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_32
#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
/* SDRAM refresh counter (90 MHz SD clock) */
-#define REFRESH_COUNT ((uint32_t)0x0569)
-#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
+#define REFRESH_COUNT ((gU32)0x0569)
+#define SDRAM_TIMEOUT ((gU32)0xFFFF)
/* DMA definitions for SDRAM DMA transfer */
#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
@@ -100,17 +100,17 @@ /**
* @brief FMC SDRAM Mode definition register defines
*/
-#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
-#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
-#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
-#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
-#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
-#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
-#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
-#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
-#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
-#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
-#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
+#define SDRAM_MODEREG_BURST_LENGTH_1 ((gU16)0x0000)
+#define SDRAM_MODEREG_BURST_LENGTH_2 ((gU16)0x0001)
+#define SDRAM_MODEREG_BURST_LENGTH_4 ((gU16)0x0002)
+#define SDRAM_MODEREG_BURST_LENGTH_8 ((gU16)0x0004)
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((gU16)0x0000)
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((gU16)0x0008)
+#define SDRAM_MODEREG_CAS_LATENCY_2 ((gU16)0x0020)
+#define SDRAM_MODEREG_CAS_LATENCY_3 ((gU16)0x0030)
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((gU16)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((gU16)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((gU16)0x0200)
/**
* @}
*/
@@ -125,14 +125,14 @@ /** @addtogroup STM32469I_Discovery_SDRAM_Exported_Functions
* @{
*/
-uint8_t BSP_SDRAM_Init(void);
-uint8_t BSP_SDRAM_DeInit(void);
-void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
-uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
-uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
-uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
-uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
-uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
+gU8 BSP_SDRAM_Init(void);
+gU8 BSP_SDRAM_DeInit(void);
+void BSP_SDRAM_Initialization_sequence(gU32 RefreshCount);
+gU8 BSP_SDRAM_ReadData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
+gU8 BSP_SDRAM_ReadData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
+gU8 BSP_SDRAM_WriteData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
+gU8 BSP_SDRAM_WriteData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
+gU8 BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
void BSP_SDRAM_DMA_IRQHandler(void);
/* These function can be modified in case the current settings (e.g. DMA stream)
diff --git a/boards/base/STM32F469i-Discovery/stm32f469i_raw32_system.c b/boards/base/STM32F469i-Discovery/stm32f469i_raw32_system.c index bfeaf3b4..d6f02d94 100644 --- a/boards/base/STM32F469i-Discovery/stm32f469i_raw32_system.c +++ b/boards/base/STM32F469i-Discovery/stm32f469i_raw32_system.c @@ -68,14 +68,14 @@ #if !defined (HSE_VALUE)
#if defined(USE_STM32469I_DISCO_REVA)
- #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+ #define HSE_VALUE ((gU32)25000000) /*!< Default value of the External oscillator in Hz */
#else
- #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
+ #define HSE_VALUE ((gU32)8000000) /*!< Default value of the External oscillator in Hz */
#endif /* USE_STM32469I_DISCO_REVA */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+ #define HSI_VALUE ((gU32)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
@@ -129,9 +129,9 @@ is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
-uint32_t SystemCoreClock = 16000000;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+gU32 SystemCoreClock = 16000000;
+const gU8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const gU8 APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@@ -167,19 +167,19 @@ void SystemInit(void) #endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
+ RCC->CR |= (gU32)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
+ RCC->CR &= (gU32)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
+ RCC->CR &= (gU32)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
@@ -234,7 +234,7 @@ void SystemInit(void) */
void SystemCoreClockUpdate(void)
{
- uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+ gU32 tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
@@ -291,8 +291,8 @@ void SystemCoreClockUpdate(void) */
void SystemInit_ExtMemCtl(void)
{
- register uint32_t tmpreg = 0, timeout = 0xFFFF;
- register __IO uint32_t index;
+ register gU32 tmpreg = 0, timeout = 0xFFFF;
+ register __IO gU32 index;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, and GPIOI interface
clock */
|