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authorinmarket <andrewh@inmarket.com.au>2013-10-19 17:58:57 +1000
committerinmarket <andrewh@inmarket.com.au>2013-10-19 17:58:57 +1000
commit929dbabf689ff2ad688dc3a3748faeb3bd351698 (patch)
treefafc4126da1ff3fc3a81801554dc6b10353fed7c /drivers/gdisp/S6D1121/board_S6D1121_olimex_e407.h
parent9a8b5b416358bbc95ffdd5b287190f0369908c1a (diff)
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Convert S6D1121 driver to new format
Diffstat (limited to 'drivers/gdisp/S6D1121/board_S6D1121_olimex_e407.h')
-rw-r--r--drivers/gdisp/S6D1121/board_S6D1121_olimex_e407.h91
1 files changed, 91 insertions, 0 deletions
diff --git a/drivers/gdisp/S6D1121/board_S6D1121_olimex_e407.h b/drivers/gdisp/S6D1121/board_S6D1121_olimex_e407.h
new file mode 100644
index 00000000..ec367183
--- /dev/null
+++ b/drivers/gdisp/S6D1121/board_S6D1121_olimex_e407.h
@@ -0,0 +1,91 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ * http://ugfx.org/license.html
+ */
+
+/**
+ * @file drivers/gdisp/S6D1121/board_S6D1121_olimex_e407.h
+ * @brief GDISP Graphic Driver subsystem board interface for the S6D1121 display
+ */
+
+#ifndef _GDISP_LLD_BOARD_H
+#define _GDISP_LLD_BOARD_H
+
+// For a multiple display configuration we would put all this in a structure and then
+// set g->priv to that structure.
+#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
+#define GDISP_RAM (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
+
+static inline void init_board(GDisplay *g) {
+
+ // As we are not using multiple displays we set g->priv to NULL as we don't use it.
+ g->priv = 0;
+
+ switch(g->controllerdisplay) {
+ case 0: // Set up for Display 0
+ /* STM32F4 FSMC init */
+ rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
+
+ /* set pins to FSMC mode */
+ IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) |
+ (1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0};
+
+ IOBus busE = {GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
+ (1 << 13) | (1 << 14) | (1 << 15), 0};
+
+ palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
+ palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
+
+ /* FSMC timing */
+ FSMC_Bank1->BTCR[0+1] = (6) | (10 << 8) | (10 << 16);
+
+ /* Bank1 NOR/SRAM control register configuration */
+ FSMC_Bank1->BTCR[0] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
+ break;
+ }
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+ (void) g;
+ (void) state;
+}
+
+static inline void set_backlight(GDisplay *g, uint8_t percent) {
+ (void) g;
+ (void) percent;
+}
+
+static inline void acquire_bus(GDisplay *g) {
+ (void) g;
+}
+
+static inline void release_bus(GDisplay *g) {
+ (void) g;
+}
+
+static inline void write_index(GDisplay *g, uint16_t index) {
+ (void) g;
+ GDISP_REG = index;
+}
+
+static inline void write_data(GDisplay *g, uint16_t data) {
+ (void) g;
+ GDISP_RAM = data;
+}
+
+static inline void setreadmode(GDisplay *g) {
+ (void) g;
+}
+
+static inline void setwritemode(GDisplay *g) {
+ (void) g;
+}
+
+static inline uint16_t read_data(GDisplay *g) {
+ (void) g;
+ return GDISP_RAM;
+}
+
+#endif /* _GDISP_LLD_BOARD_H */