merging GDISPStreaming

69 files changed, 11845 insertions, 0 deletions

diff --git a/boards/addons/gdisp/ED060SC4_example_schematics.png b/boards/addons/gdisp/ED060SC4_example_schematics.png
new file mode 100644
index 00000000..0d9d095f
--- /dev/null
+++ b/boards/addons/gdisp/ED060SC4_example_schematics.png
diff --git a/boards/addons/gdisp/board_ED060SC4_example.h b/boards/addons/gdisp/board_ED060SC4_example.h
new file mode 100644
index 00000000..cb5a92b8
--- /dev/null
+++ b/boards/addons/gdisp/board_ED060SC4_example.h
@@ -0,0 +1,143 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/* Board interface definitions for ED060SC4 PrimeView E-ink panel.
+ * 
+ * This file corresponds to the connections shown in example_schematics.png,
+ * and is designed to interface with ChibiOS/RT.
+ * 
+ * Please note that this file has never been tested in exactly this pin
+ * configuration, because the actual boards I have are slightly different.
+ */
+
+#ifndef _GDISP_LLD_BOARD_H
+#define _GDISP_LLD_BOARD_H
+
+#include <hal.h>
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOB_EINK_VDD      0
+#define GPIOB_EINK_GMODE    1
+#define GPIOB_EINK_SPV      2
+#define GPIOB_EINK_CKV      3
+#define GPIOB_EINK_CL       4
+#define GPIOB_EINK_LE       5
+#define GPIOB_EINK_OE       6
+#define GPIOB_EINK_SPH      7
+#define GPIOB_EINK_D0       8
+#define GPIOB_EINK_D1       9
+#define GPIOB_EINK_D2       10
+#define GPIOB_EINK_D3       11
+#define GPIOB_EINK_D4       12
+#define GPIOB_EINK_D5       13
+#define GPIOB_EINK_D6       14
+#define GPIOB_EINK_D7       15
+
+#define GPIOC_SMPS_CTRL     13
+#define GPIOC_VPOS_CTRL     14
+#define GPIOC_VNEG_CTRL     15
+
+static inline void init_board(GDisplay *g) {
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		/* Main SMPS power control, active low
+		 * (open collector so that MOSFET gate can be pulled up to Vbat) */
+		palWritePad(GPIOC, GPIOC_SMPS_CTRL, true);
+		palSetPadMode(GPIOC, GPIOC_SMPS_CTRL, PAL_MODE_OUTPUT_OPENDRAIN);
+
+		/* Power control for the positive & negative side */
+		palWritePad(GPIOC, GPIOC_VPOS_CTRL, false);
+		palSetPadMode(GPIOC, GPIOC_VPOS_CTRL, PAL_MODE_OUTPUT_PUSHPULL);
+		palWritePad(GPIOC, GPIOC_VNEG_CTRL, false);
+		palSetPadMode(GPIOC, GPIOC_VNEG_CTRL, PAL_MODE_OUTPUT_PUSHPULL);
+
+		/* Main data bus */
+		palWritePort(GPIOB, 0);
+		palSetGroupMode(GPIOB, 0xFFFF, 0, PAL_MODE_OUTPUT_PUSHPULL);
+		break;
+	}
+}
+
+/* Delay for display waveforms. Should be an accurate microsecond delay. */
+static void eink_delay(int us) {
+	halPolledDelay(US2RTT(us));
+}
+
+/* Turn the E-ink panel Vdd supply (+3.3V) on or off. */
+static inline void setpower_vdd(GDisplay *g, bool_t on) {
+	(void) g;
+	palWritePad(GPIOB, GPIOB_SMPS_CTRL, !on);
+	palWritePad(GPIOA, GPIOA_EINK_VDD, on);
+}
+
+/* Turn the E-ink panel negative supplies (-15V, -20V) on or off. */
+static inline void setpower_vneg(GDisplay *g, bool_t on) {
+	(void) g;
+	palWritePad(GPIOA, GPIOA_VNEG_CTRL, on);
+}
+
+/* Turn the E-ink panel positive supplies (-15V, -20V) on or off. */
+static inline void setpower_vpos(GDisplay *g, bool_t on) {
+	(void) g;
+	palWritePad(GPIOA, GPIOA_VPOS_CTRL, on);
+}
+
+/* Set the state of the LE (source driver Latch Enable) pin. */
+static inline void setpin_le(GDisplay *g, bool_t on) {
+	(void) g;
+	palWritePad(GPIOB, GPIOB_EINK_LE, on);
+}
+
+/* Set the state of the OE (source driver Output Enable) pin. */
+static inline void setpin_oe(GDisplay *g, bool_t on) {
+	(void) g;
+	palWritePad(GPIOB, GPIOB_EINK_OE, on);
+}
+
+/* Set the state of the CL (source driver Clock) pin. */
+static inline void setpin_cl(GDisplay *g, bool_t on) {
+	(void) g;
+	palWritePad(GPIOB, GPIOB_EINK_CL, on);
+}
+
+/* Set the state of the SPH (source driver Start Pulse Horizontal) pin. */
+static inline void setpin_sph(GDisplay *g, bool_t on) {
+	(void) g;
+	palWritePad(GPIOB, GPIOB_EINK_SPH, on);
+}
+
+/* Set the state of the D0-D7 (source driver Data) pins. */
+static inline void setpins_data(GDisplay *g, uint8_t value) {
+	(void) g;
+	palWriteGroup(GPIOB, 0xFF, GPIOB_EINK_D0, value);
+}
+
+/* Set the state of the CKV (gate driver Clock Vertical) pin. */
+static inline void setpin_ckv(GDisplay *g, bool_t on) {
+	(void) g;
+	palWritePad(GPIOB, GPIOB_EINK_CKV, on);
+}
+
+/* Set the state of the GMODE (gate driver Gate Mode) pin. */
+static inline void setpin_gmode(GDisplay *g, bool_t on) {
+	(void) g;
+	palWritePad(GPIOC, GPIOC_EINK_GMODE, on);
+}
+
+/* Set the state of the SPV (gate driver Start Pulse Vertical) pin. */
+static inline void setpin_spv(GDisplay *g, bool_t on) {
+	(void) g;
+	palWritePad(GPIOB, GPIOB_EINK_SPV, on);
+}
+
+#endif
diff --git a/boards/addons/gdisp/board_HX8347D_stm32f4discovery.h b/boards/addons/gdisp/board_HX8347D_stm32f4discovery.h
new file mode 100644
index 00000000..df287477
--- /dev/null
+++ b/boards/addons/gdisp/board_HX8347D_stm32f4discovery.h
@@ -0,0 +1,160 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/gdisp/HX8347D/board_HX8347D_stm32f4discovery.h
+ * @brief   GDISP Graphic Driver subsystem board SPI interface for the HX8347D display.
+ */
+
+#ifndef _GDISP_LLD_BOARD_H
+#define _GDISP_LLD_BOARD_H
+
+// For a multiple display configuration we would put all this in a structure and then
+//	set g->board to that structure.
+
+/* Pin assignments */
+#define SET_RST		palSetPad(GPIOB, 8)
+#define CLR_RST		palClearPad(GPIOB, 8)
+#define SET_DATA	palSetPad(GPIOB, 9)
+#define CLR_DATA	palClearPad(GPIOB, 9)
+#define SET_CS		palSetPad(GPIOA, 4)
+#define CLR_CS		palClearPad(GPIOA, 4)
+
+/* PWM configuration structure. We use timer 4 channel 2 (orange LED on board). */
+static const PWMConfig pwmcfg = {
+	1000000,		/* 1 MHz PWM clock frequency. */
+	100,			/* PWM period is 100 cycles. */
+	NULL,
+	{
+		{PWM_OUTPUT_ACTIVE_HIGH, NULL},
+		{PWM_OUTPUT_ACTIVE_HIGH, NULL},
+		{PWM_OUTPUT_ACTIVE_HIGH, NULL},
+		{PWM_OUTPUT_ACTIVE_HIGH, NULL}
+	},
+	0
+};
+
+/*
+ * SPI1 configuration structure.
+ * Speed 42MHz, CPHA=0, CPOL=0, 8bits frames, MSb transmitted first.
+ * The slave select line is the pin 4 on the port GPIOA.
+ */
+static const SPIConfig spi1cfg_8bit = {
+	NULL,
+	/* HW dependent part.*/
+	GPIOA,
+	4,
+	0 //SPI_CR1_BR_0
+};
+
+/*
+ * SPI1 configuration structure.
+ * Speed 42MHz, CPHA=0, CPOL=0, 16bits frames, MSb transmitted first.
+ * The slave select line is the pin 4 on the port GPIOA.
+ */
+static const SPIConfig spi1cfg_16bit = {
+	NULL,
+	/* HW dependent part.*/
+	GPIOA,
+	4,
+	SPI_CR1_DFF //SPI_CR1_BR_0
+};
+
+static inline void init_board(GDisplay *g) {
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		/* Display backlight control */
+		/* TIM4 is an alternate function 2 (AF2) */
+		pwmStart(&PWMD4, &pwmcfg);
+		palSetPadMode(GPIOD, 13, PAL_MODE_ALTERNATE(2));
+		pwmEnableChannel(&PWMD4, 1, 100);
+
+		palSetPadMode(GPIOB, 8, PAL_MODE_OUTPUT_PUSHPULL|PAL_STM32_OSPEED_HIGHEST);			/* RST    */
+		palSetPadMode(GPIOB, 9, PAL_MODE_OUTPUT_PUSHPULL|PAL_STM32_OSPEED_HIGHEST);			/* RS     */
+		/*
+		 * Initializes the SPI driver 1. The SPI1 signals are routed as follow:
+		 * PB12 - NSS.
+		 * PB13 - SCK.
+		 * PB14 - MISO.
+		 * PB15 - MOSI.
+		 */
+		SET_CS; SET_DATA;
+		spiStart(&SPID1, &spi1cfg_8bit);
+		palSetPadMode(GPIOA, 4, PAL_MODE_OUTPUT_PUSHPULL|PAL_STM32_OSPEED_HIGHEST);			/* NSS.     */
+		palSetPadMode(GPIOA, 5, PAL_MODE_ALTERNATE(5)|PAL_STM32_OSPEED_HIGHEST);			/* SCK.     */
+		palSetPadMode(GPIOA, 6, PAL_MODE_ALTERNATE(5));										/* MISO.    */
+		palSetPadMode(GPIOA, 7, PAL_MODE_ALTERNATE(5)|PAL_STM32_OSPEED_HIGHEST);			/* MOSI.    */
+		break;
+	}
+}
+
+static inline void post_init_board(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	if (state) {
+		CLR_RST;
+	} else {
+		SET_RST;
+	}
+}
+
+static inline void set_backlight(GDisplay *g, uint8_t percent) {
+	(void) g;
+	pwmEnableChannel(&PWMD4, 1, percent);
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+	spiAcquireBus(&SPID1);
+    while(((SPI1->SR & SPI_SR_TXE) == 0) || ((SPI1->SR & SPI_SR_BSY) != 0));		// Safety
+	CLR_CS;
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+	SET_CS;
+	spiReleaseBus(&SPID1);
+}
+
+static inline void busmode16(GDisplay *g) {
+	(void) g;
+	spiStart(&SPID1, &spi1cfg_16bit);
+}
+
+static inline void busmode8(GDisplay *g) {
+	(void) g;
+	spiStart(&SPID1, &spi1cfg_8bit);
+}
+
+static inline void write_index(GDisplay *g, uint8_t index) {
+	(void) g;
+    CLR_DATA;
+    SPI1->DR = index;
+    while(((SPI1->SR & SPI_SR_TXE) == 0) || ((SPI1->SR & SPI_SR_BSY) != 0));
+    SET_DATA;
+}
+
+static inline void write_data(GDisplay *g, uint8_t data) {
+	(void) g;
+    SPI1->DR = data;
+    while(((SPI1->SR & SPI_SR_TXE) == 0) || ((SPI1->SR & SPI_SR_BSY) != 0));
+}
+
+static inline void write_ram16(GDisplay *g, uint16_t data) {
+	(void) g;
+    SPI1->DR      = data;
+    while((SPI1->SR & SPI_SR_TXE) == 0);
+}
+
+#endif /* _GDISP_LLD_BOARD_H */
diff --git a/boards/addons/gdisp/board_ILI9320_olimex_pic32mx_lcd.h b/boards/addons/gdisp/board_ILI9320_olimex_pic32mx_lcd.h
new file mode 100644
index 00000000..5315127b
--- /dev/null
+++ b/boards/addons/gdisp/board_ILI9320_olimex_pic32mx_lcd.h
@@ -0,0 +1,126 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/gdisp/ILI9320/board_ILI9320_olimex_pic32mx_lcd.h
+ * @brief   GDISP Graphic Driver subsystem board interface for the ILI9325 display.
+ */
+
+#ifndef GDISP_LLD_BOARD_H
+#define GDISP_LLD_BOARD_H
+
+#ifndef noinline
+#define noinline __attribute__((noinline))
+#endif
+
+static void init_board(GDisplay *g) {
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		// RST
+		palSetPadMode(IOPORTA, 7, PAL_MODE_OUTPUT);
+		palClearPad(IOPORTA, 7);
+
+		// RS
+		palSetPadMode(IOPORTA, 10, PAL_MODE_OUTPUT);
+		palSetPad(IOPORTA, 10);
+
+		// CS
+		palSetPadMode(IOPORTA, 9, PAL_MODE_OUTPUT);
+		palClearPad(IOPORTA, 9);
+
+		// Backlight
+		palSetPadMode(IOPORTD, 3, PAL_MODE_OUTPUT);
+		palSetPad(IOPORTD, 3);
+
+		// PMP setup
+		PMMODE = 0;
+		PMAEN = 0;
+		PMCON = 0;
+		PMMODEbits.MODE = 2;
+		PMMODEbits.WAITB = 0;
+		PMMODEbits.WAITM = 1;
+		PMMODEbits.WAITE = 0;
+		PMCONbits.CSF = 0;
+		PMCONbits.PTRDEN = 1;
+		PMCONbits.PTWREN = 1;
+		PMMODEbits.MODE16 = 1;
+		PMCONbits.PMPEN = 1;
+
+		palClearPad(IOPORTA, 9);
+		break;
+	}
+}
+
+#define PmpWaitBusy()   do {} while (PMMODEbits.BUSY)
+
+static inline void post_init_board(GDisplay *g) {
+	(void) g;
+}
+
+static noinline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	if (state)
+		palClearPad(IOPORTA, 7);
+	else
+		palSetPad(IOPORTA, 7);
+}
+
+static void set_backlight(GDisplay *g, uint8_t percent) {
+	(void) g;
+	if (percentage)
+		palClearPad(IOPORTD, 3);
+	else
+		palSetPad(IOPORTD, 3);
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+}
+
+static noinline void write_index(GDisplay *g, uint16_t index) {
+	volatile uint16_t dummy;
+	(void) g;
+
+	PmpWaitBusy();
+	palClearPad(IOPORTA, 10);
+	PMDIN = index;
+	PmpWaitBusy();
+	palSetPad(IOPORTA, 10);
+
+	dummy = PMDIN;
+	(void)dummy;
+}
+
+static noinline void write_data(GDisplay *g, uint16_t data) {
+	(void) g;
+	PMDIN = data;
+	PmpWaitBusy();
+}
+
+static inline void setreadmode(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setwritemode(GDisplay *g) {
+	(void) g;
+}
+
+static noinline uint16_t read_data(GDisplay *g) {
+	(void) g;
+	PmpWaitBusy();
+	return PMDIN;
+}
+
+#endif /* GDISP_LLD_BOARD_H */
diff --git a/boards/addons/gdisp/board_ILI9320_olimex_stm32_lcd.h b/boards/addons/gdisp/board_ILI9320_olimex_stm32_lcd.h
new file mode 100644
index 00000000..bca5caf8
--- /dev/null
+++ b/boards/addons/gdisp/board_ILI9320_olimex_stm32_lcd.h
@@ -0,0 +1,100 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/gdisp/ILI9320/board_ILI9320_olimex_stm32_lcd.h
+ * @brief   GDISP Graphic Driver subsystem board interface for the ILI9320 display.
+ */
+
+#ifndef GDISP_LLD_BOARD_H
+#define GDISP_LLD_BOARD_H
+
+// For a multiple display configuration we would put all this in a structure and then
+//	set g->board to that structure.
+#define GDISP_REG              (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
+#define GDISP_RAM              (*((volatile uint16_t *) 0x60100000)) /* RS = 1 */
+
+static inline void init_board(GDisplay *g) {
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		/* FSMC setup for F1 */
+		rccEnableAHB(RCC_AHBENR_FSMCEN, 0);
+
+		/* set pin modes */
+		IOBus busD = {GPIOD, PAL_WHOLE_PORT, 0};
+		IOBus busE = {GPIOE, PAL_WHOLE_PORT, 0};
+		palSetBusMode(&busD, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
+		palSetBusMode(&busE, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
+		palSetPadMode(GPIOE, GPIOE_TFT_RST, PAL_MODE_OUTPUT_PUSHPULL);
+		palSetPadMode(GPIOD, GPIOD_TFT_LIGHT, PAL_MODE_OUTPUT_PUSHPULL);
+
+		/* FSMC timing */
+		FSMC_Bank1->BTCR[0+1] = (6) | (10 << 8) | (10 << 16);
+
+		/* Bank1 NOR/SRAM control register configuration
+		 * This is actually not needed as already set by default after reset */
+		FSMC_Bank1->BTCR[0] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
+		break;
+	}
+}
+
+static inline void post_init_board(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	if(state)
+		palClearPad(GPIOE, GPIOE_TFT_RST);
+	else
+		palSetPad(GPIOE, GPIOE_TFT_RST);
+}
+
+static inline void set_backlight(GDisplay *g, uint8_t percent) {
+	(void) g;
+	if(percent)
+		palClearPad(GPIOD, GPIOD_TFT_LIGHT);
+	else
+		palSetPad(GPIOD, GPIOD_TFT_LIGHT);
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void write_index(GDisplay *g, uint16_t index) {
+	(void) g;
+	GDISP_REG = index;
+}
+
+static inline void write_data(GDisplay *g, uint16_t data) {
+	(void) g;
+	GDISP_RAM = data;
+}
+
+static inline void setreadmode(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setwritemode(GDisplay *g) {
+	(void) g;
+}
+
+static inline uint16_t read_data(GDisplay *g) {
+	(void) g;
+	return GDISP_RAM;
+}
+
+#endif /* GDISP_LLD_BOARD_H */
diff --git a/boards/addons/gdisp/board_ILI9325_hy_stm32_100p.h b/boards/addons/gdisp/board_ILI9325_hy_stm32_100p.h
new file mode 100644
index 00000000..60508c1a
--- /dev/null
+++ b/boards/addons/gdisp/board_ILI9325_hy_stm32_100p.h
@@ -0,0 +1,112 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/*
+	driver quickly hacked together from a chinese sourcecode that came
+	with the board and existing ili9320 code by Chris van Dongen (sjaak)
+	(sjaak2002 at msn.com)
+	
+	Also added rotation for 180 and 270 degrees and minor tweaks to
+	setcursor
+	
+	Added code comes without warranty and free bugs. Feel free to use 
+	or misuse the added code :D
+*/
+
+
+/**
+ * @file    drivers/gdisp/ILI9325/board_ILI9325_hy_stm32_100p.h
+ * @brief   GDISP Graphic Driver subsystem board interface for the ILI9325 display.
+ */
+
+#ifndef GDISP_LLD_BOARD_H
+#define GDISP_LLD_BOARD_H
+
+// For a multiple display configuration we would put all this in a structure and then
+//	set g->board to that structure.
+#define GDISP_REG              (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
+#define GDISP_RAM              (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
+
+static inline void init_board(GDisplay *g) {
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		/* FSMC setup for F1 */
+		rccEnableAHB(RCC_AHBENR_FSMCEN, 0);
+
+		/* set pin modes */
+	/*	IOBus busD = {GPIOD, PAL_WHOLE_PORT, 0};
+		IOBus busE = {GPIOE, PAL_WHOLE_PORT, 0};
+		palSetBusMode(&busD, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
+		palSetBusMode(&busE, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
+		palSetPadMode(GPIOE, GPIOE_TFT_RST, PAL_MODE_OUTPUT_PUSHPULL);
+		palSetPadMode(GPIOD, GPIOD_TFT_LIGHT, PAL_MODE_OUTPUT_PUSHPULL); */
+
+		const unsigned char FSMC_Bank = 0;
+
+		/* FSMC timing */
+		FSMC_Bank1->BTCR[FSMC_Bank+1] = (6) | (10 << 8) | (10 << 16);
+
+		/* Bank1 NOR/SRAM control register configuration
+		 * This is actually not needed as already set by default after reset */
+		FSMC_Bank1->BTCR[FSMC_Bank] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
+		break;
+	}
+}
+
+static inline void post_init_board(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	if(state)
+		palClearPad(GPIOE, GPIOE_TFT_RST);
+	else
+		palSetPad(GPIOE, GPIOE_TFT_RST);
+}
+
+static inline void set_backlight(GDisplay *g, uint8_t percent) {
+	(void) g;
+	(void)percent;
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void write_index(GDisplay *g, uint16_t index) {
+	(void) g;
+	GDISP_REG = index;
+}
+
+static inline void write_data(GDisplay *g, uint16_t data) {
+	(void) g;
+	GDISP_RAM = data;
+}
+
+static inline void setreadmode(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setwritemode(GDisplay *g) {
+	(void) g;
+}
+
+static inline uint16_t read_data(GDisplay *g) {
+	(void) g;
+	return GDISP_RAM;
+}
+
+#endif /* GDISP_LLD_BOARD_H */
diff --git a/boards/addons/gdisp/board_ILI9481_firebullstm32f103.h b/boards/addons/gdisp/board_ILI9481_firebullstm32f103.h
new file mode 100644
index 00000000..17bc554d
--- /dev/null
+++ b/boards/addons/gdisp/board_ILI9481_firebullstm32f103.h
@@ -0,0 +1,107 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/gdisp/ILI9481/board_ILI9481_firebullstm32f103.h
+ * @brief   GDISP Graphics Driver subsystem low level driver source for
+ * 			the ILI9481 and compatible HVGA display
+ */
+
+#ifndef _GDISP_LLD_BOARD_H
+#define _GDISP_LLD_BOARD_H
+
+// For a multiple display configuration we would put all this in a structure and then
+//	set g->board to that structure.
+#define SET_CS		palSetPad(GPIOD, 12);
+#define CLR_CS		palClearPad(GPIOD, 12);
+#define SET_RS		palSetPad(GPIOD, 13);
+#define CLR_RS		palClearPad(GPIOD, 13);
+#define SET_WR		palSetPad(GPIOD, 14);
+#define CLR_WR		palClearPad(GPIOD, 14);
+#define SET_RD		palSetPad(GPIOD, 15);
+#define CLR_RD		palClearPad(GPIOD, 15);
+
+static inline void init_board(GDisplay *g) {
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
+		palSetPadMode(GPIOD, 12, PAL_MODE_OUTPUT_PUSHPULL);
+		palSetPadMode(GPIOD, 13, PAL_MODE_OUTPUT_PUSHPULL);
+		palSetPadMode(GPIOD, 14, PAL_MODE_OUTPUT_PUSHPULL);
+		palSetPadMode(GPIOD, 15, PAL_MODE_OUTPUT_PUSHPULL);
+
+		// Configure the pins to a well know state
+		SET_RS;
+		SET_RD;
+		SET_WR;
+		CLR_CS;
+		break;
+	}
+}
+
+static inline void post_init_board(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	(void) state;
+}
+
+static inline void set_backlight(GDisplay *g, uint8_t percent) {
+	(void) g;
+	(void) percent;
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void write_index(GDisplay *g, uint16_t index) {
+	(void) g;
+	palWritePort(GPIOE, index);
+	CLR_RS; CLR_WR; SET_WR; SET_RS;
+}
+
+static inline void write_data(GDisplay *g, uint16_t data) {
+	(void) g;
+	palWritePort(GPIOE, data);
+	CLR_WR; SET_WR;
+}
+
+static inline void setreadmode(GDisplay *g) {
+	(void) g;
+	// change pin mode to digital input
+	palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_INPUT);
+}
+
+static inline void setwritemode(GDisplay *g) {
+	(void) g;
+	// change pin mode back to digital output
+	palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
+}
+
+static inline uint16_t read_data(GDisplay *g) {
+	uint16_t	value;
+	(void) g;
+	
+	CLR_RD;
+	value = palReadPort(GPIOE);
+	SET_RD;
+	
+	return value;
+}
+
+#endif /* _GDISP_LLD_BOARD_H */
diff --git a/boards/addons/gdisp/board_RA8875_marlin.h b/boards/addons/gdisp/board_RA8875_marlin.h
new file mode 100644
index 00000000..b1d55a92
--- /dev/null
+++ b/boards/addons/gdisp/board_RA8875_marlin.h
@@ -0,0 +1,113 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/gdisp/RA8875/board_RA8875_marlin.h
+ * @brief   GDISP Graphic Driver subsystem board interface for the RA8875 display.
+ */
+
+#ifndef _BOARD_RA8875_H
+#define _BOARD_RA8875_H
+
+// For a multiple display configuration we would put all this in a structure and then
+// set g->board to that structure.
+#define GDISP_RAM              (*((volatile uint16_t *) 0x68000000)) /* RS = 0 */
+#define GDISP_REG              (*((volatile uint16_t *) 0x68020000)) /* RS = 1 */
+#define FSMC_BANK				4
+
+
+static inline void init_board(GDisplay *g) {
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+		// setup for display 0
+		case 0: {		
+
+			// enable the FSMC peripheral
+			rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
+
+			// setup the pin modes for FSMC
+			IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 8) |
+									(1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0};
+
+			IOBus busE = {GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
+								(1 << 13) | (1 << 14) | (1 << 15), 0};
+
+			IOBus busG = {GPIOG, (1 << 10), 0};
+
+			palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
+			palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
+			palSetBusMode(&busG, PAL_MODE_ALTERNATE(12));
+
+			// FSMC timing
+			FSMC_Bank1->BTCR[FSMC_BANK+1] = (FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_3) \
+					| (FSMC_BTR1_DATAST_1 | FSMC_BTR1_DATAST_3) \
+					| (FSMC_BTR1_BUSTURN_1 | FSMC_BTR1_BUSTURN_3) ;
+
+			// Bank1 NOR/SRAM control register configuration
+			// This is actually not needed as already set by default after reset
+			FSMC_Bank1->BTCR[FSMC_BANK] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
+
+			break;
+		}
+
+		// marlin does not have any secondary display so far
+		default:
+			break;
+	}
+}
+
+static inline void post_init_board(GDisplay *g) {
+	(void) g;
+	
+	// FSMC delay reduced as the controller now runs at full speed
+	FSMC_Bank1->BTCR[2+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0 ;
+	FSMC_Bank1->BTCR[2] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	(void) state;
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void write_index(GDisplay *g, uint16_t index) {
+	(void) g;
+
+	GDISP_REG = index;
+}
+
+static inline void write_data(GDisplay *g, uint16_t data) {
+	(void) g;
+
+	GDISP_RAM = data;
+}
+
+static inline void setreadmode(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setwritemode(GDisplay *g) {
+	(void) g;
+}
+
+static inline uint16_t read_data(GDisplay *g) {
+	(void) g;
+
+	return GDISP_RAM;
+}
+
+#endif /* _BOARD_RA8875_H */
+
diff --git a/boards/addons/gdisp/board_S6D1121_olimex_e407.h b/boards/addons/gdisp/board_S6D1121_olimex_e407.h
new file mode 100644
index 00000000..e0bb8e26
--- /dev/null
+++ b/boards/addons/gdisp/board_S6D1121_olimex_e407.h
@@ -0,0 +1,91 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/gdisp/S6D1121/board_S6D1121_olimex_e407.h
+ * @brief   GDISP Graphic Driver subsystem board interface for the S6D1121 display
+ */
+
+#ifndef _GDISP_LLD_BOARD_H
+#define _GDISP_LLD_BOARD_H
+
+// For a multiple display configuration we would put all this in a structure and then
+//	set g->board to that structure.
+#define GDISP_REG              (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
+#define GDISP_RAM              (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
+
+static inline void init_board(GDisplay *g) {
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		/* STM32F4 FSMC init */
+		rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
+
+		/* set pins to FSMC mode */
+		IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) |
+							(1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0};
+
+		IOBus busE = {GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
+							(1 << 13) | (1 << 14) | (1 << 15), 0};
+
+		palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
+		palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
+
+		/* FSMC timing */
+		FSMC_Bank1->BTCR[0+1] = (6) | (10 << 8) | (10 << 16);
+
+		/* Bank1 NOR/SRAM control register configuration */
+		FSMC_Bank1->BTCR[0] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
+		break;
+	}
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	(void) state;
+}
+
+static inline void set_backlight(GDisplay *g, uint8_t percent) {
+	(void) g;
+	(void) percent;
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void write_index(GDisplay *g, uint16_t index) {
+	(void) g;
+	GDISP_REG = index;
+}
+
+static inline void write_data(GDisplay *g, uint16_t data) {
+	(void) g;
+	GDISP_RAM = data;
+}
+
+static inline void setreadmode(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setwritemode(GDisplay *g) {
+	(void) g;
+}
+
+static inline uint16_t read_data(GDisplay *g) {
+	(void) g;
+	return GDISP_RAM;
+}
+
+#endif /* _GDISP_LLD_BOARD_H */
diff --git a/boards/addons/gdisp/board_SSD1289_firebullstm32f103.h b/boards/addons/gdisp/board_SSD1289_firebullstm32f103.h
new file mode 100644
index 00000000..99d37299
--- /dev/null
+++ b/boards/addons/gdisp/board_SSD1289_firebullstm32f103.h
@@ -0,0 +1,108 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/gdisp/SSD1289/board_SSD1289_firebullstm32f103.h
+ * @brief   GDISP Graphic Driver subsystem board interface for the SSD1289 display.
+ */
+
+#ifndef _GDISP_LLD_BOARD_H
+#define _GDISP_LLD_BOARD_H
+
+// For a multiple display configuration we would put all this in a structure and then
+//	set g->board to that structure.
+#define SET_CS		palSetPad(GPIOD, 12);
+#define CLR_CS		palClearPad(GPIOD, 12);
+#define SET_RS		palSetPad(GPIOD, 13);
+#define CLR_RS		palClearPad(GPIOD, 13);
+#define SET_WR		palSetPad(GPIOD, 14);
+#define CLR_WR		palClearPad(GPIOD, 14);
+#define SET_RD		palSetPad(GPIOD, 15);
+#define CLR_RD		palClearPad(GPIOD, 15);
+
+static inline void init_board(GDisplay *g) {
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
+		palSetPadMode(GPIOD, 12, PAL_MODE_OUTPUT_PUSHPULL);
+		palSetPadMode(GPIOD, 13, PAL_MODE_OUTPUT_PUSHPULL);
+		palSetPadMode(GPIOD, 14, PAL_MODE_OUTPUT_PUSHPULL);
+		palSetPadMode(GPIOD, 15, PAL_MODE_OUTPUT_PUSHPULL);
+
+		// Configure the pins to a well know state
+		SET_RS;
+		SET_RD;
+		SET_WR;
+		CLR_CS;
+		break;
+	}
+}
+
+static inline void post_init_board(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	(void) state;
+	/* Nothing to do here - reset pin tied to Vcc */
+}
+
+static inline void set_backlight(GDisplay *g, uint8_t percent) {
+	(void) g;
+	(void) percent;
+	/* Nothing to do here - Backlight always on */
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void write_index(GDisplay *g, uint16_t index) {
+	(void) g;
+	palWritePort(GPIOE, index);
+	CLR_RS; CLR_WR; SET_WR; SET_RS;
+}
+
+static inline void write_data(GDisplay *g, uint16_t data) {
+	(void) g;
+	palWritePort(GPIOE, data);
+	CLR_WR; SET_WR;
+}
+
+static inline void setreadmode(GDisplay *g) {
+	(void) g;
+	// change pin mode to digital input
+	palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_INPUT);
+	CLR_RD;
+}
+
+static inline void setwritemode(GDisplay *g) {
+	(void) g;
+	// change pin mode back to digital output
+	SET_RD;
+	palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
+}
+
+static inline uint16_t read_data(GDisplay *g) {
+	return palReadPort(GPIOE);
+}
+
+#if defined(GDISP_USE_DMA)
+	#error "GDISP - SSD1289: The GPIO interface does not support DMA"
+#endif
+
+#endif /* _GDISP_LLD_BOARD_H */
+
diff --git a/boards/addons/gdisp/board_SSD1289_stm32f4discovery.h b/boards/addons/gdisp/board_SSD1289_stm32f4discovery.h
new file mode 100644
index 00000000..866311dc
--- /dev/null
+++ b/boards/addons/gdisp/board_SSD1289_stm32f4discovery.h
@@ -0,0 +1,172 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/gdisp/SSD1289/board_SSD1289_stm32f4discovery.h
+ * @brief   GDISP Graphic Driver subsystem board interface for the SSD1289 display.
+ */
+
+#ifndef _GDISP_LLD_BOARD_H
+#define _GDISP_LLD_BOARD_H
+
+// For a multiple display configuration we would put all this in a structure and then
+//	set g->board to that structure.
+#define GDISP_REG              ((volatile uint16_t *) 0x60000000)[0] /* RS = 0 */
+#define GDISP_RAM              ((volatile uint16_t *) 0x60020000)[0] /* RS = 1 */
+#define GDISP_DMA_STREAM		STM32_DMA2_STREAM6
+#define FSMC_BANK				0
+
+/* PWM configuration structure. We use timer 3 channel 3 */
+static const PWMConfig pwmcfg = {
+  100000,       /* 100 kHz PWM clock frequency. */
+  100,          /* PWM period is 100 cycles. */
+  NULL,
+  {
+   {PWM_OUTPUT_DISABLED, NULL},
+   {PWM_OUTPUT_DISABLED, NULL},
+   {PWM_OUTPUT_ACTIVE_HIGH, NULL},
+   {PWM_OUTPUT_DISABLED, NULL}
+  },
+  0
+};
+
+static inline void init_board(GDisplay *g) {
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		/**
+		 * Performs the following functions:
+		 *		1. initialise the io port used by the display
+		 *		2. initialise the reset pin (initial state not-in-reset)
+		 *		3. initialise the chip select pin (initial state not-active)
+		 *		4. initialise the backlight pin (initial state back-light off)
+		 */
+
+		#if defined(STM32F1XX) || defined(STM32F3XX)
+			/* FSMC setup for F1/F3 */
+			rccEnableAHB(RCC_AHBENR_FSMCEN, 0);
+
+			#if defined(GDISP_USE_DMA)
+				#error "GDISP: SSD1289 - DMA not implemented for F1/F3 Devices"
+			#endif
+		#elif defined(STM32F4XX) || defined(STM32F2XX)
+			/* STM32F2-F4 FSMC init */
+			rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
+
+			#if defined(GDISP_USE_DMA)
+				if (dmaStreamAllocate(GDISP_DMA_STREAM, 0, NULL, NULL)) gfxExit();
+				dmaStreamSetMemory0(GDISP_DMA_STREAM, &GDISP_RAM);
+				dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
+			#else
+				#warning "GDISP: SSD1289 - DMA is supported for F2/F4 Devices. Define GDISP_USE_DMA in your gfxconf.h to turn this on for better performance."
+			#endif
+		#else
+			#error "GDISP: SSD1289 - FSMC not implemented for this device"
+		#endif
+
+		/* set pins to FSMC mode */
+		IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) |
+								(1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0};
+
+		IOBus busE = {GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
+							(1 << 13) | (1 << 14) | (1 << 15), 0};
+
+		palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
+		palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
+
+		/* FSMC timing */
+		FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0 ;
+
+		/* Bank1 NOR/SRAM control register configuration
+		 * This is actually not needed as already set by default after reset */
+		FSMC_Bank1->BTCR[FSMC_BANK] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
+
+		/* Display backlight control */
+		/* TIM3 is an alternate function 2 (AF2) */
+		pwmStart(&PWMD3, &pwmcfg);
+		palSetPadMode(GPIOB, 0, PAL_MODE_ALTERNATE(2));
+		pwmEnableChannel(&PWMD3, 2, 100);
+		break;
+	}
+}
+
+static inline void post_init_board(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	(void) state;
+}
+
+static inline void set_backlight(GDisplay *g, uint8_t percent) {
+	(void) g;
+    pwmEnableChannel(&PWMD3, 2, percent);
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void write_index(GDisplay *g, uint16_t index) {
+	(void) g;
+	GDISP_REG = index;
+}
+
+static inline void write_data(GDisplay *g, uint16_t data) {
+	(void) g;
+	GDISP_RAM = data;
+}
+
+static inline void setreadmode(GDisplay *g) {
+	(void) g;
+	FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_3 | FSMC_BTR1_DATAST_3 | FSMC_BTR1_BUSTURN_0;		/* FSMC timing */
+}
+
+static inline void setwritemode(GDisplay *g) {
+	(void) g;
+	FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0;		/* FSMC timing */
+}
+
+static inline uint16_t read_data(GDisplay *g) {
+	(void) g;
+	return GDISP_RAM;
+}
+
+#if defined(GDISP_USE_DMA) || defined(__DOXYGEN__)
+	static inline void dma_with_noinc(GDisplay *g, color_t *buffer, int area) {
+		(void) g;
+		dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer);
+		dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
+		for (; area > 0; area -= 65535) {
+			dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area > 65535 ? 65535 : area);
+			dmaStreamEnable(GDISP_DMA_STREAM);
+			dmaWaitCompletion(GDISP_DMA_STREAM);
+		}
+	}
+
+	static inline void dma_with_inc(GDisplay *g, color_t *buffer, int area) {
+		(void) g;
+        dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer);
+        dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PINC | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
+		for (; area > 0; area -= 65535) {
+			dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area > 65535 ? 65535 : area);
+			dmaStreamEnable(GDISP_DMA_STREAM);
+			dmaWaitCompletion(GDISP_DMA_STREAM);
+		}
+	}
+#endif
+
+#endif /* _GDISP_LLD_BOARD_H */
+
diff --git a/boards/addons/gdisp/board_SSD1306_i2c.h b/boards/addons/gdisp/board_SSD1306_i2c.h
new file mode 100644
index 00000000..449d47ba
--- /dev/null
+++ b/boards/addons/gdisp/board_SSD1306_i2c.h
@@ -0,0 +1,129 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/gdisp/SSD1306/board_SSD1306_i2c.h
+ * @brief   GDISP Graphic Driver subsystem board interface for the SSD1306 display.
+ */
+
+#ifndef _GDISP_LLD_BOARD_H
+#define _GDISP_LLD_BOARD_H
+
+// The command byte to put on the front of each page line
+#define SSD1306_PAGE_PREFIX		0x40			 		// Co = 0, D/C = 1
+
+// For a multiple display configuration we would put all this in a structure and then
+//	set g->board to that structure.
+#define SSD1306_RESET_PORT		GPIOB
+#define SSD1306_RESET_PIN		5
+
+/**
+ * The default slave address is 0x3D, (talking about
+ * only the real address part here) and the slave
+ * address can be changed to 0x3C by soldering the
+ * SA0 pads on the bottom side of the module.
+ *
+ * b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0
+ * --------------------------------------
+ * 0  | 1  | 1  | 1  | 1  | 0  |SA0 | R/W
+ */
+#define SSD1306_I2C_ADDRESS   	0x3D
+#define SSD1306_SDA_PORT		GPIOB
+#define SSD1306_SDA_PIN			7
+#define SSD1306_SCL_PORT		GPIOB
+#define SSD1306_SCL_PIN			6
+#define SET_RST					palSetPad(SSD1306_RESET_PORT, SSD1306_RESET_PIN);
+#define CLR_RST					palClearPad(SSD1306_RESET_PORT, SSD1306_RESET_PIN);
+
+// I2C configuration structure.
+static I2CConfig i2cconfig;
+
+#if GFX_USE_OS_CHIBIOS
+	static int32_t thdPriority = 0;
+#endif
+
+static inline void init_board(GDisplay *g) {
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		// RESET pin.
+		palSetPadMode(SSD1306_RESET_PORT, SSD1306_RESET_PIN, PAL_MODE_OUTPUT_PUSHPULL);
+
+
+		/*
+		 * Initializes the I2C driver 1. The I2C1 signals are routed as follows:
+		 * PB6 - SCL.
+		 * PB7 - SDA.
+		 * Timing value comes from ST I2C config tool (xls):
+		 * 0x00901D2B;		// 100kHz Standard Mode
+		 * 0x00300444;		// 100kHz Fast Mode
+		 * 0x0030020A;		// 400kHz Fast Mode
+		 * 0x00100002;		// 800kHz Fast Mode +
+		 */
+		palSetPadMode(SSD1306_SCL_PORT, SSD1306_SCL_PIN, PAL_MODE_ALTERNATE(1));
+		palSetPadMode(SSD1306_SDA_PORT, SSD1306_SDA_PIN, PAL_MODE_ALTERNATE(1));
+		i2cconfig.timingr = 0x00100002;		// 800kHz Fast Mode+
+		i2cInit();
+		break;
+	}
+}
+
+static inline void post_init_board(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	if(state)
+		CLR_RST
+	else
+		SET_RST
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+	#if GFX_USE_OS_CHIBIOS
+		thdPriority = (int32_t)chThdGetPriority();
+		chThdSetPriority(HIGHPRIO);
+	#endif
+	i2cAcquireBus(&I2CD1);
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+	#if GFX_USE_OS_CHIBIOS
+		chThdSetPriority(thdPriority);
+	#endif
+	i2cReleaseBus(&I2CD1);
+}
+
+static inline void write_cmd(GDisplay *g, uint8_t cmd) {
+	uint8_t command[2];
+	(void) g;
+
+	command[0] = 0x00;		// Co = 0, D/C = 0
+	command[1] = cmd;
+
+	i2cStart(&I2CD1, &i2cconfig);
+	i2cMasterTransmitTimeout(&I2CD1, SSD1306_I2C_ADDRESS, command, 2, NULL, 0, MS2ST(10));
+	i2cStop(&I2CD1);
+}
+
+static inline void write_data(GDisplay *g, uint8_t* data, uint16_t length) {
+	(void) g;
+
+	i2cStart(&I2CD1, &i2cconfig);
+	i2cMasterTransmitTimeout(&I2CD1, SSD1306_I2C_ADDRESS, data, length, NULL, 0, MS2ST(10));
+	i2cStop(&I2CD1);
+}
+
+#endif /* _GDISP_LLD_BOARD_H */
+
+
diff --git a/boards/addons/gdisp/board_SSD1306_spi.h b/boards/addons/gdisp/board_SSD1306_spi.h
new file mode 100644
index 00000000..21bf095f
--- /dev/null
+++ b/boards/addons/gdisp/board_SSD1306_spi.h
@@ -0,0 +1,133 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/gdisp/SSD1306/board_SSD1306_spi.h
+ * @brief   GDISP Graphic Driver subsystem board interface for the SSD1306 display.
+ */
+
+#ifndef _GDISP_LLD_BOARD_H
+#define _GDISP_LLD_BOARD_H
+
+// The command byte to put on the front of each page line
+#define SSD1306_PAGE_PREFIX		0x40			 		// Co = 0, D/C = 1
+
+// For a multiple display configuration we would put all this in a structure and then
+//	set g->board to that structure.
+#define SSD1306_RESET_PORT		GPIOB
+#define SSD1306_RESET_PIN		5
+#define SSD1306_MISO_PORT		GPIOB
+#define SSD1306_MISO_PIN		8
+#define SSD1306_MOSI_PORT		GPIOB
+#define SSD1306_MOSI_PIN		7
+#define SSD1306_SCK_PORT		GPIOB
+#define SSD1306_SCK_PIN			6
+#define SSD1306_CS_PORT			GPIOB
+#define SSD1306_CS_PIN			5
+#define SET_RST					palSetPad(SSD1306_RESET_PORT, SSD1306_RESET_PIN);
+#define CLR_RST					palClearPad(SSD1306_RESET_PORT, SSD1306_RESET_PIN);
+
+/*
+ * SPI1 configuration structure.
+ * Speed 42MHz, CPHA=0, CPOL=0, 8bits frames, MSb transmitted first.
+ * The slave select line is the pin 4 on the port GPIOA.
+ */
+static const SPIConfig spi1config = {
+	NULL,
+	/* HW dependent part.*/
+	SSD1306_MISO_PORT,
+	SSD1306_MISO_PIN,
+	0
+	//SPI_CR1_BR_0
+};
+
+#if GFX_USE_OS_CHIBIOS
+	static int32_t thdPriority = 0;
+#endif
+
+static inline void init_board(GDisplay *g) {
+	unsigned	i;
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		// RESET pin.
+		palSetPadMode(SSD1306_RESET_PORT, SSD1306_RESET_PIN, PAL_MODE_OUTPUT_PUSHPULL);
+
+		palSetPadMode(SSD1306_MISO_PORT, SSD1306_MISO_PIN, 	PAL_MODE_ALTERNATE(1)|
+															PAL_STM32_OSPEED_HIGHEST);
+		palSetPadMode(SSD1306_MOSI_PORT, SSD1306_MOSI_PIN, 	PAL_MODE_ALTERNATE(1)|
+															PAL_STM32_OSPEED_HIGHEST);
+		palSetPadMode(SSD1306_SCK_PORT,  SSD1306_SCK_PIN,  	PAL_MODE_ALTERNATE(1)|
+															PAL_STM32_OSPEED_HIGHEST);
+		palSetPad(SSD1306_CS_PORT, SSD1306_CS_PIN);
+		palSetPadMode(SSD1306_CS_PORT,   SSD1306_CS_PIN,   	PAL_MODE_ALTERNATE(1)|
+															PAL_STM32_OSPEED_HIGHEST);
+		spiInit();
+		break;
+	}
+}
+
+static inline void post_init_board(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	if(state)
+		CLR_RST
+	else
+		SET_RST
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+	#if GFX_USE_OS_CHIBIOS
+		thdPriority = (int32_t)chThdGetPriority();
+		chThdSetPriority(HIGHPRIO);
+	#endif
+	spiAcquireBus(&SPID1);
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+	#if GFX_USE_OS_CHIBIOS
+		chThdSetPriority(thdPriority);
+	#endif
+	spiReleaseBus(&SPID1);
+}
+
+static inline void write_cmd(GDisplay *g, uint8_t cmd) {
+	uint8_t command[2];
+	(void)	g;
+
+	command[0] = 0x00;		// Co = 0, D/C = 0
+	command[1] = cmd;
+
+	spiStart(&SPID1, &spi1config);
+	spiSelect(&SPID1);
+	spiStartSend(&SPID1, 2, command);
+	spiUnselect(&SPID1);
+	spiStop(&SPID1);
+}
+
+static inline void write_data(GDisplay *g, uint8_t* data, uint16_t length) {
+	(void) g;
+
+	spiStart(&SPID1, &spi1config);
+	spiSelect(&SPID1);
+	spiStartSend(&SPID1, length, data);
+	spiUnselect(&SPID1);
+	spiStop(&SPID1);
+}
+
+
+#endif /* _GDISP_LLD_BOARD_H */
+
diff --git a/boards/addons/gdisp/board_SSD1963_fsmc.h b/boards/addons/gdisp/board_SSD1963_fsmc.h
new file mode 100644
index 00000000..6c7119a4
--- /dev/null
+++ b/boards/addons/gdisp/board_SSD1963_fsmc.h
@@ -0,0 +1,105 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://chibios-gfx.com/license.html
+ */
+
+/**
+ * @file    drivers/gdisp/SSD1963/board_SSD1963_fsmc.h
+ * @brief   GDISP Graphic Driver subsystem board interface for the SSD1963 display.
+ */
+
+#ifndef _GDISP_LLD_BOARD_H
+#define _GDISP_LLD_BOARD_H
+
+static const LCD_Parameters	DisplayTimings[] = {
+	// You need one of these array elements per display
+	{
+		480, 272,								// Panel width and height
+		2, 2, 41,								// Horizontal Timings (back porch, front porch, pulse)
+		CALC_PERIOD(480,2,2,41),				// Total Horizontal Period (calculated from above line)
+		2, 2, 10,								// Vertical Timings (back porch, front porch, pulse)
+		CALC_PERIOD(272,2,2,10),				// Total Vertical Period (calculated from above line)
+		CALC_FPR(480,272,2,2,41,2,2,10,60ULL)	// FPR - the 60ULL is the frames per second. Note the ULL!
+	},
+};
+
+// For a multiple display configuration we would put all this in a structure and then
+//	set g->board to that structure.
+
+/* Using FSMC A16 as RS */
+#define GDISP_REG              (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
+#define GDISP_RAM              (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
+
+static inline void init_board(GDisplay *g) {
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		#if defined(STM32F1XX) || defined(STM32F3XX)
+			/* FSMC setup for F1/F3 */
+			rccEnableAHB(RCC_AHBENR_FSMCEN, 0);
+		#elif defined(STM32F4XX) || defined(STM32F2XX)
+			/* STM32F2-F4 FSMC init */
+			rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
+		#else
+			#error "FSMC not implemented for this device"
+		#endif
+
+		/* set pins to FSMC mode */
+		IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) |
+								(1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0};
+
+		IOBus busE = {GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
+							(1 << 13) | (1 << 14) | (1 << 15), 0};
+	
+		palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
+		palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
+
+		/* FSMC timing */
+		FSMC_Bank1->BTCR[0+1] = (FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_3) \
+				| (FSMC_BTR1_DATAST_1 | FSMC_BTR1_DATAST_3) \
+				| (FSMC_BTR1_BUSTURN_1 | FSMC_BTR1_BUSTURN_3) ;
+	
+		/* Bank1 NOR/SRAM control register configuration
+		 * This is actually not needed as already set by default after reset */
+		FSMC_Bank1->BTCR[0] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
+		break;
+	}
+}
+
+static inline void post_init_board(GDisplay *g) {
+	(void) g;
+	/* FSMC delay reduced as the controller now runs at full speed */
+	FSMC_Bank1->BTCR[0+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0 ;
+	FSMC_Bank1->BTCR[0] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	(void) state;
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void write_index(GDisplay *g, uint16_t index) {
+	(void) g;
+	GDISP_REG = index;
+}
+
+static inline void write_data(GDisplay *g, uint16_t data) {
+	(void) g;
+	GDISP_RAM = data;
+}
+
+#endif /* _GDISP_LLD_BOARD_H */
+
diff --git a/boards/addons/gdisp/board_SSD1963_gpio.h b/boards/addons/gdisp/board_SSD1963_gpio.h
new file mode 100644
index 00000000..0b9c0135
--- /dev/null
+++ b/boards/addons/gdisp/board_SSD1963_gpio.h
@@ -0,0 +1,102 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://chibios-gfx.com/license.html
+ */
+
+/**
+ * @file    drivers/gdisp/SSD1963/board_SSD1963_gpio.h
+ * @brief   GDISP Graphic Driver subsystem board interface for the SSD1963 display.
+ */
+
+#ifndef _GDISP_LLD_BOARD_H
+#define _GDISP_LLD_BOARD_H
+
+static const LCD_Parameters	DisplayTimings[] = {
+	// You need one of these array elements per display
+	{
+		480, 272,								// Panel width and height
+		2, 2, 41,								// Horizontal Timings (back porch, front porch, pulse)
+		CALC_PERIOD(480,2,2,41),				// Total Horizontal Period (calculated from above line)
+		2, 2, 10,								// Vertical Timings (back porch, front porch, pulse)
+		CALC_PERIOD(272,2,2,10),				// Total Vertical Period (calculated from above line)
+		CALC_FPR(480,272,2,2,41,2,2,10,60ULL)	// FPR - the 60ULL is the frames per second. Note the ULL!
+	},
+};
+
+// For a multiple display configuration we would put all this in a structure and then
+//	set g->board to that structure.
+
+/**
+ * @brief	The GPIO pin config
+ *
+ * @details	This block of defines tell your driver how you wired your display
+ *			controller to your MCU. Please change them accordingly.
+ */
+#define GDISP_CMD_PORT		GPIOC
+#define GDISP_DATA_PORT		GPIOD
+#define GDISP_CS			0
+#define GDISP_RS			1
+#define GDISP_WR			2
+#define GDISP_RD			3
+
+#define Set_CS		palSetPad(GDISP_CMD_PORT, GDISP_CS);
+#define Clr_CS		palClearPad(GDISP_CMD_PORT, GDISP_CS);
+#define Set_RS		palSetPad(GDISP_CMD_PORT, GDISP_RS);
+#define Clr_RS		palClearPad(GDISP_CMD_PORT, GDISP_RS);
+#define Set_WR		palSetPad(GDISP_CMD_PORT, GDISP_WR);
+#define Clr_WR		palClearPad(GDISP_CMD_PORT, GDISP_WR);
+#define Set_RD		palSetPad(GDISP_CMD_PORT, GDISP_RD);
+#define Clr_RD		palClearPad(GDISP_CMD_PORT, GDISP_RD);
+
+static inline void init_board(GDisplay *g) {
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		IOBus busCMD = {GDISP_CMD_PORT, (1 << GDISP_CS) | (1 << GDISP_RS) | (1 << GDISP_WR) | (1 << GDISP_RD), 0};
+		IOBus busDATA = {GDISP_CMD_PORT, 0xFFFFF, 0};
+		palSetBusMode(&busCMD, PAL_MODE_OUTPUT_PUSHPULL);
+		palSetBusMode(&busDATA, PAL_MODE_OUTPUT_PUSHPULL);
+		break;
+	}
+}
+
+static inline void post_init_board(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	(void) state;
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+	Set_CS;
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+	Clr_CS;
+}
+
+static inline void write_index(GDisplay *g, uint16_t index) {
+	(void) g;
+	Set_RS; Clr_RD; Set_WR;
+	palWritePort(GDISP_DATA_PORT, index);
+	Clr_WR;
+}
+
+static inline void write_data(GDisplay *g, uint16_t data) {
+	(void) g;
+	Clr_RS; Clr_RD; Set_WR;
+	palWritePort(GDISP_DATA_PORT, data);
+	Clr_WR;
+}
+
+#endif /* _GDISP_LLD_BOARD_H */
+
diff --git a/boards/addons/gdisp/board_SSD2119_embest_dmstf4bb.h b/boards/addons/gdisp/board_SSD2119_embest_dmstf4bb.h
new file mode 100644
index 00000000..927e93a4
--- /dev/null
+++ b/boards/addons/gdisp/board_SSD2119_embest_dmstf4bb.h
@@ -0,0 +1,173 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/gdisp/SSD2119/board_SSD2119_embest_dmstf4bb.h
+ * @brief   GDISP Graphic Driver subsystem board FSMC interface for the SSD2119 display.
+ */
+
+#ifndef _GDISP_LLD_BOARD_H
+#define _GDISP_LLD_BOARD_H
+
+// For a multiple display configuration we would put all this in a structure and then
+//	set g->board to that structure.
+
+/* Using FSMC A19 (PE3) as DC */
+#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* DC = 0 */
+#define GDISP_RAM (*((volatile uint16_t *) 0x60100000)) /* DC = 1 */
+#define GDISP_DMA_STREAM STM32_DMA2_STREAM6
+
+#define SET_RST palSetPad(GPIOD, 3);
+#define CLR_RST palClearPad(GPIOD, 3);
+
+/*
+ * PWM configuration structure. We use timer 4 channel 2 (orange LED on board).
+ * The reason for so high clock is that with any lower, onboard coil is squeaking.
+ * The major disadvantage of this clock is a lack of linearity between PWM duty
+ * cycle width and brightness. In fact only with low preset one sees any change
+ * (eg. duty cycle between 1-20). Feel free to adjust this, maybe only my board
+ * behaves like this. According to the G5126 datesheet (backlight LED driver)
+ * the PWM frequency should be somewhere between 200 Hz to 200 kHz.
+ */
+static const PWMConfig pwmcfg = {
+	1000000,       /* 1 MHz PWM clock frequency. */
+	100,           /* PWM period is 100 cycles. */
+	NULL,
+	{
+		{PWM_OUTPUT_ACTIVE_HIGH, NULL},
+		{PWM_OUTPUT_ACTIVE_HIGH, NULL},
+		{PWM_OUTPUT_ACTIVE_HIGH, NULL},
+		{PWM_OUTPUT_ACTIVE_HIGH, NULL}
+	},
+	0
+};
+
+static inline void init_board(GDisplay *g) {
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		#if defined(STM32F4XX) || defined(STM32F2XX)
+			/* STM32F4 FSMC init */
+			rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
+
+			#if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
+				if (dmaStreamAllocate(GDISP_DMA_STREAM, 0, NULL, NULL))
+					gfxExit();
+				dmaStreamSetMemory0(GDISP_DMA_STREAM, &GDISP_RAM);
+				dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
+			#endif
+		#else
+			#error "FSMC not implemented for this device"
+		#endif
+
+		/* Group pins */
+		IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) |
+								(1 << 9) | (1 << 10) | (1 << 14) | (1 << 15), 0};
+
+		IOBus busE = {GPIOE, (1 << 3) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
+								(1 << 13) | (1 << 14) | (1 << 15), 0};
+
+		/* FSMC is an alternate function 12 (AF12) */
+		palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
+		palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
+
+		/* FSMC timing register configuration */
+		FSMC_Bank1->BTCR[0 + 1] = (FSMC_BTR1_ADDSET_2 | FSMC_BTR1_ADDSET_1) \
+				| (FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_1) \
+				| FSMC_BTR1_BUSTURN_0;
+
+		/* Bank1 NOR/PSRAM control register configuration
+		 * Write enable, memory databus width set to 16 bit, memory bank enable */
+		FSMC_Bank1->BTCR[0] = FSMC_BCR1_WREN | FSMC_BCR1_MWID_0 | FSMC_BCR1_MBKEN;
+
+		/* Display backlight control */
+		/* TIM4 is an alternate function 2 (AF2) */
+		pwmStart(&PWMD4, &pwmcfg);
+		palSetPadMode(GPIOD, 13, PAL_MODE_ALTERNATE(2));
+		pwmEnableChannel(&PWMD4, 1, 100);
+		break;
+	}
+}
+
+static inline void post_init_board(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	if (state) {
+		CLR_RST;
+	} else {
+		SET_RST;
+	}
+}
+
+static inline void set_backlight(GDisplay *g, uint8_t percent) {
+	(void) g;
+	pwmEnableChannel(&PWMD4, 1, percent);
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void write_index(GDisplay *g, uint16_t index) {
+	(void) g;
+	GDISP_REG = index;
+}
+
+static inline void write_data(GDisplay *g, uint16_t data) {
+	(void) g;
+	GDISP_RAM = data;
+}
+
+static inline void setreadmode(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setwritemode(GDisplay *g) {
+	(void) g;
+}
+
+static inline uint16_t read_data(GDisplay *g) {
+	(void) g;
+	return GDISP_RAM;
+}
+
+#if defined(GDISP_USE_DMA)
+	static inline void dma_with_noinc(GDisplay *g, color_t *buffer, int area) {
+		(void) g;
+		dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer);
+		dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
+		for (; area > 0; area -= 65535) {
+			dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area > 65535 ? 65535 : area);
+			dmaStreamEnable(GDISP_DMA_STREAM);
+			dmaWaitCompletion(GDISP_DMA_STREAM);
+		}
+	}
+
+	static inline void dma_with_inc(GDisplay *g, color_t *buffer, int area) {
+		(void) g;
+        dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer);
+        dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PINC | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
+		for (; area > 0; area -= 65535) {
+			dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area > 65535 ? 65535 : area);
+			dmaStreamEnable(GDISP_DMA_STREAM);
+			dmaWaitCompletion(GDISP_DMA_STREAM);
+		}
+	}
+#endif
+
+#endif /* _GDISP_LLD_BOARD_H */
+
diff --git a/boards/addons/ginput/touch/ADS7843/ginput_lld_mouse_board_firebull_stm32f103.h b/boards/addons/ginput/touch/ADS7843/ginput_lld_mouse_board_firebull_stm32f103.h
new file mode 100644
index 00000000..63e9e3dd
--- /dev/null
+++ b/boards/addons/ginput/touch/ADS7843/ginput_lld_mouse_board_firebull_stm32f103.h
@@ -0,0 +1,90 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/ginput/touch/ADS7843/ginput_lld_mouse_board_firebull_stm32f103.h
+ * @brief   GINPUT ouch low level driver source for the ADS7843 on the FireBull STM32F103-FB board.
+ *
+ * @defgroup Mouse Mouse
+ * @ingroup GINPUT
+ * @{
+ */
+
+#ifndef _GINPUT_LLD_MOUSE_BOARD_H
+#define _GINPUT_LLD_MOUSE_BOARD_H
+
+static const SPIConfig spicfg = { 
+    NULL,
+	GPIOC, 
+    6,
+    /* SPI_CR1_BR_2 |*/ SPI_CR1_BR_1 | SPI_CR1_BR_0,
+};
+
+/**
+ * @brief   Initialise the board for the touch.
+ *
+ * @notapi
+ */
+static inline void init_board(void) {
+	spiStart(&SPID1, &spicfg);
+}
+
+/**
+ * @brief   Check whether the surface is currently touched
+ * @return	TRUE if the surface is currently touched
+ *
+ * @notapi
+ */
+static inline bool_t getpin_pressed(void) {
+	return (!palReadPad(GPIOC, 4));
+}
+/**
+ * @brief   Aquire the bus ready for readings
+ *
+ * @notapi
+ */
+static inline void aquire_bus(void) {
+	spiAcquireBus(&SPID1);
+    //TOUCHSCREEN_SPI_PROLOGUE();
+    palClearPad(GPIOC, 6);
+}
+
+/**
+ * @brief   Release the bus after readings
+ *
+ * @notapi
+ */
+static inline void release_bus(void) {
+	palSetPad(GPIOC, 6);
+	spiReleaseBus(&SPID1);
+    //TOUCHSCREEN_SPI_EPILOGUE();
+}
+
+/**
+ * @brief   Read a value from touch controller
+ * @return	The value read from the controller
+ *
+ * params[in] port	The controller port to read.
+ *
+ * @notapi
+ */
+static inline uint16_t read_value(uint16_t port) {
+    static uint8_t txbuf[3] = {0};
+    static uint8_t rxbuf[3] = {0};
+    uint16_t ret;
+
+    txbuf[0] = port;
+
+    spiExchange(&SPID1, 3, txbuf, rxbuf);
+
+    ret = (rxbuf[1] << 5) | (rxbuf[2] >> 3); 
+    
+	return ret;
+}
+
+#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
+/** @} */
diff --git a/boards/addons/ginput/touch/ADS7843/ginput_lld_mouse_board_olimex_stm32_e407.h b/boards/addons/ginput/touch/ADS7843/ginput_lld_mouse_board_olimex_stm32_e407.h
new file mode 100644
index 00000000..e0ab85dc
--- /dev/null
+++ b/boards/addons/ginput/touch/ADS7843/ginput_lld_mouse_board_olimex_stm32_e407.h
@@ -0,0 +1,90 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/ginput/touch/ADS7843/ginput_lld_mouse_board_olimex_stm32_e407.h
+ * @brief   GINPUT Touch low level driver source for the ADS7843 on an Olimex STM32E407.
+ *
+ * @defgroup Mouse Mouse
+ * @ingroup GINPUT
+ * @{
+ */
+
+#ifndef _GINPUT_LLD_MOUSE_BOARD_H
+#define _GINPUT_LLD_MOUSE_BOARD_H
+
+static const SPIConfig spicfg = { 
+    NULL,
+	GPIOG, 
+    10,
+    /* SPI_CR1_BR_2 |*/ SPI_CR1_BR_1 | SPI_CR1_BR_0,
+};
+
+/**
+ * @brief   Initialise the board for the touch.
+ *
+ * @notapi
+ */
+static inline void init_board(void) {
+	spiStart(&SPID2, &spicfg);
+}
+
+/**
+ * @brief   Check whether the surface is currently touched
+ * @return	TRUE if the surface is currently touched
+ *
+ * @notapi
+ */
+static inline bool_t getpin_pressed(void) {
+	return (!palReadPad(GPIOG, 0));
+}
+/**
+ * @brief   Aquire the bus ready for readings
+ *
+ * @notapi
+ */
+static inline void aquire_bus(void) {
+	spiAcquireBus(&SPID2);
+    //TOUCHSCREEN_SPI_PROLOGUE();
+    palClearPad(GPIOG, 10);
+}
+
+/**
+ * @brief   Release the bus after readings
+ *
+ * @notapi
+ */
+static inline void release_bus(void) {
+	palSetPad(GPIOG, 10);
+	spiReleaseBus(&SPID2);
+    //TOUCHSCREEN_SPI_EPILOGUE();
+}
+
+/**
+ * @brief   Read a value from touch controller
+ * @return	The value read from the controller
+ *
+ * params[in] port	The controller port to read.
+ *
+ * @notapi
+ */
+static inline uint16_t read_value(uint16_t port) {
+    static uint8_t txbuf[3] = {0};
+    static uint8_t rxbuf[3] = {0};
+    uint16_t ret;
+
+    txbuf[0] = port;
+
+    spiExchange(&SPID2, 3, txbuf, rxbuf);
+
+    ret = (rxbuf[1] << 5) | (rxbuf[2] >> 3); 
+    
+	return ret;
+}
+
+#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
+/** @} */
diff --git a/boards/addons/ginput/touch/ADS7843/ginput_lld_mouse_board_st_stm32f4_discovery.h b/boards/addons/ginput/touch/ADS7843/ginput_lld_mouse_board_st_stm32f4_discovery.h
new file mode 100644
index 00000000..158934b6
--- /dev/null
+++ b/boards/addons/ginput/touch/ADS7843/ginput_lld_mouse_board_st_stm32f4_discovery.h
@@ -0,0 +1,90 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/ginput/touch/ADS7843/ginput_lld_mouse_board_olimex_stm32_e407.h
+ * @brief   GINPUT Touch low level driver source for the ADS7843 on an Olimex STM32E407.
+ *
+ * @defgroup Mouse Mouse
+ * @ingroup GINPUT
+ * @{
+ */
+
+#ifndef _GINPUT_LLD_MOUSE_BOARD_H
+#define _GINPUT_LLD_MOUSE_BOARD_H
+
+static const SPIConfig spicfg = { 
+    NULL,
+	GPIOC,
+    4,
+    /* SPI_CR1_BR_2 |*/ SPI_CR1_BR_1 | SPI_CR1_BR_0,
+};
+
+/**
+ * @brief   Initialise the board for the touch.
+ *
+ * @notapi
+ */
+static inline void init_board(void) {
+	spiStart(&SPID2, &spicfg);
+}
+
+/**
+ * @brief   Check whether the surface is currently touched
+ * @return	TRUE if the surface is currently touched
+ *
+ * @notapi
+ */
+static inline bool_t getpin_pressed(void) {
+	return (!palReadPad(GPIOC, 5));
+}
+/**
+ * @brief   Aquire the bus ready for readings
+ *
+ * @notapi
+ */
+static inline void aquire_bus(void) {
+	spiAcquireBus(&SPID2);
+    //TOUCHSCREEN_SPI_PROLOGUE();
+    palClearPad(GPIOC, 4);
+}
+
+/**
+ * @brief   Release the bus after readings
+ *
+ * @notapi
+ */
+static inline void release_bus(void) {
+	palSetPad(GPIOC, 4);
+	spiReleaseBus(&SPID2);
+    //TOUCHSCREEN_SPI_EPILOGUE();
+}
+
+/**
+ * @brief   Read a value from touch controller
+ * @return	The value read from the controller
+ *
+ * params[in] port	The controller port to read.
+ *
+ * @notapi
+ */
+static inline uint16_t read_value(uint16_t port) {
+    static uint8_t txbuf[3] = {0};
+    static uint8_t rxbuf[3] = {0};
+    uint16_t ret;
+
+    txbuf[0] = port;
+
+    spiExchange(&SPID2, 3, txbuf, rxbuf);
+
+    ret = (rxbuf[1] << 5) | (rxbuf[2] >> 3); 
+    
+	return ret;
+}
+
+#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
+/** @} */
diff --git a/boards/addons/ginput/touch/FT5x06/ginput_lld_mouse_board_marlin.h b/boards/addons/ginput/touch/FT5x06/ginput_lld_mouse_board_marlin.h
new file mode 100644
index 00000000..e3e18c24
--- /dev/null
+++ b/boards/addons/ginput/touch/FT5x06/ginput_lld_mouse_board_marlin.h
@@ -0,0 +1,111 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/ginput/touch/FT5x06/ginput_lld_mouse_board_marlin.h
+ * @brief   GINPUT Touch low level driver source for the FT5x06.
+ *
+ * @defgroup Mouse Mouse
+ * @ingroup GINPUT
+ * @{
+ */
+
+#ifndef _GINPUT_LLD_MOUSE_BOARD_H
+#define _GINPUT_LLD_MOUSE_BOARD_H
+
+/* I2C interface #2 - Touchscreen controller */
+static const I2CConfig i2ccfg2 = {
+    OPMODE_I2C,
+    400000,
+    FAST_DUTY_CYCLE_2,
+};
+
+/**
+ * @brief   Initialise the board for the touch.
+ *
+ * @notapi
+ */
+static void init_board(void) {
+
+}
+
+
+/**
+ * @brief	Write a value into a certain register
+ *
+ * @param[in] reg	The register address
+ * @param[in] n		The amount of bytes (one or two)
+ * @param[in] val	The value
+ *
+ * @notapi
+ */
+static void write_reg(uint8_t reg, uint8_t n, uint16_t val) {
+	uint8_t txbuf[3];
+
+	i2cAcquireBus(&I2CD2);
+
+	txbuf[0] = reg;
+
+	if (n == 1) {
+		txbuf[1] = val;
+		i2cMasterTransmitTimeout(&I2CD2, FT5x06_ADDR, txbuf, 2, NULL, 0, MS2ST(FT5x06_TIMEOUT));
+	} else if (n == 2) {
+		txbuf[1] = ((val & 0xFF00) >> 8);
+		txbuf[2] = (val & 0x00FF);
+		i2cMasterTransmitTimeout(&I2CD2, FT5x06_ADDR, txbuf, 3, NULL, 0, MS2ST(FT5x06_TIMEOUT));
+	}
+	
+	i2cReleaseBus(&I2CD2);
+}
+ 
+/**
+ * @brief	Read the value of a certain register
+ *
+ * @param[in] reg	The register address
+ * @param[in] n		The amount of bytes (one or two)
+ *
+ * @return Data read from device (one byte or two depending on n param)
+ *
+ * @notapi
+ */
+static uint16_t read_reg(uint8_t reg, uint8_t n) {
+	uint8_t txbuf[1], rxbuf[2];
+	uint16_t ret;
+
+	rxbuf[0] = 0;
+	rxbuf[1] = 0;
+
+	i2cAcquireBus(&I2CD2);
+
+	txbuf[0] = reg;
+	i2cMasterTransmitTimeout(&I2CD2, FT5x06_ADDR, txbuf, 1, rxbuf, n, MS2ST(FT5x06_TIMEOUT));
+
+	if (n == 1) {
+		ret = rxbuf[0];
+	} else if (n == 2) {
+		ret = ((rxbuf[0] << 8) | (rxbuf[1] & 0xFF));
+	}
+
+	i2cReleaseBus(&I2CD2);
+
+	return ret;
+}
+
+static void read_reg_n(uint8_t reg, uint8_t n, uint8_t *rxbuf) {
+	uint8_t txbuf[1];
+
+	i2cAcquireBus(&I2CD2);
+
+	txbuf[0] = reg;
+	i2cMasterTransmitTimeout(&I2CD2, FT5x06_ADDR, txbuf, 1, rxbuf, n, MS2ST(FT5x06_TIMEOUT));
+
+	i2cReleaseBus(&I2CD2);
+}
+
+#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
+/** @} */
+
diff --git a/boards/addons/ginput/touch/MCU/ginput_lld_mouse_board_olimex_pic32mx_lcd.h b/boards/addons/ginput/touch/MCU/ginput_lld_mouse_board_olimex_pic32mx_lcd.h
new file mode 100644
index 00000000..a7435c95
--- /dev/null
+++ b/boards/addons/ginput/touch/MCU/ginput_lld_mouse_board_olimex_pic32mx_lcd.h
@@ -0,0 +1,151 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/ginput/touch/MCU/ginput_lld_mouse_board_olimex_stm32_lcd.h
+ * @brief   GINPUT Touch low level driver source for the MCU on the example board.
+ *
+ * @defgroup Mouse Mouse
+ * @ingroup GINPUT
+ *
+ * @{
+ */
+
+#ifndef _GINPUT_LLD_MOUSE_BOARD_H
+#define _GINPUT_LLD_MOUSE_BOARD_H
+
+static const ADCConfig ADCC = {
+  .vref = ADC_VREF_CFG_AVDD_AVSS,
+  .stime = 15,
+  .irq = EIC_IRQ_ADC,
+  .base = _ADC10_BASE_ADDRESS,
+};
+static struct ADCDriver ADCD;
+
+#define YNEG 13 // U
+#define XNEG 15 // R
+#define XPOS 12 // L
+#define YPOS 11 // D
+
+#define ADC_MAX 1023
+
+#define TOUCH_THRESHOULD 50
+
+static const ADCConversionGroup ADC_X_CG = {
+  .circular = FALSE,
+  .num_channels = 1,
+  .channels = 1 << XNEG,
+};
+
+static const ADCConversionGroup ADC_Y_CG = {
+  .circular = FALSE,
+  .num_channels = 1,
+  .channels = 1 << YPOS,
+};
+
+/**
+ * @brief   Initialise the board for the touch.
+ *
+ * @notapi
+ */
+static inline void init_board(void) {
+  adcObjectInit(&ADCD);
+  adcStart(&ADCD, &ADCC);
+}
+
+/**
+ * @brief   Check whether the surface is currently touched
+ * @return	TRUE if the surface is currently touched
+ *
+ * @notapi
+ */
+static inline bool_t getpin_pressed(void) {
+  adcsample_t samples[2] = {0, };
+
+  // Set X+ to ground
+  palSetPadMode(IOPORTB, XPOS, PAL_MODE_OUTPUT);
+  palClearPad(IOPORTB, XPOS);
+
+  // Set Y- to VCC
+  palSetPadMode(IOPORTB, YNEG, PAL_MODE_OUTPUT);
+  palSetPad(IOPORTB, YNEG);
+
+  palSetPadMode(IOPORTB, XNEG, PAL_MODE_INPUT_ANALOG);
+  palSetPadMode(IOPORTB, YPOS, PAL_MODE_INPUT_ANALOG);
+
+  adcConvert(&ADCD, &ADC_X_CG, &samples[0], 1);
+  adcConvert(&ADCD, &ADC_Y_CG, &samples[1], 1);
+
+  return (ADC_MAX - (samples[1] - samples[0])) > TOUCH_THRESHOULD;
+}
+
+/**
+ * @brief   Aquire the bus ready for readings
+ *
+ * @notapi
+ */
+static inline void aquire_bus(void) {
+}
+
+/**
+ * @brief   Release the bus after readings
+ *
+ * @notapi
+ */
+static inline void release_bus(void) {
+}
+
+/**
+ * @brief   Read an x value from touch controller
+ * @return	The value read from the controller
+ *
+ * @notapi
+ */
+static inline uint16_t read_x_value(void) {
+  adcsample_t sample;
+
+  palSetPadMode(IOPORTB, XPOS, PAL_MODE_OUTPUT);
+  palSetPad(IOPORTB, XPOS);
+
+  palSetPadMode(IOPORTB, XNEG, PAL_MODE_OUTPUT);
+  palClearPad(IOPORTB, XNEG);
+
+  palSetPadMode(IOPORTB, YNEG, PAL_MODE_INPUT);
+
+  palSetPadMode(IOPORTB, YPOS, PAL_MODE_INPUT_ANALOG);
+
+  adcConvert(&ADCD, &ADC_Y_CG, &sample, 1);
+
+  return ADC_MAX - sample;
+}
+
+/**
+ * @brief   Read an y value from touch controller
+ * @return	The value read from the controller
+ *
+ * @notapi
+ */
+static inline uint16_t read_y_value(void) {
+  adcsample_t sample;
+
+  palSetPadMode(IOPORTB, YNEG, PAL_MODE_OUTPUT);
+  palClearPad(IOPORTB, YNEG);
+
+  palSetPadMode(IOPORTB, YPOS, PAL_MODE_OUTPUT);
+  palSetPad(IOPORTB, YPOS);
+
+  palSetPadMode(IOPORTB, XPOS, PAL_MODE_INPUT);
+
+  palSetPadMode(IOPORTB, XNEG, PAL_MODE_INPUT_ANALOG);
+
+  adcConvert(&ADCD, &ADC_X_CG, &sample, 1);
+
+  return ADC_MAX - sample;
+}
+
+#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
+/** @} */
diff --git a/boards/addons/ginput/touch/MCU/ginput_lld_mouse_board_olimex_stm32_lcd.h b/boards/addons/ginput/touch/MCU/ginput_lld_mouse_board_olimex_stm32_lcd.h
new file mode 100644
index 00000000..ca177a89
--- /dev/null
+++ b/boards/addons/ginput/touch/MCU/ginput_lld_mouse_board_olimex_stm32_lcd.h
@@ -0,0 +1,152 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/ginput/touch/MCU/ginput_lld_mouse_board_olimex_stm32_lcd.h
+ * @brief   GINPUT Touch low level driver source for the MCU on the example board.
+ *
+ * @defgroup Mouse Mouse
+ * @ingroup GINPUT
+ *
+ * @{
+ */
+
+#ifndef _GINPUT_LLD_MOUSE_BOARD_H
+#define _GINPUT_LLD_MOUSE_BOARD_H
+
+#define ADC_NUM_CHANNELS   2
+#define ADC_BUF_DEPTH      1
+
+static const ADCConversionGroup adc_y_config = { 
+    FALSE,
+    ADC_NUM_CHANNELS,
+    NULL,
+    NULL,
+    0, 0,    
+    0, 0,    
+    ADC_SQR1_NUM_CH(ADC_NUM_CHANNELS),
+    0,    
+    ADC_SQR3_SQ2_N(ADC_CHANNEL_IN12) | ADC_SQR3_SQ1_N(ADC_CHANNEL_IN13)
+};
+
+static const ADCConversionGroup adc_x_config = { 
+    FALSE,
+    ADC_NUM_CHANNELS,
+    NULL,
+    NULL,
+    0, 0,
+    0, 0,
+    ADC_SQR1_NUM_CH(ADC_NUM_CHANNELS),
+    0,  
+    ADC_SQR3_SQ2_N(ADC_CHANNEL_IN10) | ADC_SQR3_SQ1_N(ADC_CHANNEL_IN11)
+};
+
+/**
+ * @brief   Initialise the board for the touch.
+ *
+ * @notapi
+ */
+static inline void init_board(void) {
+	adcStart(&ADCD1, NULL);
+}
+
+/**
+ * @brief   Check whether the surface is currently touched
+ * @return	TRUE if the surface is currently touched
+ *
+ * @notapi
+ */
+static inline bool_t getpin_pressed(void) {
+    palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_PULLDOWN);
+    palSetPadMode(GPIOC, 1, PAL_MODE_INPUT);
+    palSetPadMode(GPIOC, 2, PAL_MODE_INPUT);
+    palSetPadMode(GPIOC, 3, PAL_MODE_OUTPUT_PUSHPULL);
+    palSetPad(GPIOC, 3);
+	
+	return palReadPad(GPIOC, 0);
+}
+
+/**
+ * @brief   Aquire the bus ready for readings
+ *
+ * @notapi
+ */
+static inline void aquire_bus(void) {
+
+}
+
+/**
+ * @brief   Release the bus after readings
+ *
+ * @notapi
+ */
+static inline void release_bus(void) {
+
+}
+
+/**
+ * @brief   Read an x value from touch controller
+ * @return	The value read from the controller
+ *
+ * @notapi
+ */
+static inline uint16_t read_x_value(void) {
+	uint16_t val1, val2;
+    adcsample_t samples[ADC_NUM_CHANNELS * ADC_BUF_DEPTH];
+
+    palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_ANALOG);
+    palSetPadMode(GPIOC, 1, PAL_MODE_INPUT_ANALOG);
+    palSetPadMode(GPIOC, 2, PAL_MODE_OUTPUT_PUSHPULL);
+    palSetPadMode(GPIOC, 3, PAL_MODE_OUTPUT_PUSHPULL);
+    
+	palSetPad(GPIOC, 2);
+    palClearPad(GPIOC, 3); 
+    gfxSleepMilliseconds(1);
+    adcConvert(&ADCD1, &adc_x_config, samples, ADC_BUF_DEPTH);  
+    val1 = ((samples[0] + samples[1])/2);
+    
+	palClearPad(GPIOC, 2);
+    palSetPad(GPIOC, 3);
+    gfxSleepMilliseconds(1);
+    adcConvert(&ADCD1, &adc_x_config, samples, ADC_BUF_DEPTH);
+    val2 = ((samples[0] + samples[1])/2);
+    
+	return ((val1+((1<<12)-val2))/4);
+}
+
+/**
+ * @brief   Read an y value from touch controller
+ * @return	The value read from the controller
+ *
+ * @notapi
+ */
+static inline uint16_t read_y_value(void) {
+	uint16_t val1, val2;
+    adcsample_t samples[ADC_NUM_CHANNELS * ADC_BUF_DEPTH];
+
+    palSetPadMode(GPIOC, 2, PAL_MODE_INPUT_ANALOG);
+    palSetPadMode(GPIOC, 3, PAL_MODE_INPUT_ANALOG);
+    palSetPadMode(GPIOC, 0, PAL_MODE_OUTPUT_PUSHPULL);
+    palSetPadMode(GPIOC, 1, PAL_MODE_OUTPUT_PUSHPULL);
+
+    palSetPad(GPIOC, 1);
+    palClearPad(GPIOC, 0);
+    gfxSleepMilliseconds(1);
+    adcConvert(&ADCD1, &adc_y_config, samples, ADC_BUF_DEPTH);
+    val1 = ((samples[0] + samples[1])/2);
+
+    palClearPad(GPIOC, 1);
+    palSetPad(GPIOC, 0);
+    gfxSleepMilliseconds(1);
+    adcConvert(&ADCD1, &adc_y_config, samples, ADC_BUF_DEPTH);
+    val2 = ((samples[0] + samples[1])/2);
+    
+	return ((val1+((1<<12)-val2))/4);
+}
+
+#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
+/** @} */
diff --git a/boards/addons/ginput/touch/STMPE811/ginput_lld_mouse_board_embest_dmstf4bb.h b/boards/addons/ginput/touch/STMPE811/ginput_lld_mouse_board_embest_dmstf4bb.h
new file mode 100644
index 00000000..a2d38d34
--- /dev/null
+++ b/boards/addons/ginput/touch/STMPE811/ginput_lld_mouse_board_embest_dmstf4bb.h
@@ -0,0 +1,126 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/ginput/touch/STMPE811/ginput_lld_mouse_board_embest_dmstf4bb.h
+ * @brief   GINPUT Touch low level driver source for the STMPE811 on the Embest DM-STF4BB board.
+ *
+ * @defgroup Mouse Mouse
+ * @ingroup GINPUT
+ * @{
+ */
+
+#ifndef _GINPUT_LLD_MOUSE_BOARD_H
+#define _GINPUT_LLD_MOUSE_BOARD_H
+
+static const I2CConfig i2ccfg = {
+	OPMODE_I2C,
+	400000,
+	FAST_DUTY_CYCLE_2,
+};
+
+/**
+ * @brief   Initialise the board for the touch.
+ *
+ * @notapi
+ */
+static void init_board(void)
+{
+	palSetPadMode(GPIOC, 13, PAL_MODE_INPUT | PAL_STM32_PUDR_FLOATING);			/* TP IRQ */
+	palSetPadMode(GPIOB, 8, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN);	/* SCL */
+	palSetPadMode(GPIOB, 9, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN);	/* SDA */
+
+	i2cStart(&I2CD1, &i2ccfg);
+}
+
+/**
+ * @brief   Check whether an interrupt is raised
+ * @return	TRUE if there is an interrupt signal present
+ *
+ * @notapi
+ */
+static inline bool_t getpin_irq(void) {
+	return (!(palReadPad(GPIOC, 13)));
+}
+
+/**
+ * @brief	Write a value into a certain register
+ *
+ * @param[in] reg	The register address
+ * @param[in] n		The amount of bytes (one or two)
+ * @param[in] val	The value
+ *
+ * @notapi
+ */
+static void write_reg(uint8_t reg, uint8_t n, uint16_t val)
+{
+	uint8_t txbuf[3];
+
+	i2cAcquireBus(&I2CD1);
+
+	txbuf[0] = reg;
+
+	if (n == 1) {
+		txbuf[1] = val;
+		i2cMasterTransmitTimeout(&I2CD1, STMPE811_ADDR, txbuf, 2, NULL, 0, MS2ST(STMPE811_TIMEOUT));
+	} else if (n == 2) {
+		txbuf[1] = ((val & 0xFF00) >> 8);
+		txbuf[2] = (val & 0x00FF);
+		i2cMasterTransmitTimeout(&I2CD1, STMPE811_ADDR, txbuf, 3, NULL, 0, MS2ST(STMPE811_TIMEOUT));
+	}
+	
+	i2cReleaseBus(&I2CD1);
+}
+ 
+/**
+ * @brief	Read the value of a certain register
+ *
+ * @param[in] reg	The register address
+ * @param[in] n		The amount of bytes (one or two)
+ *
+ * @return Data read from device (one byte or two depending on n param)
+ *
+ * @notapi
+ */
+static uint16_t read_reg(uint8_t reg, uint8_t n)
+{
+	uint8_t txbuf[1], rxbuf[2];
+	uint16_t ret;
+
+	rxbuf[0] = 0;
+	rxbuf[1] = 0;
+
+	i2cAcquireBus(&I2CD1);
+
+	txbuf[0] = reg;
+	i2cMasterTransmitTimeout(&I2CD1, STMPE811_ADDR, txbuf, 1, rxbuf, n, MS2ST(STMPE811_TIMEOUT));
+
+	if (n == 1) {
+		ret = rxbuf[0];
+	} else if (n == 2) {
+		ret = ((rxbuf[0] << 8) | (rxbuf[1] & 0xFF));
+	}
+
+	i2cReleaseBus(&I2CD1);
+
+	return ret;
+}
+
+static void read_reg_n(uint8_t reg, uint8_t n, uint8_t *rxbuf)
+{
+	uint8_t txbuf[1];
+
+	i2cAcquireBus(&I2CD1);
+
+	txbuf[0] = reg;
+	i2cMasterTransmitTimeout(&I2CD1, STMPE811_ADDR, txbuf, 1, rxbuf, n, MS2ST(STMPE811_TIMEOUT));
+
+	i2cReleaseBus(&I2CD1);
+}
+
+#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
+/** @} */
diff --git a/boards/addons/tdisp/HD44780/tdisp_lld_board_olimex_e407.h b/boards/addons/tdisp/HD44780/tdisp_lld_board_olimex_e407.h
new file mode 100644
index 00000000..12407356
--- /dev/null
+++ b/boards/addons/tdisp/HD44780/tdisp_lld_board_olimex_e407.h
@@ -0,0 +1,59 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/tdisp/HD44780/tdisp_lld_board_olimex_e407.h
+ * @brief   TDISP driver subsystem board interface for the HD44780 display
+ *
+ * @addtogroup TDISP
+ * @{
+ */
+
+#ifndef _TDISP_LLD_BOARD_H
+#define _TDISP_LLD_BOARD_H
+
+/* Configure these to match the hardware connections on your board */
+#define BUS_4BITS	FALSE
+#define PORT_DATA	GPIOG
+#define PORT_CTRL	GPIOE
+#define PIN_RS		0
+#define PIN_RW		1
+#define PIN_EN		2
+
+static void init_board(void) {
+	palSetGroupMode(PORT_CTRL, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
+	palSetGroupMode(PORT_DATA, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
+	palClearPad(PORT_CTRL, PIN_RW);
+}
+
+static void writeToLCD(uint8_t data) {
+	palWritePort(PORT_DATA, data);
+	palSetPad(PORT_CTRL, PIN_EN);
+	gfxSleepMicroseconds(1);
+	palClearPad(PORT_CTRL, PIN_EN);
+	gfxSleepMicroseconds(5);
+}
+
+static void write_cmd(uint8_t data) {
+	palClearPad(PORT_CTRL, PIN_RS);
+	#if BUS_4BITS
+		writeToLCD(data>>4);
+	#endif
+	writeToLCD(data);
+}
+
+static void write_data(uint8_t data) {
+	palSetPad(PORT_CTRL, PIN_RS);
+	#if BUS_4BITS
+		writeToLCD(data>>4);
+	#endif
+	writeToLCD(data);
+}
+
+#endif /* _TDISP_LLD_BOARD_H */
+/** @} */
+
diff --git a/boards/addons/tdisp/HD44780/tdisp_lld_board_st_stm32f4_discovery.h b/boards/addons/tdisp/HD44780/tdisp_lld_board_st_stm32f4_discovery.h
new file mode 100644
index 00000000..43e161f1
--- /dev/null
+++ b/boards/addons/tdisp/HD44780/tdisp_lld_board_st_stm32f4_discovery.h
@@ -0,0 +1,122 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    drivers/tdisp/HD44780/tdisp_lld_board_st_stm32f4_discovery.h
+ * @brief   TDISP driver subsystem board interface for the HD44780 display
+ *
+ * @addtogroup TDISP
+ * @{
+ */
+
+#ifndef _TDISP_LLD_BOARD_H
+#define _TDISP_LLD_BOARD_H
+
+/* Configure these to match the hardware connections on your board */
+#define BUS_4BITS	TRUE
+
+/* Configure the bitoffset in the dataport so they match with the
+ * hardware pins. An offset of 0 means bit0 stays at bit0 of the dataport.
+ * If the offset is set to 3, bit0 of the nibble will be positioned at
+ * P[A..G]3 of the hardware-port.
+ */
+#define hardware_offset	3
+
+/* The port where the data is sent to. In the
+ * low-leveldriver het hardware_offset is taken
+ * into account. If for example the hardware_offset
+ * is set to 3, then de data will be sent to
+ * PE3, PE4, PE5 en PE6, if the dataport where GPIOE.
+ */
+#define PORT_DATA	GPIOE
+
+/* The port used to controle the controle lines of
+ * the display.
+ */
+#define PORT_CTRL	GPIOD
+/* Pin to controle the R/S-line of the display */
+#define PIN_RS		0
+/* Pin to controle the EN-line of the display */
+#define PIN_EN		1
+/* Pin to controle the R/W-pin of the display.
+ * If reading of the display is not used disable
+ * reading in the gfxconf.h and put a dummy value here
+ * as it will not be used.
+ */
+#define PIN_RW		7
+
+
+static void init_board(void) {
+	/* Initialize the ports for data and controle-lines */
+	palSetGroupMode(PORT_CTRL, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
+	palSetGroupMode(PORT_DATA, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
+	/* Set alle controle pins to low */
+	palClearPad(PORT_CTRL, PIN_RS);
+	palClearPad(PORT_CTRL, PIN_EN);
+	#if TDISP_NEED_READ
+	  palClearPad(PORT_CTRL, PIN_RW);
+	#endif
+}
+
+/* This is the low-level routine for sending the bits
+ * to the LCD-display. This routine shifts
+ * the bits so they match the hardware port.
+ */
+static void writeToLCD(uint8_t data) {
+	palWritePort(PORT_DATA, data<<hardware_offset);
+	palSetPad(PORT_CTRL, PIN_EN);
+	gfxSleepMicroseconds(1);
+	palClearPad(PORT_CTRL, PIN_EN);
+	/* wait a little while so that de display can process the data */
+	gfxSleepMicroseconds(5);
+}
+
+/* Writes a command to the display. The
+ * RS-line is pulled low and than the
+ * data is send.
+ */
+static void write_cmd(uint8_t data) {
+	palClearPad(PORT_CTRL, PIN_RS);
+	#if BUS_4BITS
+		/* first send the high-nibble */
+		writeToLCD(data>>4);
+	#endif
+	/* send the low-nibble */
+	#if BUS_4BITS
+		/* in 4-bit mode the high-nibble is zeroed out */
+		writeToLCD(data & 0x0F);
+	#else
+		writeToLCD(data);
+	#endif
+}
+
+// static void write_initcmd(uint8_t data) {
+//   write_cmd(data);
+// }
+
+/* Write data to the display. The
+ * RS-line is pulled high and than the
+ * data is send.
+ */
+static void write_data(uint8_t data) {
+	palSetPad(PORT_CTRL, PIN_RS);
+	#if BUS_4BITS
+		/* first send the high-nibble */
+		writeToLCD(data>>4);
+	#endif
+	/* send the low-nibble */
+	#if BUS_4BITS
+		/* in 4-bit mode the high-nibble is zeroed out */
+		writeToLCD(data & 0x0F);
+	#else
+		writeToLCD(data);
+	#endif
+}
+
+#endif /* _TDISP_LLD_BOARD_H */
+/** @} */
+
diff --git a/boards/base/Linux/board.mk b/boards/base/Linux/board.mk
new file mode 100644
index 00000000..f022947f
--- /dev/null
+++ b/boards/base/Linux/board.mk
@@ -0,0 +1,4 @@
+GFXINC  += $(GFXLIB)/boards/base/Linux
+GFXSRC  +=
+GFXDEFS += -DGFX_USE_OS_LINUX=TRUE
+include $(GFXLIB)/drivers/multiple/X/gdisp_lld.mk
diff --git a/boards/base/Linux/example/Makefile b/boards/base/Linux/example/Makefile
new file mode 100644
index 00000000..1d59fe43
--- /dev/null
+++ b/boards/base/Linux/example/Makefile
@@ -0,0 +1,153 @@
+#
+#       !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!!
+#
+##############################################################################################
+#
+# On command line:
+#
+# make all = Create project
+#
+# make clean = Clean project files.
+#
+# To rebuild project do "make clean" and "make all".
+#
+
+##############################################################################################
+# Start of default section
+#
+
+TRGT = 
+CC   = $(TRGT)gcc
+AS   = $(TRGT)gcc -x assembler-with-cpp
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS = 
+
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS =
+
+# List all default directories to look for include files here
+DINCDIR =
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS = -lX11 -pthread -lrt
+
+#
+# End of default section
+##############################################################################################
+
+##############################################################################################
+# Start of user section
+#
+
+# Define project name here
+PROJECT = ugfx
+
+# Imported source files and paths for uGFX
+GFXLIB = ../ugfx
+include ${GFXLIB}/gfx.mk
+include ${GFXLIB}/boards/base/Linux/board.mk
+
+# Where is our source code - alter these for your project.
+MYFILES = $(GFXLIB)/demos/modules/gdisp/basics
+MYCSRC  = $(MYFILES)/main.c
+MYDEFS  =
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS = $(MYDEFS) $(GFXDEFS)
+
+# Define ASM defines here
+UADEFS =
+
+# List C source files here
+SRC  = $(GFXSRC) \
+       $(MYCSRC)
+
+# List ASM source files here
+ASRC =
+
+# List all user directories here
+UINCDIR = $(MYFILES) $(GFXINC)
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+# Define optimisation level here
+OPT = -ggdb -O0 -fomit-frame-pointer
+
+#
+# End of user defines
+##############################################################################################
+
+INCDIR  = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR))
+LIBDIR  = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+DEFS    = $(DDEFS) $(UDEFS)
+ADEFS   = $(DADEFS) $(UADEFS)
+OBJS    = $(ASRC:.s=.o) $(SRC:.c=.o)
+LIBS    = $(DLIBS) $(ULIBS)
+
+ASFLAGS = -Wa,-amhls=$(<:.s=.lst) $(ADEFS)
+CPFLAGS = $(OPT) -Wall -Wextra -Wstrict-prototypes -fverbose-asm $(DEFS) 
+
+ifeq ($(HOST_OSX),yes)
+  ifeq ($(OSX_SDK),)
+    OSX_SDK = /Developer/SDKs/MacOSX10.7.sdk
+  endif
+  ifeq ($(OSX_ARCH),)
+    OSX_ARCH = -mmacosx-version-min=10.3 -arch i386
+  endif
+
+  CPFLAGS += -isysroot $(OSX_SDK) $(OSX_ARCH)
+  LDFLAGS = -Wl -Map=$(PROJECT).map,-syslibroot,$(OSX_SDK),$(LIBDIR)
+  LIBS += $(OSX_ARCH)
+else
+  # Linux, or other
+  CPFLAGS += -m32 -Wa,-alms=$(<:.c=.lst)
+  LDFLAGS = -m32 -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR)
+endif
+
+# Generate dependency information
+CPFLAGS += -MD -MP -MF .dep/$(@F).d
+
+#
+# makefile rules
+#
+
+all: $(OBJS) $(PROJECT)
+
+%.o : %.c
+	$(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@
+
+%.o : %.s
+	$(AS) -c $(ASFLAGS) $< -o $@
+
+$(PROJECT): $(OBJS)
+	$(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+
+gcov:
+	-mkdir gcov
+	$(COV) -u $(subst /,\,$(SRC))
+	-mv *.gcov ./gcov
+
+clean:                                      
+	-rm -f $(OBJS)
+	-rm -f $(PROJECT)
+	-rm -f $(PROJECT).map
+	-rm -f $(SRC:.c=.c.bak)
+	-rm -f $(SRC:.c=.lst)
+	-rm -f $(ASRC:.s=.s.bak)
+	-rm -f $(ASRC:.s=.lst)
+	-rm -fR .dep
+
+#
+# Include the dependency files, should be the last of the makefile
+#
+-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
+
+# *** EOF ***
diff --git a/boards/base/Linux/example/readme.txt b/boards/base/Linux/example/readme.txt
new file mode 100644
index 00000000..aff58bb1
--- /dev/null
+++ b/boards/base/Linux/example/readme.txt
@@ -0,0 +1,5 @@
+Copy these files into your own project directory and alter them to suite.
+
+Notes:
+
+1/ Look at the MYFILES definition and the MYCSRC definition.
diff --git a/boards/base/Linux/readme.txt b/boards/base/Linux/readme.txt
new file mode 100644
index 00000000..491c91f5
--- /dev/null
+++ b/boards/base/Linux/readme.txt
@@ -0,0 +1,8 @@
+This directory contains the interface for Linux
+running either native Linux.
+
+On this board uGFX currently supports:
+	- GDISP via the X driver 
+	- GINPUT-touch via the X driver
+
+There is an example Makefile and project in the examples directory.
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.c b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.c
new file mode 100644
index 00000000..7dc6f285
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.c
@@ -0,0 +1,92 @@
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH},
+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+   VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH},
+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH},
+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH}
+};
+#endif
+
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return TRUE;
+}
+
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  return !palReadPad(GPIOD, GPIOD_SD_CD);
+}
+
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* Board has no write protection detection */
+  return FALSE;
+}
+#endif
+
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+
+}
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.h b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.h
new file mode 100644
index 00000000..490c0307
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.h
@@ -0,0 +1,1299 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for mikromedia STM32-M4 board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_MIKROE_MIKROMEDIA_M4
+#define BOARD_NAME                  "mikromedia STM32-M4"
+
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK                32768
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK                16000000
+#endif
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD                   330
+
+/*
+ * MCU type as defined in the ST header file stm32f4xx.h.
+ */
+#define STM32F4XX
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_VSENSE                0
+#define GPIOA_PIN1                  1
+#define GPIOA_PIN2                  2
+#define GPIOA_PIN3                  3
+#define GPIOA_PIN4                  4
+#define GPIOA_PIN5                  5
+#define GPIOA_PIN6                  6
+#define GPIOA_PIN7                  7
+#define GPIOA_PIN8                  8
+#define GPIOA_VBUS_FS               9
+#define GPIOA_PIN10                 10
+#define GPIOA_OTG_FS_DM             11
+#define GPIOA_OTG_FS_DP             12
+#define GPIOA_TMS                   13
+#define GPIOA_TCK                   14
+#define GPIOA_TDI                   15
+
+#define GPIOB_LCD_YD                0
+#define GPIOB_LCD_XL                1
+#define GPIOB_PIN2                  2
+#define GPIOB_TDO                   3
+#define GPIOB_TRST                  4
+#define GPIOB_PIN5                  5
+#define GPIOB_SCL1                  6
+#define GPIOB_SDA1                  7
+#define GPIOB_DRIVEA                8
+#define GPIOB_DRIVEB                9
+#define GPIOB_SCL2                  10
+#define GPIOB_SDA2                  11
+#define GPIOB_PIN12                 12
+#define GPIOB_SCK2                  13
+#define GPIOB_MISO2                 14
+#define GPIOB_MOSI2                 15
+
+#define GPIOC_PIN0                  0
+#define GPIOC_PIN1                  1
+#define GPIOC_PIN2                  2
+#define GPIOC_PIN3                  3
+#define GPIOC_PIN4                  4
+#define GPIOC_PIN5                  5
+#define GPIOC_MP3_DREQ              6
+#define GPIOC_MP3_RST               7
+#define GPIOC_MP3_CS                8
+#define GPIOC_MP3_DCS               9
+#define GPIOC_SCK3                  10
+#define GPIOC_MISO3                 11
+#define GPIOC_MOSI3                 12
+#define GPIOC_STAT                  13
+#define GPIOC_PIN14                 14
+#define GPIOC_PIN15                 15
+
+#define GPIOD_PIN0                  0
+#define GPIOD_PIN1                  1
+#define GPIOD_PIN2                  2
+#define GPIOD_SD_CS                 3
+#define GPIOD_PIN4                  4
+#define GPIOD_TX2                   5
+#define GPIOD_RX2                   6
+#define GPIOD_FLASH_CS              7
+#define GPIOD_PIN8                  8
+#define GPIOD_PIN9                  9
+#define GPIOD_PIN10                 10
+#define GPIOD_PIN11                 11
+#define GPIOD_PIN12                 12
+#define GPIOD_PIN13                 13
+#define GPIOD_PIN14                 14
+#define GPIOD_SD_CD                 15
+
+#define GPIOE_TD0                   0
+#define GPIOE_TD1                   1
+#define GPIOE_TD2                   2
+#define GPIOE_TD3                   3
+#define GPIOE_TD4                   4
+#define GPIOE_TD5                   5
+#define GPIOE_TD6                   6
+#define GPIOE_TD7                   7
+#define GPIOE_LCD_RST               8
+#define GPIOE_LCD_BLED              9
+#define GPIOE_PMRD                  10
+#define GPIOE_PMWR                  11
+#define GPIOE_LCD_RS                12
+#define GPIOE_PIN13                 13
+#define GPIOE_PIN14                 14
+#define GPIOE_LCD_CS                15
+
+#define GPIOF_PIN0                  0
+#define GPIOF_PIN1                  1
+#define GPIOF_PIN2                  2
+#define GPIOF_PIN3                  3
+#define GPIOF_PIN4                  4
+#define GPIOF_PIN5                  5
+#define GPIOF_PIN6                  6
+#define GPIOF_PIN7                  7
+#define GPIOF_PIN8                  8
+#define GPIOF_PIN9                  9
+#define GPIOF_PIN10                 10
+#define GPIOF_PIN11                 11
+#define GPIOF_PIN12                 12
+#define GPIOF_PIN13                 13
+#define GPIOF_PIN14                 14
+#define GPIOF_PIN15                 15
+
+#define GPIOG_PIN0                  0
+#define GPIOG_PIN1                  1
+#define GPIOG_PIN2                  2
+#define GPIOG_PIN3                  3
+#define GPIOG_PIN4                  4
+#define GPIOG_PIN5                  5
+#define GPIOG_PIN6                  6
+#define GPIOG_PIN7                  7
+#define GPIOG_PIN8                  8
+#define GPIOG_PIN9                  9
+#define GPIOG_PIN10                 10
+#define GPIOG_PIN11                 11
+#define GPIOG_PIN12                 12
+#define GPIOG_PIN13                 13
+#define GPIOG_PIN14                 14
+#define GPIOG_PIN15                 15
+
+#define GPIOH_OSC_IN                0
+#define GPIOH_OSC_OUT               1
+#define GPIOH_PIN2                  2
+#define GPIOH_PIN3                  3
+#define GPIOH_PIN4                  4
+#define GPIOH_PIN5                  5
+#define GPIOH_PIN6                  6
+#define GPIOH_PIN7                  7
+#define GPIOH_PIN8                  8
+#define GPIOH_PIN9                  9
+#define GPIOH_PIN10                 10
+#define GPIOH_PIN11                 11
+#define GPIOH_PIN12                 12
+#define GPIOH_PIN13                 13
+#define GPIOH_PIN14                 14
+#define GPIOH_PIN15                 15
+
+#define GPIOI_PIN0                  0
+#define GPIOI_PIN1                  1
+#define GPIOI_PIN2                  2
+#define GPIOI_PIN3                  3
+#define GPIOI_PIN4                  4
+#define GPIOI_PIN5                  5
+#define GPIOI_PIN6                  6
+#define GPIOI_PIN7                  7
+#define GPIOI_PIN8                  8
+#define GPIOI_PIN9                  9
+#define GPIOI_PIN10                 10
+#define GPIOI_PIN11                 11
+#define GPIOI_PIN12                 12
+#define GPIOI_PIN13                 13
+#define GPIOI_PIN14                 14
+#define GPIOI_PIN15                 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2))
+#define PIN_ODR_LOW(n)              (0U << (n))
+#define PIN_ODR_HIGH(n)             (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_2M(n)            (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n)           (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n)           (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n)          (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v)           ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0  - VSENSE                    (analog).
+ * PA1  - PIN1                      (input pullup).
+ * PA2  - PIN2                      (input pullup).
+ * PA3  - PIN3                      (input pullup).
+ * PA4  - PIN4                      (alternate 6).
+ * PA5  - PIN5                      (alternate 5).
+ * PA6  - PIN6                      (alternate 5).
+ * PA7  - PIN7                      (alternate 5).
+ * PA8  - PIN8                      (input pullup).
+ * PA9  - VBUS_FS                   (input floating).
+ * PA10 - PIN10                     (input floating).
+ * PA11 - OTG_FS_DM                 (alternate 10).
+ * PA12 - OTG_FS_DP                 (alternate 10).
+ * PA13 - TMS                       (alternate 0).
+ * PA14 - TCK                       (alternate 0).
+ * PA15 - TDI                       (input pullup).
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_ANALOG(GPIOA_VSENSE) |        \
+                                     PIN_MODE_INPUT(GPIOA_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN3) |           \
+                                     PIN_MODE_ALTERNATE(GPIOA_PIN4) |       \
+                                     PIN_MODE_ALTERNATE(GPIOA_PIN5) |       \
+                                     PIN_MODE_ALTERNATE(GPIOA_PIN6) |       \
+                                     PIN_MODE_ALTERNATE(GPIOA_PIN7) |       \
+                                     PIN_MODE_INPUT(GPIOA_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOA_VBUS_FS) |        \
+                                     PIN_MODE_INPUT(GPIOA_PIN10) |          \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_TMS) |        \
+                                     PIN_MODE_ALTERNATE(GPIOA_TCK) |        \
+                                     PIN_MODE_INPUT(GPIOA_TDI))
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_VSENSE) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_TMS) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_TCK) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_TDI))
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_100M(GPIOA_VSENSE) |        \
+                                     PIN_OSPEED_100M(GPIOA_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN4) |          \
+                                     PIN_OSPEED_50M(GPIOA_PIN5) |           \
+                                     PIN_OSPEED_50M(GPIOA_PIN6) |           \
+                                     PIN_OSPEED_50M(GPIOA_PIN7) |           \
+                                     PIN_OSPEED_100M(GPIOA_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOA_VBUS_FS) |       \
+                                     PIN_OSPEED_100M(GPIOA_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_DM) |     \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_DP) |     \
+                                     PIN_OSPEED_100M(GPIOA_TMS) |           \
+                                     PIN_OSPEED_100M(GPIOA_TCK) |           \
+                                     PIN_OSPEED_100M(GPIOA_TDI))
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_FLOATING(GPIOA_VSENSE) |     \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN3) |         \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN7) |       \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN8) |         \
+                                     PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) |    \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_TMS) |        \
+                                     PIN_PUPDR_FLOATING(GPIOA_TCK) |        \
+                                     PIN_PUPDR_PULLUP(GPIOA_TDI))
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_VSENSE) |           \
+                                     PIN_ODR_HIGH(GPIOA_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOA_VBUS_FS) |          \
+                                     PIN_ODR_HIGH(GPIOA_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DM) |        \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DP) |        \
+                                     PIN_ODR_HIGH(GPIOA_TMS) |              \
+                                     PIN_ODR_HIGH(GPIOA_TCK) |              \
+                                     PIN_ODR_HIGH(GPIOA_TDI))
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_VSENSE, 0) |         \
+                                     PIN_AFIO_AF(GPIOA_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN4, 6) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN5, 5) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN6, 5) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN7, 5))
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_VBUS_FS, 0) |        \
+                                     PIN_AFIO_AF(GPIOA_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) |     \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) |     \
+                                     PIN_AFIO_AF(GPIOA_TMS, 0) |            \
+                                     PIN_AFIO_AF(GPIOA_TCK, 0) |            \
+                                     PIN_AFIO_AF(GPIOA_TDI, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0  - LCD_YD                    (analog).
+ * PB1  - LCD_XL                    (analog).
+ * PB2  - PIN2                      (input pullup).
+ * PB3  - TDO                       (alternate 0).
+ * PB4  - TRST                      (input pullup).
+ * PB5  - PIN5                      (input pullup).
+ * PB6  - SCL1                      (alternate 4).
+ * PB7  - SDA1                      (input pullup).
+ * PB8  - DRIVEA                    (output pushpull maximum).
+ * PB9  - DRIVEB                    (output opendrain maximum).
+ * PB10 - SCL2                      (input pullup).
+ * PB11 - SDA2                      (input pullup).
+ * PB12 - PIN12                     (input pullup).
+ * PB13 - SCK2                      (input pullup).
+ * PB14 - MISO2                     (input pullup).
+ * PB15 - MOSI2                     (input pullup).
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_ANALOG(GPIOB_LCD_YD) |        \
+                                     PIN_MODE_ANALOG(GPIOB_LCD_XL) |        \
+                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_TDO) |        \
+                                     PIN_MODE_INPUT(GPIOB_TRST) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN5) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_SCL1) |       \
+                                     PIN_MODE_INPUT(GPIOB_SDA1) |           \
+                                     PIN_MODE_OUTPUT(GPIOB_DRIVEA) |        \
+                                     PIN_MODE_OUTPUT(GPIOB_DRIVEB) |        \
+                                     PIN_MODE_INPUT(GPIOB_SCL2) |           \
+                                     PIN_MODE_INPUT(GPIOB_SDA2) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOB_SCK2) |           \
+                                     PIN_MODE_INPUT(GPIOB_MISO2) |          \
+                                     PIN_MODE_INPUT(GPIOB_MOSI2))
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_LCD_YD) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_LCD_XL) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_TDO) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_TRST) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |       \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_SCL1) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_SDA1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_DRIVEA) |     \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_DRIVEB) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_SCL2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_SDA2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_SCK2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_MISO2) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_MOSI2))
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_100M(GPIOB_LCD_YD) |        \
+                                     PIN_OSPEED_100M(GPIOB_LCD_XL) |        \
+                                     PIN_OSPEED_100M(GPIOB_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOB_TDO) |           \
+                                     PIN_OSPEED_100M(GPIOB_TRST) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOB_SCL1) |          \
+                                     PIN_OSPEED_100M(GPIOB_SDA1) |          \
+                                     PIN_OSPEED_100M(GPIOB_DRIVEA) |        \
+                                     PIN_OSPEED_100M(GPIOB_DRIVEB) |        \
+                                     PIN_OSPEED_100M(GPIOB_SCL2) |          \
+                                     PIN_OSPEED_100M(GPIOB_SDA2) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOB_SCK2) |          \
+                                     PIN_OSPEED_100M(GPIOB_MISO2) |         \
+                                     PIN_OSPEED_100M(GPIOB_MOSI2))
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_FLOATING(GPIOB_LCD_YD) |     \
+                                     PIN_PUPDR_FLOATING(GPIOB_LCD_XL) |     \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_TDO) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_TRST) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_SCL1) |       \
+                                     PIN_PUPDR_PULLUP(GPIOB_SDA1) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_DRIVEA) |     \
+                                     PIN_PUPDR_FLOATING(GPIOB_DRIVEB) |     \
+                                     PIN_PUPDR_PULLUP(GPIOB_SCL2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_SDA2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_SCK2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_MISO2) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_MOSI2))
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_LCD_YD) |           \
+                                     PIN_ODR_HIGH(GPIOB_LCD_XL) |           \
+                                     PIN_ODR_HIGH(GPIOB_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOB_TDO) |              \
+                                     PIN_ODR_HIGH(GPIOB_TRST) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOB_SCL1) |             \
+                                     PIN_ODR_HIGH(GPIOB_SDA1) |             \
+                                     PIN_ODR_HIGH(GPIOB_DRIVEA) |           \
+                                     PIN_ODR_HIGH(GPIOB_DRIVEB) |           \
+                                     PIN_ODR_HIGH(GPIOB_SCL2) |             \
+                                     PIN_ODR_HIGH(GPIOB_SDA2) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOB_SCK2) |             \
+                                     PIN_ODR_HIGH(GPIOB_MISO2) |            \
+                                     PIN_ODR_HIGH(GPIOB_MOSI2))
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_LCD_YD, 0) |         \
+                                     PIN_AFIO_AF(GPIOB_LCD_XL, 0) |         \
+                                     PIN_AFIO_AF(GPIOB_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_TDO, 0) |            \
+                                     PIN_AFIO_AF(GPIOB_TRST, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_SCL1, 4) |           \
+                                     PIN_AFIO_AF(GPIOB_SDA1, 4))
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_DRIVEA, 0) |         \
+                                     PIN_AFIO_AF(GPIOB_DRIVEB, 0) |         \
+                                     PIN_AFIO_AF(GPIOB_SCL2, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_SDA2, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_SCK2, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_MISO2, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_MOSI2, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0  - PIN0                      (output pushpull maximum).
+ * PC1  - PIN1                      (input pullup).
+ * PC2  - PIN2                      (input pullup).
+ * PC3  - PIN3                      (input pullup).
+ * PC4  - PIN4                      (input pullup).
+ * PC5  - PIN5                      (input pullup).
+ * PC6  - MP3_DREQ                  (input pullup).
+ * PC7  - MP3_RST                   (alternate 6).
+ * PC8  - MP3_CS                    (output pushpull maximum).
+ * PC9  - MP3_DCS                   (input pullup).
+ * PC10 - SCK3                      (alternate 6).
+ * PC11 - MISO3                     (alternate 6).
+ * PC12 - MOSI3                     (alternate 6).
+ * PC13 - STAT                      (input pullup).
+ * PC14 - PIN14                     (input pullup).
+ * PC15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOC_MODER             (PIN_MODE_OUTPUT(GPIOC_PIN0) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOC_MP3_DREQ) |       \
+                                     PIN_MODE_ALTERNATE(GPIOC_MP3_RST) |    \
+                                     PIN_MODE_OUTPUT(GPIOC_MP3_CS) |        \
+                                     PIN_MODE_INPUT(GPIOC_MP3_DCS) |        \
+                                     PIN_MODE_ALTERNATE(GPIOC_SCK3) |       \
+                                     PIN_MODE_ALTERNATE(GPIOC_MISO3) |      \
+                                     PIN_MODE_ALTERNATE(GPIOC_MOSI3) |      \
+                                     PIN_MODE_INPUT(GPIOC_STAT) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN15))
+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_MP3_DREQ) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_MP3_RST) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_MP3_CS) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_MP3_DCS) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SCK3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_MISO3) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_MOSI3) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_STAT) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_100M(GPIOC_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOC_MP3_DREQ) |      \
+                                     PIN_OSPEED_100M(GPIOC_MP3_RST) |       \
+                                     PIN_OSPEED_100M(GPIOC_MP3_CS) |        \
+                                     PIN_OSPEED_100M(GPIOC_MP3_DCS) |       \
+                                     PIN_OSPEED_100M(GPIOC_SCK3) |          \
+                                     PIN_OSPEED_100M(GPIOC_MISO3) |         \
+                                     PIN_OSPEED_100M(GPIOC_MOSI3) |         \
+                                     PIN_OSPEED_100M(GPIOC_STAT) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOC_PIN15))
+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_FLOATING(GPIOC_PIN0) |       \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_MP3_DREQ) |     \
+                                     PIN_PUPDR_FLOATING(GPIOC_MP3_RST) |    \
+                                     PIN_PUPDR_PULLUP(GPIOC_MP3_CS) |       \
+                                     PIN_PUPDR_PULLUP(GPIOC_MP3_DCS) |      \
+                                     PIN_PUPDR_FLOATING(GPIOC_SCK3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOC_MISO3) |      \
+                                     PIN_PUPDR_FLOATING(GPIOC_MOSI3) |      \
+                                     PIN_PUPDR_PULLUP(GPIOC_STAT) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN15))
+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOC_MP3_DREQ) |         \
+                                     PIN_ODR_HIGH(GPIOC_MP3_RST) |          \
+                                     PIN_ODR_HIGH(GPIOC_MP3_CS) |           \
+                                     PIN_ODR_HIGH(GPIOC_MP3_DCS) |          \
+                                     PIN_ODR_HIGH(GPIOC_SCK3) |             \
+                                     PIN_ODR_HIGH(GPIOC_MISO3) |            \
+                                     PIN_ODR_HIGH(GPIOC_MOSI3) |            \
+                                     PIN_ODR_HIGH(GPIOC_STAT) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN15))
+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_MP3_DREQ, 0) |       \
+                                     PIN_AFIO_AF(GPIOC_MP3_RST, 6))
+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_MP3_CS, 0) |         \
+                                     PIN_AFIO_AF(GPIOC_MP3_DCS, 0) |        \
+                                     PIN_AFIO_AF(GPIOC_SCK3, 6) |           \
+                                     PIN_AFIO_AF(GPIOC_MISO3, 6) |          \
+                                     PIN_AFIO_AF(GPIOC_MOSI3, 6) |          \
+                                     PIN_AFIO_AF(GPIOC_STAT, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN15, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0  - PIN0                      (input pullup).
+ * PD1  - PIN1                      (input pullup).
+ * PD2  - PIN2                      (input pullup).
+ * PD3  - SD_CS                     (output pushpull maximum).
+ * PD4  - PIN4                      (output pushpull maximum).
+ * PD5  - TX2                       (alternate 7).
+ * PD6  - RX2                       (alternate 7).
+ * PD7  - FLASH_CS                  (output pushpull maximum).
+ * PD8  - PIN8                      (input pullup).
+ * PD9  - PIN9                      (input pullup).
+ * PD10 - PIN10                     (input pullup).
+ * PD11 - PIN11                     (input pullup).
+ * PD12 - PIN12                     (output pushpull maximum).
+ * PD13 - PIN13                     (output pushpull maximum).
+ * PD14 - PIN14                     (output pushpull maximum).
+ * PD15 - SD_CD                     (output pushpull maximum).
+ */
+#define VAL_GPIOD_MODER             (PIN_MODE_INPUT(GPIOD_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN2) |           \
+                                     PIN_MODE_OUTPUT(GPIOD_SD_CS) |         \
+                                     PIN_MODE_OUTPUT(GPIOD_PIN4) |          \
+                                     PIN_MODE_ALTERNATE(GPIOD_TX2) |        \
+                                     PIN_MODE_ALTERNATE(GPIOD_RX2) |        \
+                                     PIN_MODE_OUTPUT(GPIOD_FLASH_CS) |      \
+                                     PIN_MODE_INPUT(GPIOD_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN11) |          \
+                                     PIN_MODE_OUTPUT(GPIOD_PIN12) |         \
+                                     PIN_MODE_OUTPUT(GPIOD_PIN13) |         \
+                                     PIN_MODE_OUTPUT(GPIOD_PIN14) |         \
+                                     PIN_MODE_INPUT(GPIOD_SD_CD))
+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_SD_CS) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_TX2) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_RX2) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_FLASH_CS) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_SD_CD))
+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_100M(GPIOD_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOD_SD_CS) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOD_TX2) |           \
+                                     PIN_OSPEED_100M(GPIOD_RX2) |           \
+                                     PIN_OSPEED_100M(GPIOD_FLASH_CS) |      \
+                                     PIN_OSPEED_100M(GPIOD_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOD_SD_CD))
+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_PULLUP(GPIOD_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN2) |         \
+                                     PIN_PUPDR_FLOATING(GPIOD_SD_CS) |        \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOD_TX2) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_RX2) |          \
+                                     PIN_PUPDR_PULLUP(GPIOD_FLASH_CS) |     \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN11) |        \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN14) |      \
+                                     PIN_PUPDR_PULLUP(GPIOD_SD_CD))
+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOD_SD_CS) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOD_TX2) |              \
+                                     PIN_ODR_HIGH(GPIOD_RX2) |              \
+                                     PIN_ODR_HIGH(GPIOD_FLASH_CS) |         \
+                                     PIN_ODR_HIGH(GPIOD_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN11) |            \
+                                     PIN_ODR_LOW(GPIOD_PIN12) |             \
+                                     PIN_ODR_LOW(GPIOD_PIN13) |             \
+                                     PIN_ODR_LOW(GPIOD_PIN14) |             \
+                                     PIN_ODR_LOW(GPIOD_SD_CD))
+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_SD_CS, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_TX2, 7) |            \
+                                     PIN_AFIO_AF(GPIOD_RX2, 7) |            \
+                                     PIN_AFIO_AF(GPIOD_FLASH_CS, 0))
+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_SD_CD, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0  - TD0                       (output pushpull maximum).
+ * PE1  - TD1                       (output pushpull maximum).
+ * PE2  - TD2                       (output pushpull maximum).
+ * PE3  - TD3                       (output pushpull maximum).
+ * PE4  - TD4                       (output pushpull maximum).
+ * PE5  - TD5                       (output pushpull maximum).
+ * PE6  - TD6                       (output pushpull maximum).
+ * PE7  - TD7                       (output pushpull maximum).
+ * PE8  - LCD_RST                   (output pushpull maximum).
+ * PE9  - LCD_BLED                  (output pushpull maximum).
+ * PE10 - PMRD                      (output pushpull maximum).
+ * PE11 - PMWR                      (output pushpull maximum).
+ * PE12 - LCD_RS                    (output pushpull maximum).
+ * PE13 - PIN13                     (input floating).
+ * PE14 - PIN14                     (input floating).
+ * PE15 - LCD_CS                    (output pushpull maximum).
+ */
+#define VAL_GPIOE_MODER             (PIN_MODE_OUTPUT(GPIOE_TD0) |           \
+                                     PIN_MODE_OUTPUT(GPIOE_TD1) |           \
+                                     PIN_MODE_OUTPUT(GPIOE_TD2) |           \
+                                     PIN_MODE_OUTPUT(GPIOE_TD3) |           \
+                                     PIN_MODE_OUTPUT(GPIOE_TD4) |           \
+                                     PIN_MODE_OUTPUT(GPIOE_TD5) |           \
+                                     PIN_MODE_OUTPUT(GPIOE_TD6) |           \
+                                     PIN_MODE_OUTPUT(GPIOE_TD7) |           \
+                                     PIN_MODE_OUTPUT(GPIOE_LCD_RST) |       \
+                                     PIN_MODE_OUTPUT(GPIOE_LCD_BLED) |      \
+                                     PIN_MODE_OUTPUT(GPIOE_PMRD) |          \
+                                     PIN_MODE_OUTPUT(GPIOE_PMWR) |          \
+                                     PIN_MODE_OUTPUT(GPIOE_LCD_RS) |        \
+                                     PIN_MODE_INPUT(GPIOE_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN14) |          \
+                                     PIN_MODE_OUTPUT(GPIOE_LCD_CS))
+#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_TD0) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_TD1) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_TD2) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_TD3) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_TD4) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_TD5) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_TD6) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_TD7) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LCD_RST) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LCD_BLED) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PMRD) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PMWR) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LCD_RS) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LCD_CS))
+#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_100M(GPIOE_TD0) |           \
+                                     PIN_OSPEED_100M(GPIOE_TD1) |           \
+                                     PIN_OSPEED_100M(GPIOE_TD2) |           \
+                                     PIN_OSPEED_100M(GPIOE_TD3) |           \
+                                     PIN_OSPEED_100M(GPIOE_TD4) |           \
+                                     PIN_OSPEED_100M(GPIOE_TD5) |           \
+                                     PIN_OSPEED_100M(GPIOE_TD6) |           \
+                                     PIN_OSPEED_100M(GPIOE_TD7) |           \
+                                     PIN_OSPEED_100M(GPIOE_LCD_RST) |       \
+                                     PIN_OSPEED_100M(GPIOE_LCD_BLED) |      \
+                                     PIN_OSPEED_100M(GPIOE_PMRD) |          \
+                                     PIN_OSPEED_100M(GPIOE_PMWR) |          \
+                                     PIN_OSPEED_100M(GPIOE_LCD_RS) |        \
+                                     PIN_OSPEED_100M(GPIOE_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOE_LCD_CS))
+#define VAL_GPIOE_PUPDR             (PIN_PUPDR_FLOATING(GPIOE_TD0) |        \
+                                     PIN_PUPDR_FLOATING(GPIOE_TD1) |        \
+                                     PIN_PUPDR_FLOATING(GPIOE_TD2) |        \
+                                     PIN_PUPDR_FLOATING(GPIOE_TD3) |        \
+                                     PIN_PUPDR_FLOATING(GPIOE_TD4) |        \
+                                     PIN_PUPDR_FLOATING(GPIOE_TD5) |        \
+                                     PIN_PUPDR_FLOATING(GPIOE_TD6) |        \
+                                     PIN_PUPDR_FLOATING(GPIOE_TD7) |        \
+                                     PIN_PUPDR_FLOATING(GPIOE_LCD_RST) |    \
+                                     PIN_PUPDR_FLOATING(GPIOE_LCD_BLED) |   \
+                                     PIN_PUPDR_FLOATING(GPIOE_PMRD) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PMWR) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_LCD_RS) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOE_LCD_CS))
+#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_TD0) |              \
+                                     PIN_ODR_HIGH(GPIOE_TD1) |              \
+                                     PIN_ODR_HIGH(GPIOE_TD2) |              \
+                                     PIN_ODR_HIGH(GPIOE_TD3) |              \
+                                     PIN_ODR_HIGH(GPIOE_TD4) |              \
+                                     PIN_ODR_HIGH(GPIOE_TD5) |              \
+                                     PIN_ODR_HIGH(GPIOE_TD6) |              \
+                                     PIN_ODR_HIGH(GPIOE_TD7) |              \
+                                     PIN_ODR_HIGH(GPIOE_LCD_RST) |          \
+                                     PIN_ODR_LOW(GPIOE_LCD_BLED) |          \
+                                     PIN_ODR_HIGH(GPIOE_PMRD) |             \
+                                     PIN_ODR_HIGH(GPIOE_PMWR) |             \
+                                     PIN_ODR_HIGH(GPIOE_LCD_RS) |           \
+                                     PIN_ODR_HIGH(GPIOE_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN14) |            \
+                                     PIN_ODR_LOW(GPIOE_LCD_CS))
+#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_TD0, 0) |            \
+                                     PIN_AFIO_AF(GPIOE_TD1, 0) |            \
+                                     PIN_AFIO_AF(GPIOE_TD2, 0) |            \
+                                     PIN_AFIO_AF(GPIOE_TD3, 0) |            \
+                                     PIN_AFIO_AF(GPIOE_TD4, 0) |            \
+                                     PIN_AFIO_AF(GPIOE_TD5, 0) |            \
+                                     PIN_AFIO_AF(GPIOE_TD6, 0) |            \
+                                     PIN_AFIO_AF(GPIOE_TD7, 0))
+#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_LCD_RST, 0) |        \
+                                     PIN_AFIO_AF(GPIOE_LCD_BLED, 0) |       \
+                                     PIN_AFIO_AF(GPIOE_PMRD, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PMWR, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_LCD_RS, 0) |         \
+                                     PIN_AFIO_AF(GPIOE_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_LCD_CS, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0  - PIN0                      (input floating).
+ * PF1  - PIN1                      (input floating).
+ * PF2  - PIN2                      (input floating).
+ * PF3  - PIN3                      (input floating).
+ * PF4  - PIN4                      (input floating).
+ * PF5  - PIN5                      (input floating).
+ * PF6  - PIN6                      (input floating).
+ * PF7  - PIN7                      (input floating).
+ * PF8  - PIN8                      (input floating).
+ * PF9  - PIN9                      (input floating).
+ * PF10 - PIN10                     (input floating).
+ * PF11 - PIN11                     (input floating).
+ * PF12 - PIN12                     (input floating).
+ * PF13 - PIN13                     (input floating).
+ * PF14 - PIN14                     (input floating).
+ * PF15 - PIN15                     (input floating).
+ */
+#define VAL_GPIOF_MODER             (PIN_MODE_INPUT(GPIOF_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_100M(GPIOF_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR             (PIN_PUPDR_FLOATING(GPIOF_PIN0) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN15))
+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0  - PIN0                      (input floating).
+ * PG1  - PIN1                      (input floating).
+ * PG2  - PIN2                      (input floating).
+ * PG3  - PIN3                      (input floating).
+ * PG4  - PIN4                      (input floating).
+ * PG5  - PIN5                      (input floating).
+ * PG6  - PIN6                      (input floating).
+ * PG7  - PIN7                      (input floating).
+ * PG8  - PIN8                      (input floating).
+ * PG9  - PIN9                      (input floating).
+ * PG10 - PIN10                     (input floating).
+ * PG11 - PIN11                     (input floating).
+ * PG12 - PIN12                     (input floating).
+ * PG13 - PIN13                     (input floating).
+ * PG14 - PIN14                     (input floating).
+ * PG15 - PIN15                     (input floating).
+ */
+#define VAL_GPIOG_MODER             (PIN_MODE_INPUT(GPIOG_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR           (PIN_OSPEED_100M(GPIOG_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR             (PIN_PUPDR_FLOATING(GPIOG_PIN0) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN15))
+#define VAL_GPIOG_ODR               (PIN_ODR_HIGH(GPIOG_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL              (PIN_AFIO_AF(GPIOG_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN7, 0))
+#define VAL_GPIOG_AFRH              (PIN_AFIO_AF(GPIOG_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN15, 0))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0  - OSC_IN                    (input floating).
+ * PH1  - OSC_OUT                   (input floating).
+ * PH2  - PIN2                      (input floating).
+ * PH3  - PIN3                      (input floating).
+ * PH4  - PIN4                      (input floating).
+ * PH5  - PIN5                      (input floating).
+ * PH6  - PIN6                      (input floating).
+ * PH7  - PIN7                      (input floating).
+ * PH8  - PIN8                      (input floating).
+ * PH9  - PIN9                      (input floating).
+ * PH10 - PIN10                     (input floating).
+ * PH11 - PIN11                     (input floating).
+ * PH12 - PIN12                     (input floating).
+ * PH13 - PIN13                     (input floating).
+ * PH14 - PIN14                     (input floating).
+ * PH15 - PIN15                     (input floating).
+ */
+#define VAL_GPIOH_MODER             (PIN_MODE_INPUT(GPIOH_OSC_IN) |         \
+                                     PIN_MODE_INPUT(GPIOH_OSC_OUT) |        \
+                                     PIN_MODE_INPUT(GPIOH_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR           (PIN_OSPEED_100M(GPIOH_OSC_IN) |        \
+                                     PIN_OSPEED_100M(GPIOH_OSC_OUT) |       \
+                                     PIN_OSPEED_100M(GPIOH_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR             (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) |     \
+                                     PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) |    \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN15))
+#define VAL_GPIOH_ODR               (PIN_ODR_HIGH(GPIOH_OSC_IN) |           \
+                                     PIN_ODR_HIGH(GPIOH_OSC_OUT) |          \
+                                     PIN_ODR_HIGH(GPIOH_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL              (PIN_AFIO_AF(GPIOH_OSC_IN, 0) |         \
+                                     PIN_AFIO_AF(GPIOH_OSC_OUT, 0) |        \
+                                     PIN_AFIO_AF(GPIOH_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN7, 0))
+#define VAL_GPIOH_AFRH              (PIN_AFIO_AF(GPIOH_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN15, 0))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0  - PIN0                      (input floating).
+ * PI1  - PIN1                      (input floating).
+ * PI2  - PIN2                      (input floating).
+ * PI3  - PIN3                      (input floating).
+ * PI4  - PIN4                      (input floating).
+ * PI5  - PIN5                      (input floating).
+ * PI6  - PIN6                      (input floating).
+ * PI7  - PIN7                      (input floating).
+ * PI8  - PIN8                      (input floating).
+ * PI9  - PIN9                      (input floating).
+ * PI10 - PIN10                     (input floating).
+ * PI11 - PIN11                     (input floating).
+ * PI12 - PIN12                     (input floating).
+ * PI13 - PIN13                     (input floating).
+ * PI14 - PIN14                     (input floating).
+ * PI15 - PIN15                     (input floating).
+ */
+#define VAL_GPIOI_MODER             (PIN_MODE_INPUT(GPIOI_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR           (PIN_OSPEED_100M(GPIOI_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR             (PIN_PUPDR_FLOATING(GPIOI_PIN0) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN15))
+#define VAL_GPIOI_ODR               (PIN_ODR_HIGH(GPIOI_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL              (PIN_AFIO_AF(GPIOI_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN7, 0))
+#define VAL_GPIOI_AFRH              (PIN_AFIO_AF(GPIOI_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.mk b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.mk
new file mode 100644
index 00000000..d6a45638
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.mk
@@ -0,0 +1,7 @@
+# Required include directories
+BOARDINC = $(GFXLIB)/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board
+
+# List of all the board related files.
+BOARDSRC = $(BOARDINC)/board.c \
+			$(BOARDINC)/flash_memory.c
+
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board_orig.h b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board_orig.h
new file mode 100644
index 00000000..e4d2c31f
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board_orig.h
@@ -0,0 +1,1303 @@
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Mikroe mikromedia STM32-M4.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_MIKROMEDIA_STM32_M4
+#define BOARD_NAME                  "mikromedia STM32-M4"
+
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK                32768
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK                16000000
+#endif
+
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD                   330
+
+/*
+ * MCU type as defined in the ST header file stm32f4xx.h.
+ */
+#define STM32F4XX
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_VSENSE                0
+#define GPIOA_PIN1                  1
+#define GPIOA_PIN2                  2
+#define GPIOA_PIN3                  3
+#define GPIOA_PIN4                  4
+#define GPIOA_PIN5                  5
+#define GPIOA_PIN6                  6
+#define GPIOA_PIN7                  7
+#define GPIOA_PIN8                  8
+#define GPIOA_VBUS_FS               9
+#define GPIOA_PIN10                 10
+#define GPIOA_OTG_FS_DM             11
+#define GPIOA_OTG_FS_DP             12
+#define GPIOA_TMS                   13
+#define GPIOA_TCK                   14
+#define GPIOA_TDI                   15
+
+#define GPIOB_LCD_YD                0
+#define GPIOB_LCD_XL                1
+#define GPIOB_PIN2                  2
+#define GPIOB_TDO                   3
+#define GPIOB_TRST                  4
+#define GPIOB_PIN5                  5
+#define GPIOB_SCL1                  6
+#define GPIOB_SDA1                  7
+#define GPIOB_DRIVEA                8
+#define GPIOB_DRIVEB                9
+#define GPIOB_SCL2                  10
+#define GPIOB_SDA2                  11
+#define GPIOB_PIN12                 12
+#define GPIOB_SCK2                  13
+#define GPIOB_MISO2                 14
+#define GPIOB_MOSI2                 15
+
+#define GPIOC_PIN0                  0
+#define GPIOC_PIN1                  1
+#define GPIOC_PIN2                  2
+#define GPIOC_PIN3                  3
+#define GPIOC_PIN4                  4
+#define GPIOC_PIN5                  5
+#define GPIOC_MP3_DREQ              6
+#define GPIOC_MP3_RST               7
+#define GPIOC_MP3_CS                8
+#define GPIOC_MP3_DCS               9
+#define GPIOC_SCL3                  10
+#define GPIOC_MISO3                 11
+#define GPIOC_MOSI3                 12
+#define GPIOC_STAT                  13
+#define GPIOC_OSC32_IN              14
+#define GPIOC_OSC32_OUT             15
+
+#define GPIOD_PIN0                  0
+#define GPIOD_PIN1                  1
+#define GPIOD_PIN2                  2
+#define GPIOD_SD_CS                 3
+#define GPIOD_PIN4                  4
+#define GPIOD_TX2                   5
+#define GPIOD_RX2                   6
+#define GPIOD_FLASH_CS              7
+#define GPIOD_PIN8                  8
+#define GPIOD_PIN9                  9
+#define GPIOD_PIN10                 10
+#define GPIOD_PIN11                 11
+#define GPIOD_PIN12                 12
+#define GPIOD_PIN13                 13
+#define GPIOD_PIN14                 14
+#define GPIOD_SD_CD                 15
+
+// DONE TO HERE
+
+#define GPIOE_TD0                   0
+#define GPIOE_TD1                   1
+#define GPIOE_TD2                   2
+#define GPIOE_TD3                   3
+#define GPIOE_TD4                   4
+#define GPIOE_TD5                   5
+#define GPIOE_TD6                   6
+#define GPIOE_TD7                   7
+#define GPIOE_LCD_RST               8
+#define GPIOE_LCD_BLED              9
+#define GPIOE_PMRD                  10
+#define GPIOE_PMWR                  11
+#define GPIOE_LCD_RS                12
+#define GPIOE_PIN13                 13
+#define GPIOE_PIN14                 14
+#define GPIOE_LCD_CS                15
+
+#define GPIOF_PIN0                  0
+#define GPIOF_PIN1                  1
+#define GPIOF_PIN2                  2
+#define GPIOF_PIN3                  3
+#define GPIOF_PIN4                  4
+#define GPIOF_PIN5                  5
+#define GPIOF_PIN6                  6
+#define GPIOF_PIN7                  7
+#define GPIOF_PIN8                  8
+#define GPIOF_PIN9                  9
+#define GPIOF_PIN10                 10
+#define GPIOF_PIN11                 11
+#define GPIOF_PIN12                 12
+#define GPIOF_PIN13                 13
+#define GPIOF_PIN14                 14
+#define GPIOF_PIN15                 15
+
+#define GPIOG_PIN0                  0
+#define GPIOG_PIN1                  1
+#define GPIOG_PIN2                  2
+#define GPIOG_PIN3                  3
+#define GPIOG_PIN4                  4
+#define GPIOG_PIN5                  5
+#define GPIOG_PIN6                  6
+#define GPIOG_PIN7                  7
+#define GPIOG_PIN8                  8
+#define GPIOG_PIN9                  9
+#define GPIOG_PIN10                 10
+#define GPIOG_PIN11                 11
+#define GPIOG_PIN12                 12
+#define GPIOG_PIN13                 13
+#define GPIOG_PIN14                 14
+#define GPIOG_PIN15                 15
+
+#define GPIOH_OSC_IN                0
+#define GPIOH_OSC_OUT               1
+#define GPIOH_PIN2                  2
+#define GPIOH_PIN3                  3
+#define GPIOH_PIN4                  4
+#define GPIOH_PIN5                  5
+#define GPIOH_PIN6                  6
+#define GPIOH_PIN7                  7
+#define GPIOH_PIN8                  8
+#define GPIOH_PIN9                  9
+#define GPIOH_PIN10                 10
+#define GPIOH_PIN11                 11
+#define GPIOH_PIN12                 12
+#define GPIOH_PIN13                 13
+#define GPIOH_PIN14                 14
+#define GPIOH_PIN15                 15
+
+#define GPIOI_PIN0                  0
+#define GPIOI_PIN1                  1
+#define GPIOI_PIN2                  2
+#define GPIOI_PIN3                  3
+#define GPIOI_PIN4                  4
+#define GPIOI_PIN5                  5
+#define GPIOI_PIN6                  6
+#define GPIOI_PIN7                  7
+#define GPIOI_PIN8                  8
+#define GPIOI_PIN9                  9
+#define GPIOI_PIN10                 10
+#define GPIOI_PIN11                 11
+#define GPIOI_PIN12                 12
+#define GPIOI_PIN13                 13
+#define GPIOI_PIN14                 14
+#define GPIOI_PIN15                 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2))
+#define PIN_ODR_LOW(n)              (0U << (n))
+#define PIN_ODR_HIGH(n)             (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_2M(n)            (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n)           (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n)           (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n)          (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v)           ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - Battery Voltage Sense      (Analog)
+ * PA0  - BUTTON                    (input floating).
+#define GPIOA_VSENSE                0
+#define GPIOA_PIN1                  1
+#define GPIOA_PIN2                  2
+#define GPIOA_PIN3                  3
+#define GPIOA_PIN4                  4
+#define GPIOA_PIN5                  5
+#define GPIOA_PIN6                  6
+#define GPIOA_PIN7                  7
+#define GPIOA_PIN8                  8
+#define GPIOA_VBUS_FS               9
+#define GPIOA_PIN10                 10
+#define GPIOA_OTG_FS_DM             11
+#define GPIOA_OTG_FS_DP             12
+#define GPIOA_TMS                   13
+#define GPIOA_TCK                   14
+#define GPIOA_TDI                   15
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_ANALOG(GPIOA_VSENSE) |        \
+                                     PIN_MODE_INPUT(GPIOA_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOA_VBUS_FS) |        \
+                                     PIN_MODE_INPUT(GPIOA_PIN10) |          \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_TMS) |        \
+                                     PIN_MODE_ALTERNATE(GPIOA_TCK) |        \
+                                     PIN_MODE_ALTERNATE(GPIOA_TDI))
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_VSENSE) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_TMS) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_TCK) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_TDI))
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_100M(GPIOA_VSENSE) |        \
+                                     PIN_OSPEED_100M(GPIOA_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOA_VBUS_FS) |       \
+                                     PIN_OSPEED_100M(GPIOA_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_DM) |     \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_DP) |     \
+                                     PIN_OSPEED_100M(GPIOA_TMS) |           \
+                                     PIN_OSPEED_100M(GPIOA_TCK) |           \
+                                     PIN_OSPEED_100M(GPIOA_TDI))
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_FLOATING(GPIOA_VSENSE) |     \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN8) |         \
+                                     PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) |    \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN10) |        \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_TMS) |        \
+                                     PIN_PUPDR_FLOATING(GPIOA_TCK) |        \
+                                     PIN_PUPDR_FLOATING(GPIOA_TDI))
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_VSENSE) |           \
+                                     PIN_ODR_HIGH(GPIOA_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOA_VBUS_FS) |          \
+                                     PIN_ODR_HIGH(GPIOA_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DM) |        \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DP) |        \
+                                     PIN_ODR_HIGH(GPIOA_TMS) |              \
+                                     PIN_ODR_HIGH(GPIOA_TCK) |              \
+                                     PIN_ODR_HIGH(GPIOA_TDI))
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_VSENSE, 0) |         \
+                                     PIN_AFIO_AF(GPIOA_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN7, 0))
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_VBUS_FS, 0) |        \
+                                     PIN_AFIO_AF(GPIOA_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) |     \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) |     \
+                                     PIN_AFIO_AF(GPIOA_TMS, 0) |            \
+                                     PIN_AFIO_AF(GPIOA_TCK, 0) |            \
+                                     PIN_AFIO_AF(GPIOA_TDI, 0))
+// DONE TO HERE
+/*
+ * GPIOB setup:
+ *
+ * PB0  - PIN0                      (input pullup).
+ * PB1  - PIN1                      (input pullup).
+ * PB2  - PIN2                      (input pullup).
+ * PB3  - SWO                       (alternate 0).
+ * PB4  - PIN4                      (input pullup).
+ * PB5  - PIN5                      (input pullup).
+ * PB6  - SCL                       (alternate 4).
+ * PB7  - PIN7                      (input pullup).
+ * PB8  - PIN8                      (input pullup).
+ * PB9  - SDA                       (alternate 4).
+ * PB10 - CLK_IN                    (input pullup).
+ * PB11 - PIN11                     (input pullup).
+ * PB12 - PIN12                     (input pullup).
+ * PB13 - PIN13                     (input pullup).
+ * PB14 - PIN14                     (input pullup).
+ * PB15 - PIN15                     (input pullup).
+
+#define GPIOB_LCD_YD                0
+#define GPIOB_LCD_XL                1
+
+#define GPIOB_TDO                   3
+#define GPIOB_TRST                  4
+#define GPIOB_PIN5                  5
+#define GPIOB_SCL1                  6
+#define GPIOB_SDA1                  7
+#define GPIOB_DRIVEA                8
+#define GPIOB_DRIVEB                9
+#define GPIOB_SCL2                  10
+#define GPIOB_SDA2                  11
+#define GPIOB_PIN12                 12
+#define GPIOB_SCK2                  13
+#define GPIOB_MISO2                 14
+#define GPIOB_MOSI2                 15
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_INPUT(GPIOB_LCD_YD) |           \
+                                     PIN_MODE_INPUT(GPIOB_LCD_XL) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_TDO) |        \
+                                     PIN_MODE_ALTERNATE(GPIOB_TRST) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN5) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_SCL1) |        \
+                                     PIN_MODE_ALTERNATE(GPIOB_SDA1) |        \
+                                     PIN_MODE_INPUT(GPIOB_DRIVEA) |           \
+                                     PIN_MODE_INPUT(GPIOB_DRIVEB) |        \
+                                     PIN_MODE_ALTERNATE(GPIOB_SCL2) |        \
+                                     PIN_MODE_ALTERNATE(GPIOB_SDA2) |        \
+                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \
+                                     PIN_MODE_ALTERNATE(GPIOB_SCK2) |          \
+                                     PIN_MODE_ALTERNATE(GPIOB_MISO2) |          \
+                                     PIN_MODE_ALTERNATE(GPIOB_MOSI2))
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_LCD_YD) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_LCD_XL) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_TDO) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_TRST) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |       \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_SCL1) |       \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_SDA1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_DRIVEA) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_DRIVEB) |       \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_SCL2) |     \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_SDA2) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_SCK2 ) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_MISO2) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_MOSI2))
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_100M(GPIOB_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOB_SWO) |           \
+                                     PIN_OSPEED_100M(GPIOB_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOB_SCL) |           \
+                                     PIN_OSPEED_100M(GPIOB_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOB_SDA) |           \
+                                     PIN_OSPEED_100M(GPIOB_CLK_IN) |        \
+                                     PIN_OSPEED_100M(GPIOB_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOB_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOB_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOB_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_PULLUP(GPIOB_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_SWO) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_SCL) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN8) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_SDA) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_CLK_IN) |       \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOB_SWO) |              \
+                                     PIN_ODR_HIGH(GPIOB_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOB_SCL) |              \
+                                     PIN_ODR_HIGH(GPIOB_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOB_SDA) |              \
+                                     PIN_ODR_HIGH(GPIOB_CLK_IN) |           \
+                                     PIN_ODR_HIGH(GPIOB_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_SWO, 0) |            \
+                                     PIN_AFIO_AF(GPIOB_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_SCL, 4) |            \
+                                     PIN_AFIO_AF(GPIOB_PIN7, 0))
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_SDA, 4) |            \
+                                     PIN_AFIO_AF(GPIOB_CLK_IN, 0) |         \
+                                     PIN_AFIO_AF(GPIOB_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN15, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0  - OTG_FS_POWER_ON           (output pushpull maximum).
+ * PC1  - PIN1                      (input pullup).
+ * PC2  - PIN2                      (input pullup).
+ * PC3  - PDM_OUT                   (input pullup).
+ * PC4  - PIN4                      (input pullup).
+ * PC5  - PIN5                      (input pullup).
+ * PC6  - PIN6                      (input pullup).
+ * PC7  - MCLK                      (alternate 6).
+ * PC8  - PIN8                      (input pullup).
+ * PC9  - PIN9                      (input pullup).
+ * PC10 - SCLK                      (alternate 6).
+ * PC11 - PIN11                     (input pullup).
+ * PC12 - SDIN                      (alternate 6).
+ * PC13 - PIN13                     (input pullup).
+ * PC14 - PIN14                     (input pullup).
+ * PC15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOC_MODER             (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) |\
+                                     PIN_MODE_INPUT(GPIOC_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOC_PDM_OUT) |        \
+                                     PIN_MODE_INPUT(GPIOC_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN6) |           \
+                                     PIN_MODE_ALTERNATE(GPIOC_MCLK) |       \
+                                     PIN_MODE_INPUT(GPIOC_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN9) |           \
+                                     PIN_MODE_ALTERNATE(GPIOC_SCLK) |       \
+                                     PIN_MODE_INPUT(GPIOC_PIN11) |          \
+                                     PIN_MODE_ALTERNATE(GPIOC_SDIN) |       \
+                                     PIN_MODE_INPUT(GPIOC_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN15))
+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_OTG_FS_POWER_ON) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PDM_OUT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_MCLK) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SCLK) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SDIN) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_100M(GPIOC_OTG_FS_POWER_ON) |\
+                                     PIN_OSPEED_100M(GPIOC_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOC_PDM_OUT) |       \
+                                     PIN_OSPEED_100M(GPIOC_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOC_MCLK) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOC_SCLK) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOC_SDIN) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOC_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOC_PIN15))
+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_FLOATING(GPIOC_OTG_FS_POWER_ON) |\
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PDM_OUT) |      \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN6) |         \
+                                     PIN_PUPDR_FLOATING(GPIOC_MCLK) |       \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN9) |         \
+                                     PIN_PUPDR_FLOATING(GPIOC_SCLK) |       \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN11) |        \
+                                     PIN_PUPDR_FLOATING(GPIOC_SDIN) |       \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN15))
+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_OTG_FS_POWER_ON) |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOC_PDM_OUT) |          \
+                                     PIN_ODR_HIGH(GPIOC_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOC_MCLK) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOC_SCLK) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOC_SDIN) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN15))
+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0) |\
+                                     PIN_AFIO_AF(GPIOC_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PDM_OUT, 0) |        \
+                                     PIN_AFIO_AF(GPIOC_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_MCLK, 6))
+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_SCLK, 6) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_SDIN, 6) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN15, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0  - PIN0                      (input pullup).
+ * PD1  - PIN1                      (input pullup).
+ * PD2  - PIN2                      (input pullup).
+ * PD3  - PIN3                      (input pullup).
+ * PD4  - RESET                     (output pushpull maximum).
+ * PD5  - OVER_CURRENT              (input floating).
+ * PD6  - PIN6                      (input pullup).
+ * PD7  - PIN7                      (input pullup).
+ * PD8  - PIN8                      (input pullup).
+ * PD9  - PIN9                      (input pullup).
+ * PD10 - PIN10                     (input pullup).
+ * PD11 - PIN11                     (input pullup).
+ * PD12 - LED4                      (output pushpull maximum).
+ * PD13 - LED3                      (output pushpull maximum).
+ * PD14 - LED5                      (output pushpull maximum).
+ * PD15 - LED6                      (output pushpull maximum).
+ */
+#define VAL_GPIOD_MODER             (PIN_MODE_INPUT(GPIOD_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN3) |           \
+                                     PIN_MODE_OUTPUT(GPIOD_RESET) |         \
+                                     PIN_MODE_INPUT(GPIOD_OVER_CURRENT) |   \
+                                     PIN_MODE_INPUT(GPIOD_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN11) |          \
+                                     PIN_MODE_OUTPUT(GPIOD_LED4) |          \
+                                     PIN_MODE_OUTPUT(GPIOD_LED3) |          \
+                                     PIN_MODE_OUTPUT(GPIOD_LED5) |          \
+                                     PIN_MODE_OUTPUT(GPIOD_LED6))
+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_RESET) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_OVER_CURRENT) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_LED4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_LED3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_LED5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_LED6))
+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_100M(GPIOD_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOD_RESET) |         \
+                                     PIN_OSPEED_100M(GPIOD_OVER_CURRENT) |  \
+                                     PIN_OSPEED_100M(GPIOD_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOD_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOD_LED4) |          \
+                                     PIN_OSPEED_100M(GPIOD_LED3) |          \
+                                     PIN_OSPEED_100M(GPIOD_LED5) |          \
+                                     PIN_OSPEED_100M(GPIOD_LED6))
+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_PULLUP(GPIOD_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN3) |         \
+                                     PIN_PUPDR_FLOATING(GPIOD_RESET) |      \
+                                     PIN_PUPDR_FLOATING(GPIOD_OVER_CURRENT) |\
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN11) |        \
+                                     PIN_PUPDR_FLOATING(GPIOD_LED4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOD_LED3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOD_LED5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOD_LED6))
+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOD_RESET) |            \
+                                     PIN_ODR_HIGH(GPIOD_OVER_CURRENT) |     \
+                                     PIN_ODR_HIGH(GPIOD_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN11) |            \
+                                     PIN_ODR_LOW(GPIOD_LED4) |              \
+                                     PIN_ODR_LOW(GPIOD_LED3) |              \
+                                     PIN_ODR_LOW(GPIOD_LED5) |              \
+                                     PIN_ODR_LOW(GPIOD_LED6))
+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_RESET, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_OVER_CURRENT, 0) |   \
+                                     PIN_AFIO_AF(GPIOD_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_LED4, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_LED3, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_LED5, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_LED6, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0  - INT1                      (input floating).
+ * PE1  - INT2                      (input floating).
+ * PE2  - PIN2                      (input floating).
+ * PE3  - CS_SPI                    (output pushpull maximum).
+ * PE4  - PIN4                      (input floating).
+ * PE5  - PIN5                      (input floating).
+ * PE6  - PIN6                      (input floating).
+ * PE7  - PIN7                      (input floating).
+ * PE8  - PIN8                      (input floating).
+ * PE9  - PIN9                      (input floating).
+ * PE10 - PIN10                     (input floating).
+ * PE11 - PIN11                     (input floating).
+ * PE12 - PIN12                     (input floating).
+ * PE13 - PIN13                     (input floating).
+ * PE14 - PIN14                     (input floating).
+ * PE15 - PIN15                     (input floating).
+ */
+#define VAL_GPIOE_MODER             (PIN_MODE_INPUT(GPIOE_INT1) |           \
+                                     PIN_MODE_INPUT(GPIOE_INT2) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN2) |           \
+                                     PIN_MODE_OUTPUT(GPIOE_CS_SPI) |        \
+                                     PIN_MODE_INPUT(GPIOE_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_INT1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_INT2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_CS_SPI) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_100M(GPIOE_INT1) |          \
+                                     PIN_OSPEED_100M(GPIOE_INT2) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOE_CS_SPI) |        \
+                                     PIN_OSPEED_100M(GPIOE_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR             (PIN_PUPDR_FLOATING(GPIOE_INT1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_INT2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_CS_SPI) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN15))
+#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_INT1) |             \
+                                     PIN_ODR_HIGH(GPIOE_INT2) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOE_CS_SPI) |           \
+                                     PIN_ODR_HIGH(GPIOE_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_INT1, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_INT2, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_CS_SPI, 0) |         \
+                                     PIN_AFIO_AF(GPIOE_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN7, 0))
+#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN15, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0  - PIN0                      (input floating).
+ * PF1  - PIN1                      (input floating).
+ * PF2  - PIN2                      (input floating).
+ * PF3  - PIN3                      (input floating).
+ * PF4  - PIN4                      (input floating).
+ * PF5  - PIN5                      (input floating).
+ * PF6  - PIN6                      (input floating).
+ * PF7  - PIN7                      (input floating).
+ * PF8  - PIN8                      (input floating).
+ * PF9  - PIN9                      (input floating).
+ * PF10 - PIN10                     (input floating).
+ * PF11 - PIN11                     (input floating).
+ * PF12 - PIN12                     (input floating).
+ * PF13 - PIN13                     (input floating).
+ * PF14 - PIN14                     (input floating).
+ * PF15 - PIN15                     (input floating).
+ */
+#define VAL_GPIOF_MODER             (PIN_MODE_INPUT(GPIOF_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_100M(GPIOF_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR             (PIN_PUPDR_FLOATING(GPIOF_PIN0) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN15))
+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0  - PIN0                      (input floating).
+ * PG1  - PIN1                      (input floating).
+ * PG2  - PIN2                      (input floating).
+ * PG3  - PIN3                      (input floating).
+ * PG4  - PIN4                      (input floating).
+ * PG5  - PIN5                      (input floating).
+ * PG6  - PIN6                      (input floating).
+ * PG7  - PIN7                      (input floating).
+ * PG8  - PIN8                      (input floating).
+ * PG9  - PIN9                      (input floating).
+ * PG10 - PIN10                     (input floating).
+ * PG11 - PIN11                     (input floating).
+ * PG12 - PIN12                     (input floating).
+ * PG13 - PIN13                     (input floating).
+ * PG14 - PIN14                     (input floating).
+ * PG15 - PIN15                     (input floating).
+ */
+#define VAL_GPIOG_MODER             (PIN_MODE_INPUT(GPIOG_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR           (PIN_OSPEED_100M(GPIOG_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOG_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR             (PIN_PUPDR_FLOATING(GPIOG_PIN0) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN15))
+#define VAL_GPIOG_ODR               (PIN_ODR_HIGH(GPIOG_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL              (PIN_AFIO_AF(GPIOG_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN7, 0))
+#define VAL_GPIOG_AFRH              (PIN_AFIO_AF(GPIOG_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN15, 0))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0  - OSC_IN                    (input floating).
+ * PH1  - OSC_OUT                   (input floating).
+ * PH2  - PIN2                      (input floating).
+ * PH3  - PIN3                      (input floating).
+ * PH4  - PIN4                      (input floating).
+ * PH5  - PIN5                      (input floating).
+ * PH6  - PIN6                      (input floating).
+ * PH7  - PIN7                      (input floating).
+ * PH8  - PIN8                      (input floating).
+ * PH9  - PIN9                      (input floating).
+ * PH10 - PIN10                     (input floating).
+ * PH11 - PIN11                     (input floating).
+ * PH12 - PIN12                     (input floating).
+ * PH13 - PIN13                     (input floating).
+ * PH14 - PIN14                     (input floating).
+ * PH15 - PIN15                     (input floating).
+ */
+#define VAL_GPIOH_MODER             (PIN_MODE_INPUT(GPIOH_OSC_IN) |         \
+                                     PIN_MODE_INPUT(GPIOH_OSC_OUT) |        \
+                                     PIN_MODE_INPUT(GPIOH_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR           (PIN_OSPEED_100M(GPIOH_OSC_IN) |        \
+                                     PIN_OSPEED_100M(GPIOH_OSC_OUT) |       \
+                                     PIN_OSPEED_100M(GPIOH_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR             (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) |     \
+                                     PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) |    \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN15))
+#define VAL_GPIOH_ODR               (PIN_ODR_HIGH(GPIOH_OSC_IN) |           \
+                                     PIN_ODR_HIGH(GPIOH_OSC_OUT) |          \
+                                     PIN_ODR_HIGH(GPIOH_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL              (PIN_AFIO_AF(GPIOH_OSC_IN, 0) |         \
+                                     PIN_AFIO_AF(GPIOH_OSC_OUT, 0) |        \
+                                     PIN_AFIO_AF(GPIOH_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN7, 0))
+#define VAL_GPIOH_AFRH              (PIN_AFIO_AF(GPIOH_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN15, 0))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0  - PIN0                      (input floating).
+ * PI1  - PIN1                      (input floating).
+ * PI2  - PIN2                      (input floating).
+ * PI3  - PIN3                      (input floating).
+ * PI4  - PIN4                      (input floating).
+ * PI5  - PIN5                      (input floating).
+ * PI6  - PIN6                      (input floating).
+ * PI7  - PIN7                      (input floating).
+ * PI8  - PIN8                      (input floating).
+ * PI9  - PIN9                      (input floating).
+ * PI10 - PIN10                     (input floating).
+ * PI11 - PIN11                     (input floating).
+ * PI12 - PIN12                     (input floating).
+ * PI13 - PIN13                     (input floating).
+ * PI14 - PIN14                     (input floating).
+ * PI15 - PIN15                     (input floating).
+ */
+#define VAL_GPIOI_MODER             (PIN_MODE_INPUT(GPIOI_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR           (PIN_OSPEED_100M(GPIOI_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR             (PIN_PUPDR_FLOATING(GPIOI_PIN0) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN15))
+#define VAL_GPIOI_ODR               (PIN_ODR_HIGH(GPIOI_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL              (PIN_AFIO_AF(GPIOI_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN7, 0))
+#define VAL_GPIOI_AFRH              (PIN_AFIO_AF(GPIOI_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/cfg/board.chcfg b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/cfg/board.chcfg
new file mode 100644
index 00000000..a5593446
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/cfg/board.chcfg
@@ -0,0 +1,1186 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--mikromedia STM32F4-->
+<board
+  xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+  xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f4xx_board.xsd">
+  <configuration_settings>
+    <templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
+    <output_path>..</output_path>
+  </configuration_settings>
+  <board_name>mikromedia STM32-M4</board_name>
+  <board_id>MIKROE_MIKROMEDIA_M4</board_id>
+  <board_functions></board_functions>
+  <clocks HSEFrequency="16000000" HSEBypass="false" LSEFrequency="32768" VDD="330" />
+  <ports>
+    <GPIOA>
+      <pin0
+        ID="VSENSE"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Analog"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="6" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="High"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="5" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="High"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="5" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="High"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="5" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" ></pin8>
+      <pin9
+        ID="VBUS_FS"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID="OTG_FS_DM"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="10" />
+      <pin12
+        ID="OTG_FS_DP"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="10" />
+      <pin13
+        ID="TMS"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin14
+        ID="TCK"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin15
+        ID="TDI"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOA>
+    <GPIOB>
+      <pin0
+        ID="LCD_YD"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Analog"
+        Alternate="0" />
+      <pin1
+        ID="LCD_XL"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Analog"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID="TDO"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="0" ></pin3>
+      <pin4
+        ID="TRST"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID="SCL1"
+        Type="OpenDrain"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="4" />
+      <pin7
+        ID="SDA1"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="4" />
+      <pin8
+        ID="DRIVEA"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin9
+        ID="DRIVEB"
+        Type="OpenDrain"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" ></pin9>
+      <pin10
+        ID="SCL2"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID="SDA2"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID="SCK2"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID="MISO2"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID="MOSI2"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOB>
+    <GPIOC>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" ></pin3>
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID="MP3_DREQ"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID="MP3_RST"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="6" />
+      <pin8
+        ID="MP3_CS"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Output"
+        Alternate="0" />
+      <pin9
+        ID="MP3_DCS"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID="SCK3"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="6" />
+      <pin11
+        ID="MISO3"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="6" />
+      <pin12
+        ID="MOSI3"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="6" />
+      <pin13
+        ID="STAT"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOC>
+    <GPIOD>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID="SD_CS"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin5
+        ID="TX2"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="7" ></pin5>
+      <pin6
+        ID="RX2"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Alternate"
+        Alternate="7" />
+      <pin7
+        ID="FLASH_CS"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Output"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="Low"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="Low"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="Low"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" ></pin14>
+      <pin15
+        ID="SD_CD"
+        Type="PushPull"
+        Level="Low"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOD>
+    <GPIOE>
+      <pin0
+        ID="TD0"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin1
+        ID="TD1"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin2
+        ID="TD2"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin3
+        ID="TD3"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin4
+        ID="TD4"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin5
+        ID="TD5"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin6
+        ID="TD6"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin7
+        ID="TD7"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin8
+        ID="LCD_RST"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin9
+        ID="LCD_BLED"
+        Type="PushPull"
+        Level="Low"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin10
+        ID="PMRD"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin11
+        ID="PMWR"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin12
+        ID="LCD_RS"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID="LCD_CS"
+        Type="PushPull"
+        Level="Low"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+    </GPIOE>
+    <GPIOF>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOF>
+    <GPIOG>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOG>
+    <GPIOH>
+      <pin0
+        ID="OSC_IN"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID="OSC_OUT"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" ></pin2>
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOH>
+    <GPIOI>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOI>
+  </ports>
+</board>
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/flash_memory.c b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/flash_memory.c
new file mode 100644
index 00000000..a27a3db5
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/flash_memory.c
@@ -0,0 +1,127 @@
+#include "hal.h"
+#include "flash_memory.h"
+
+static const unsigned short _SERIAL_FLASH_CMD_RDID  = 0x9F;    // 25P80
+static const unsigned short _SERIAL_FLASH_CMD_READ  = 0x03;
+static const unsigned short _SERIAL_FLASH_CMD_WRITE = 0x02;
+static const unsigned short _SERIAL_FLASH_CMD_WREN  = 0x06;
+static const unsigned short _SERIAL_FLASH_CMD_RDSR  = 0x05;
+static const unsigned short _SERIAL_FLASH_CMD_ERASE = 0xC7;    // 25P80
+static const unsigned short _SERIAL_FLASH_CMD_EWSR  = 0x06;    // 25P80
+static const unsigned short _SERIAL_FLASH_CMD_WRSR  = 0x01;
+static const unsigned short _SERIAL_FLASH_CMD_SER   = 0xD8;    //25P80
+
+static const SPIConfig flash_spicfg = {
+  NULL,
+  GPIOD,
+  GPIOD_FLASH_CS,
+  0
+};
+
+bool flash_is_write_busy(void) {
+  static uint8_t is_write_busy_cmd[1];
+  is_write_busy_cmd[0] = _SERIAL_FLASH_CMD_RDSR;
+  
+  uint8_t result[1];
+
+  spiAcquireBus(&SPID3);
+  spiStart(&SPID3, &flash_spicfg);
+  spiSelect(&SPID3);
+  spiSend(&SPID3, sizeof(is_write_busy_cmd), is_write_busy_cmd);
+  spiReceive(&SPID3, sizeof(result), result);
+  spiUnselect(&SPID3);
+  spiReleaseBus(&SPID3);
+
+  return result[0]&0x01;
+}
+
+void flash_write_enable(void) {
+  spiAcquireBus(&SPID3);
+  spiStart(&SPID3, &flash_spicfg);
+  spiSelect(&SPID3);
+  spiSend(&SPID3, 1, &_SERIAL_FLASH_CMD_WREN);
+  spiUnselect(&SPID3);
+  spiReleaseBus(&SPID3);
+}
+
+void flash_sector_erase(uint32_t sector) {
+  flash_write_enable();
+  static uint8_t sector_erase_cmd[4];
+  sector_erase_cmd[0] = _SERIAL_FLASH_CMD_SER;
+  sector_erase_cmd[1] = (sector >> 16) & 0xFF;
+  sector_erase_cmd[2] = (sector >> 8) & 0xFF;
+  sector_erase_cmd[3] = sector & 0xFF;
+
+
+  spiAcquireBus(&SPID3);
+  spiStart(&SPID3, &flash_spicfg);
+  spiSelect(&SPID3);
+  spiSend(&SPID3, sizeof(sector_erase_cmd), sector_erase_cmd);
+  spiUnselect(&SPID3);
+  spiReleaseBus(&SPID3);
+
+  /* wait for complete */
+  while(flash_is_write_busy());
+}
+
+void flash_read(uint32_t address, size_t bytes, uint8_t *out) {
+  static uint8_t sector_read_cmd[4];
+  sector_read_cmd[0] = _SERIAL_FLASH_CMD_READ;
+  sector_read_cmd[1] = (address >> 16) & 0xFF;
+  sector_read_cmd[2] = (address >> 8) & 0xFF;
+  sector_read_cmd[3] = address & 0xFF;
+
+  spiAcquireBus(&SPID3);
+  spiStart(&SPID3, &flash_spicfg);
+  spiSelect(&SPID3);
+  spiSend(&SPID3, sizeof(sector_read_cmd), sector_read_cmd);
+  spiReceive(&SPID3, bytes, out);
+  spiUnselect(&SPID3);
+  spiReleaseBus(&SPID3);
+}
+
+void flash_write(uint32_t address, size_t bytes, const uint8_t *data) {
+  static uint8_t flash_write_cmd[4];
+
+  flash_write_enable();
+
+  flash_write_cmd[0] = _SERIAL_FLASH_CMD_WRITE;
+  flash_write_cmd[1] = (address >> 16) & 0xFF;
+  flash_write_cmd[2] = (address >> 8) & 0xFF;
+  flash_write_cmd[3] = address & 0xFF;
+
+  spiAcquireBus(&SPID3);
+  spiStart(&SPID3, &flash_spicfg);
+  spiSelect(&SPID3);
+  spiSend(&SPID3, sizeof(flash_write_cmd), flash_write_cmd);
+  spiSend(&SPID3, bytes, data);
+  spiUnselect(&SPID3);
+  spiReleaseBus(&SPID3);
+
+  /* wait for complete */
+  while(flash_is_write_busy());
+}
+
+bool flash_tp_calibrated(void) {
+  uint8_t out[1];
+  flash_read(0x0F0000, 1, out);
+
+  return (out[0] == 0x01);
+}
+
+void flash_tp_calibration_save(uint16_t instance, const uint8_t *calbuf, size_t sz) {
+  if (instance) return;
+  flash_sector_erase(0x0F0000);
+  uint8_t calibrated = 0x01;
+  flash_write(0x0F0000, 1, &calibrated);
+  flash_write(0x0F0001, sz, calbuf);
+}
+const char *flash_tp_calibration_load(uint16_t instance) {
+  static uint8_t foo[24];
+
+  if (instance) return 0;
+  if (!flash_tp_calibrated()) return 0;
+  flash_read(0x0F0001, 24, foo);
+
+  return (char *)foo;
+}
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/flash_memory.h b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/flash_memory.h
new file mode 100644
index 00000000..2dcc9206
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/flash_memory.h
@@ -0,0 +1,6 @@
+void flash_sector_erase(uint32_t sector);
+void flash_read(uint32_t address, size_t bytes, uint8_t *out);
+void flash_write(uint32_t address, size_t bytes, const uint8_t *data);
+bool flash_tp_calibrated(void);
+void flash_tp_calibration_save(uint16_t instance, const uint8_t *calbuf, size_t sz);
+const char *flash_tp_calibration_load(uint16_t instance);
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/board.mk b/boards/base/Mikromedia-STM32-M4-ILI9341/board.mk
new file mode 100644
index 00000000..e466621c
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/board.mk
@@ -0,0 +1,5 @@
+GFXINC  += $(GFXLIB)/boards/base/Mikromedia-STM32-M4-ILI9341
+GFXSRC  +=
+GFXDEFS += -DGFX_USE_OS_CHIBIOS=TRUE
+include $(GFXLIB)/drivers/gdisp/ILI9341/gdisp_lld.mk
+include $(GFXLIB)/drivers/ginput/touch/MCU/ginput_lld.mk
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/board_ILI9341.h b/boards/base/Mikromedia-STM32-M4-ILI9341/board_ILI9341.h
new file mode 100644
index 00000000..c73c68a9
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/board_ILI9341.h
@@ -0,0 +1,124 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    boards/base/Mikromedia-STM32-M4-ILI9341/board_ILI9341.h
+ * @brief   GDISP Graphics Driver subsystem low level driver source for the ILI9341 display.
+ */
+
+#ifndef _GDISP_LLD_BOARD_H
+#define _GDISP_LLD_BOARD_H
+
+// For a multiple display configuration we would put all this in a structure and then
+//	set g->board to that structure.
+#define SET_CS    palSetPad(GPIOE, GPIOE_LCD_CS);
+#define CLR_CS    palClearPad(GPIOE, GPIOE_LCD_CS);
+#define SET_RS    palSetPad(GPIOE, GPIOE_LCD_RS);
+#define CLR_RS    palClearPad(GPIOE, GPIOE_LCD_RS);
+#define SET_WR    palSetPad(GPIOE, GPIOE_PMWR);
+#define CLR_WR    palClearPad(GPIOE, GPIOE_PMWR);
+#define SET_RD    palSetPad(GPIOE, GPIOE_PMRD);
+#define CLR_RD    palClearPad(GPIOE, GPIOE_PMRD);
+
+static inline void init_board(GDisplay *g) {
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		/* Configure the pins to a well know state */
+		SET_RS;
+		SET_RD;
+		SET_WR;
+		CLR_CS;
+		break;
+	}
+}
+
+static inline void post_init_board(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	if(state) {
+		// reset lcd
+		palClearPad(GPIOE, GPIOE_LCD_RST);
+	} else {
+		palSetPad(GPIOE, GPIOE_LCD_RST);
+	}
+}
+
+static inline void set_backlight(GDisplay *g, uint8_t percent) {
+	(void) g;
+	// TODO: can probably pwm this
+	if(percent) {
+		// turn back light on
+		palSetPad(GPIOE, GPIOE_LCD_BLED);
+	} else {
+		// turn off
+		palClearPad(GPIOE, GPIOE_LCD_BLED);
+	}
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+}
+
+/**
+ * @brief   Short delay
+ *
+ * @param[in] dly		Length of delay
+ *
+ * @notapi
+ */
+static inline void ili9341_delay(uint16_t dly) {
+  static uint16_t i;
+  for(i = 0; i < dly; i++)
+    asm("nop");
+}
+
+static inline void write_index(GDisplay *g, uint16_t index) {
+	(void) g;
+	palWriteGroup(GPIOE, 0x00FF, 0, index);
+	CLR_RS; CLR_WR; ili9341_delay(1); SET_WR; ili9341_delay(1); SET_RS;
+}
+
+static inline void write_data(GDisplay *g, uint16_t data) {
+	(void) g;
+	palWriteGroup(GPIOE, 0x00FF, 0, data);
+	CLR_WR; ili9341_delay(1); SET_WR; ili9341_delay(1);
+}
+
+static inline void setreadmode(GDisplay *g) {
+	(void) g;
+	// change pin mode to digital input
+	palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_INPUT);
+}
+
+static inline void setwritemode(GDisplay *g) {
+	(void) g;
+	// change pin mode back to digital output
+	palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
+}
+
+static inline uint16_t read_data(GDisplay *g) {
+	uint16_t	value;
+	(void) g;
+	CLR_RD;
+	value = palReadPort(GPIOE);
+	value = palReadPort(GPIOE);
+	SET_RD;
+	return value;
+}
+
+#endif /* _GDISP_LLD_BOARD_H */
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/example/Makefile b/boards/base/Mikromedia-STM32-M4-ILI9341/example/Makefile
new file mode 100644
index 00000000..6fca731e
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/example/Makefile
@@ -0,0 +1,232 @@
+##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+  # Replace -O0 with -O2 for a production build. -O2 just messes with the debugger.
+  USE_OPT = -O0 -g -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+  USE_COPT = 
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+  USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+  USE_LINK_GC = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+  USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+  USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+  USE_FPU = no
+endif
+
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FWLIB),)
+  USE_FWLIB = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+SW = ..
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../ChibiOS
+#include $(CHIBIOS)/boards/MIKROMEDIA_STM32_M4/board.mk					# Not a standard ChibiOS supported board
+include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
+include $(CHIBIOS)/os/kernel/kernel.mk
+LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+
+# Imported source files and paths for uGFX
+GFXLIB = ../uGFX
+include $(GFXLIB)/gfx.mk
+include $(GFXLIB)/boards/base/Mikromedia-STM32-M4-ILI9341/board.mk
+include $(GFXLIB)/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.mk		# The replacement ChibiOS board files
+
+# Where is our source code - alter these for your project.
+MYFILES = $(GFXLIB)/demos/modules/gdisp/basics
+MYCSRC  = $(MYFILES)/main.c
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(PORTSRC) \
+       $(KERNSRC) \
+       $(TESTSRC) \
+       $(HALSRC) \
+       $(PLATFORMSRC) \
+       $(BOARDSRC) \
+       $(GFXSRC) \
+       $(MYCSRC)
+       
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+#       option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+#       option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+#       option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+#       option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(PORTASM)
+
+INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
+         $(HALINC) $(PLATFORMINC) $(BOARDINC) \
+         $(GFXINC) \
+         $(MYFILES)
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU  = cortex-m4
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC   = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+#       runtime support makes code size explode.
+LD   = $(TRGT)gcc
+#LD   = $(TRGT)g++
+CP   = $(TRGT)objcopy
+AS   = $(TRGT)gcc -x assembler-with-cpp
+OD   = $(TRGT)objdump
+HEX  = $(CP) -O ihex
+BIN  = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of default section
+#
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS = $(GFXDEFS)
+
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS =
+
+# List all default directories to look for include files here
+DINCDIR =
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS =
+
+#
+# End of default section
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+ifeq ($(USE_FPU),yes)
+  USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+  DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+  DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
+ifeq ($(USE_FWLIB),yes)
+  include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
+  CSRC += $(STM32SRC)
+  INCDIR += $(STM32INC)
+  USE_OPT += -DUSE_STDPERIPH_DRIVER
+endif
+
+include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/example/chconf.h b/boards/base/Mikromedia-STM32-M4-ILI9341/example/chconf.h
new file mode 100644
index 00000000..f4682cb9
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/example/chconf.h
@@ -0,0 +1,531 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    templates/chconf.h
+ * @brief   Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ *          contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ *          setting also defines the system tick time unit.
+ */
+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
+#define CH_FREQUENCY                    1000
+#endif
+
+/**
+ * @brief   Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ *          threads before preemption occurs. Setting this value to zero
+ *          disables the preemption for threads with equal priority and the
+ *          round robin becomes cooperative. Note that higher priority
+ *          threads can still preempt, the kernel is always preemptive.
+ *
+ * @note    Disabling the round robin preemption makes the kernel more compact
+ *          and generally faster.
+ */
+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
+#define CH_TIME_QUANTUM                 20
+#endif
+
+/**
+ * @brief   Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ *          then the whole available RAM is used. The core memory is made
+ *          available to the heap allocator and/or can be used directly through
+ *          the simplified core memory allocator.
+ *
+ * @note    In order to let the OS manage the whole RAM the linker script must
+ *          provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note    Requires @p CH_USE_MEMCORE.
+ */
+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
+#define CH_MEMCORE_SIZE                 0
+#endif
+
+/**
+ * @brief   Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ *          does not spawn the idle thread automatically. The application has
+ *          then the responsibility to do one of the following:
+ *          - Spawn a custom idle thread at priority @p IDLEPRIO.
+ *          - Change the main() thread priority to @p IDLEPRIO then enter
+ *            an endless loop. In this scenario the @p main() thread acts as
+ *            the idle thread.
+ *          .
+ * @note    Unless an idle thread is spawned the @p main() thread must not
+ *          enter a sleep state.
+ */
+#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
+#define CH_NO_IDLE_THREAD               FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ *          is used when two possible implementations exist.
+ *
+ * @note    This is not related to the compiler optimization options.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
+#define CH_OPTIMIZE_SPEED               TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
+#define CH_USE_REGISTRY                 TRUE
+#endif
+
+/**
+ * @brief   Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ *          the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
+#define CH_USE_WAITEXIT                 TRUE
+#endif
+
+/**
+ * @brief   Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES               TRUE
+#endif
+
+/**
+ * @brief   Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ *          priority rather than in FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special requirements.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES_PRIORITY      FALSE
+#endif
+
+/**
+ * @brief   Atomic semaphore API.
+ * @details If enabled then the semaphores the @p chSemSignalWait() API
+ *          is included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
+#define CH_USE_SEMSW                    TRUE
+#endif
+
+/**
+ * @brief   Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
+#define CH_USE_MUTEXES                  TRUE
+#endif
+
+/**
+ * @brief   Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_MUTEXES.
+ */
+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS                 TRUE
+#endif
+
+/**
+ * @brief   Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ *          specification are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_CONDVARS.
+ */
+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS_TIMEOUT         TRUE
+#endif
+
+/**
+ * @brief   Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS                   TRUE
+#endif
+
+/**
+ * @brief   Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ *          are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_EVENTS.
+ */
+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS_TIMEOUT           TRUE
+#endif
+
+/**
+ * @brief   Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES                 TRUE
+#endif
+
+/**
+ * @brief   Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ *          FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special requirements.
+ * @note    Requires @p CH_USE_MESSAGES.
+ */
+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES_PRIORITY        FALSE
+#endif
+
+/**
+ * @brief   Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ *          included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
+#define CH_USE_MAILBOXES                TRUE
+#endif
+
+/**
+ * @brief   I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
+#define CH_USE_QUEUES                   TRUE
+#endif
+
+/**
+ * @brief   Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
+#define CH_USE_MEMCORE                  TRUE
+#endif
+
+/**
+ * @brief   Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
+ *          @p CH_USE_SEMAPHORES.
+ * @note    Mutexes are recommended.
+ */
+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_HEAP                     TRUE
+#endif
+
+/**
+ * @brief   C-runtime allocator.
+ * @details If enabled the the heap allocator APIs just wrap the C-runtime
+ *          @p malloc() and @p free() functions.
+ *
+ * @note    The default is @p FALSE.
+ * @note    Requires @p CH_USE_HEAP.
+ * @note    The C-runtime may or may not require @p CH_USE_MEMCORE, see the
+ *          appropriate documentation.
+ */
+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_MALLOC_HEAP              FALSE
+#endif
+
+/**
+ * @brief   Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
+#define CH_USE_MEMPOOLS                 TRUE
+#endif
+
+/**
+ * @brief   Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_WAITEXIT.
+ * @note    Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ */
+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
+#define CH_USE_DYNAMIC                  TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ *          at runtime.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_SYSTEM_STATE_CHECK       FALSE
+#endif
+
+/**
+ * @brief   Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ *          parameters are activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_CHECKS            FALSE
+#endif
+
+/**
+ * @brief   Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ *          activated. This includes consistency checks inside the kernel,
+ *          runtime anomalies and port-defined checks.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_ASSERTS           FALSE
+#endif
+
+/**
+ * @brief   Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ *          activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_TRACE             FALSE
+#endif
+
+/**
+ * @brief   Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note    The default is @p FALSE.
+ * @note    The stack check is performed in a architecture/port dependent way.
+ *          It may not be implemented or some ports.
+ * @note    The default failure mode is to halt the system with the global
+ *          @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_STACK_CHECK       FALSE
+#endif
+
+/**
+ * @brief   Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ *          value when a thread is created. This can be useful for the
+ *          runtime measurement of the used stack.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
+#define CH_DBG_FILL_THREADS             FALSE
+#endif
+
+/**
+ * @brief   Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p Thread structure that
+ *          counts the system ticks occurred while executing the thread.
+ *
+ * @note    The default is @p TRUE.
+ * @note    This debug option is defaulted to TRUE because it is required by
+ *          some test cases into the test suite.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
+#define CH_DBG_THREADS_PROFILING        TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Threads descriptor structure extension.
+ * @details User fields added to the end of the @p Thread structure.
+ */
+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define THREAD_EXT_FIELDS                                                   \
+  /* Add threads custom fields here.*/
+#endif
+
+/**
+ * @brief   Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note    It is invoked from within @p chThdInit() and implicitly from all
+ *          the threads creation APIs.
+ */
+#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_INIT_HOOK(tp) {                                          \
+  /* Add threads initialization code here.*/                                \
+}
+#endif
+
+/**
+ * @brief   Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note    It is inserted into lock zone.
+ * @note    It is also invoked when the threads simply return in order to
+ *          terminate.
+ */
+#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_EXIT_HOOK(tp) {                                          \
+  /* Add threads finalization code here.*/                                  \
+}
+#endif
+
+/**
+ * @brief   Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
+#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \
+  /* System halt code here.*/                                               \
+}
+#endif
+
+/**
+ * @brief   Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
+#define IDLE_LOOP_HOOK() {                                                  \
+  /* Idle loop code here.*/                                                 \
+}
+#endif
+
+/**
+ * @brief   System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ *          after processing the virtual timers queue.
+ */
+#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_TICK_EVENT_HOOK() {                                          \
+  /* System tick event code here.*/                                         \
+}
+#endif
+
+/**
+ * @brief   System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ *          the system is halted.
+ */
+#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_HALT_HOOK() {                                                \
+  /* System halt code here.*/                                               \
+}
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h).    */
+/*===========================================================================*/
+
+#endif  /* _CHCONF_H_ */
+
+/** @} */
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/example/halconf.h b/boards/base/Mikromedia-STM32-M4-ILI9341/example/halconf.h
new file mode 100644
index 00000000..6585fb3e
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/example/halconf.h
@@ -0,0 +1,312 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    templates/halconf.h
+ * @brief   HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ *          various device drivers from your application. You may also use
+ *          this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief   Enables the TM subsystem.
+ */
+#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
+#define HAL_USE_TM                  FALSE
+#endif
+
+/**
+ * @brief   Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL                 TRUE
+#endif
+
+/**
+ * @brief   Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC                 TRUE
+#endif
+
+/**
+ * @brief   Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN                 FALSE
+#endif
+
+/**
+ * @brief   Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT                 FALSE
+#endif
+
+/**
+ * @brief   Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT                 FALSE
+#endif
+
+/**
+ * @brief   Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C                 FALSE
+#endif
+
+/**
+ * @brief   Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU                 FALSE
+#endif
+
+/**
+ * @brief   Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI             TRUE
+#endif
+
+/**
+ * @brief   Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM                 TRUE
+#endif
+
+/**
+ * @brief   Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL              TRUE
+#endif
+
+/**
+ * @brief   Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB          FALSE
+#endif
+
+/**
+ * @brief   Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI                 TRUE
+#endif
+
+/**
+ * @brief   Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART                FALSE
+#endif
+
+/**
+ * @brief   Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB                 FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables synchronous APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT                TRUE
+#endif
+
+/**
+ * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE          TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY           FALSE
+#endif
+
+/**
+ * @brief   Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS              TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings.                                          */
+/*===========================================================================*/
+
+/**
+ * @brief   Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ *          routines releasing some extra CPU time for the threads with
+ *          lower priority, this may slow down the driver a bit however.
+ *          This option is recommended also if the SPI driver does not
+ *          use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING            TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Number of initialization attempts before rejecting the card.
+ * @note    Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY              100
+#endif
+
+/**
+ * @brief   Include support for MMC cards.
+ * @note    MMC support is not yet implemented so this option must be kept
+ *          at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT             FALSE
+#endif
+
+/**
+ * @brief   Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ *          routines releasing some extra CPU time for the threads with
+ *          lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING            TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings.                                           */
+/*===========================================================================*/
+
+/**
+ * @brief   Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ *          default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE      38400
+#endif
+
+/**
+ * @brief   Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ *          buffers depending on the requirements of your application.
+ * @note    The default is 64 bytes for both the transmission and receive
+ *          buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE         16
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables synchronous APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT                TRUE
+#endif
+
+/**
+ * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/example/mcuconf.h b/boards/base/Mikromedia-STM32-M4-ILI9341/example/mcuconf.h
new file mode 100644
index 00000000..64895943
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/example/mcuconf.h
@@ -0,0 +1,289 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0       Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3        Lowest...Highest.
+ */
+
+#define STM32F4xx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT                       FALSE
+#define STM32_HSI_ENABLED                   TRUE
+#define STM32_LSI_ENABLED                   TRUE
+#define STM32_HSE_ENABLED                   FALSE
+#define STM32_LSE_ENABLED                   TRUE
+#define STM32_CLOCK48_REQUIRED              TRUE
+#define STM32_SW                            STM32_SW_PLL
+#define STM32_PLLSRC                        STM32_PLLSRC_HSI
+#define STM32_PLLM_VALUE                    16
+#define STM32_PLLN_VALUE                    336
+#define STM32_PLLP_VALUE                    2
+#define STM32_PLLQ_VALUE                    7
+#define STM32_HPRE                          STM32_HPRE_DIV1
+#define STM32_PPRE1                         STM32_PPRE1_DIV4
+#define STM32_PPRE2                         STM32_PPRE2_DIV2
+#define STM32_RTCSEL                        STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE                  8
+#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV5
+#define STM32_I2SSRC                        STM32_I2SSRC_CKIN
+#define STM32_PLLI2SN_VALUE                 192
+#define STM32_PLLI2SR_VALUE                 5
+#define STM32_VOS                           STM32_VOS_HIGH
+#define STM32_PVD_ENABLE                    FALSE
+#define STM32_PLS                           STM32_PLS_LEV0
+#define STM32_BKPRAM_ENABLE                 FALSE
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1                  TRUE
+#define STM32_ADC_USE_ADC2                  FALSE
+#define STM32_ADC_USE_ADC3                  FALSE
+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC1_DMA_PRIORITY         2
+#define STM32_ADC_ADC2_DMA_PRIORITY         2
+#define STM32_ADC_ADC3_DMA_PRIORITY         2
+#define STM32_ADC_IRQ_PRIORITY              6
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     6
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     6
+
+/*
+ * CAN driver system settings.
+ */
+#define STM32_CAN_USE_CAN1                  FALSE
+#define STM32_CAN_USE_CAN2                  FALSE
+#define STM32_CAN_CAN1_IRQ_PRIORITY         11
+#define STM32_CAN_CAN2_IRQ_PRIORITY         11
+
+/*
+ * EXT driver system settings.
+ */
+#define STM32_EXT_EXTI0_IRQ_PRIORITY        6
+#define STM32_EXT_EXTI1_IRQ_PRIORITY        6
+#define STM32_EXT_EXTI2_IRQ_PRIORITY        6
+#define STM32_EXT_EXTI3_IRQ_PRIORITY        6
+#define STM32_EXT_EXTI4_IRQ_PRIORITY        6
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY      6
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY    6
+#define STM32_EXT_EXTI16_IRQ_PRIORITY       6
+#define STM32_EXT_EXTI17_IRQ_PRIORITY       15
+#define STM32_EXT_EXTI18_IRQ_PRIORITY       6
+#define STM32_EXT_EXTI19_IRQ_PRIORITY       6
+#define STM32_EXT_EXTI20_IRQ_PRIORITY       6
+#define STM32_EXT_EXTI21_IRQ_PRIORITY       15
+#define STM32_EXT_EXTI22_IRQ_PRIORITY       15
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1                  FALSE
+#define STM32_GPT_USE_TIM2                  FALSE
+#define STM32_GPT_USE_TIM3                  FALSE
+#define STM32_GPT_USE_TIM4                  FALSE
+#define STM32_GPT_USE_TIM5                  FALSE
+#define STM32_GPT_USE_TIM6                  FALSE
+#define STM32_GPT_USE_TIM7                  FALSE
+#define STM32_GPT_USE_TIM8                  FALSE
+#define STM32_GPT_USE_TIM9                  FALSE
+#define STM32_GPT_USE_TIM11                 FALSE
+#define STM32_GPT_USE_TIM12                 FALSE
+#define STM32_GPT_USE_TIM14                 FALSE
+#define STM32_GPT_TIM1_IRQ_PRIORITY         7
+#define STM32_GPT_TIM2_IRQ_PRIORITY         7
+#define STM32_GPT_TIM3_IRQ_PRIORITY         7
+#define STM32_GPT_TIM4_IRQ_PRIORITY         7
+#define STM32_GPT_TIM5_IRQ_PRIORITY         7
+#define STM32_GPT_TIM6_IRQ_PRIORITY         7
+#define STM32_GPT_TIM7_IRQ_PRIORITY         7
+#define STM32_GPT_TIM8_IRQ_PRIORITY         7
+#define STM32_GPT_TIM9_IRQ_PRIORITY         7
+#define STM32_GPT_TIM11_IRQ_PRIORITY        7
+#define STM32_GPT_TIM12_IRQ_PRIORITY        7
+#define STM32_GPT_TIM14_IRQ_PRIORITY        7
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1                  FALSE
+#define STM32_I2C_USE_I2C2                  FALSE
+#define STM32_I2C_USE_I2C3                  FALSE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY         5
+#define STM32_I2C_I2C2_IRQ_PRIORITY         5
+#define STM32_I2C_I2C3_IRQ_PRIORITY         5
+#define STM32_I2C_I2C1_DMA_PRIORITY         3
+#define STM32_I2C_I2C2_DMA_PRIORITY         3
+#define STM32_I2C_I2C3_DMA_PRIORITY         3
+#define STM32_I2C_I2C1_DMA_ERROR_HOOK()     chSysHalt()
+#define STM32_I2C_I2C2_DMA_ERROR_HOOK()     chSysHalt()
+#define STM32_I2C_I2C3_DMA_ERROR_HOOK()     chSysHalt()
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1                  FALSE
+#define STM32_ICU_USE_TIM2                  FALSE
+#define STM32_ICU_USE_TIM3                  FALSE
+#define STM32_ICU_USE_TIM4                  FALSE
+#define STM32_ICU_USE_TIM5                  FALSE
+#define STM32_ICU_USE_TIM8                  FALSE
+#define STM32_ICU_USE_TIM9                  FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY         7
+#define STM32_ICU_TIM2_IRQ_PRIORITY         7
+#define STM32_ICU_TIM3_IRQ_PRIORITY         7
+#define STM32_ICU_TIM4_IRQ_PRIORITY         7
+#define STM32_ICU_TIM5_IRQ_PRIORITY         7
+#define STM32_ICU_TIM8_IRQ_PRIORITY         7
+#define STM32_ICU_TIM9_IRQ_PRIORITY         7
+
+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED              FALSE
+#define STM32_PWM_USE_TIM1                  FALSE
+#define STM32_PWM_USE_TIM2                  FALSE
+#define STM32_PWM_USE_TIM3                  FALSE
+#define STM32_PWM_USE_TIM4                  TRUE
+#define STM32_PWM_USE_TIM5                  FALSE
+#define STM32_PWM_USE_TIM8                  FALSE
+#define STM32_PWM_USE_TIM9                  FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY         7
+#define STM32_PWM_TIM2_IRQ_PRIORITY         7
+#define STM32_PWM_TIM3_IRQ_PRIORITY         7
+#define STM32_PWM_TIM4_IRQ_PRIORITY         7
+#define STM32_PWM_TIM5_IRQ_PRIORITY         7
+#define STM32_PWM_TIM8_IRQ_PRIORITY         7
+#define STM32_PWM_TIM9_IRQ_PRIORITY         7
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1             FALSE
+#define STM32_SERIAL_USE_USART2             TRUE
+#define STM32_SERIAL_USE_USART3             FALSE
+#define STM32_SERIAL_USE_UART4              FALSE
+#define STM32_SERIAL_USE_UART5              FALSE
+#define STM32_SERIAL_USE_USART6             FALSE
+#define STM32_SERIAL_USART1_PRIORITY        12
+#define STM32_SERIAL_USART2_PRIORITY        12
+#define STM32_SERIAL_USART3_PRIORITY        12
+#define STM32_SERIAL_UART4_PRIORITY         12
+#define STM32_SERIAL_UART5_PRIORITY         12
+#define STM32_SERIAL_USART6_PRIORITY        12
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1                  FALSE
+#define STM32_SPI_USE_SPI2                  TRUE
+#define STM32_SPI_USE_SPI3                  TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI1_DMA_PRIORITY         1
+#define STM32_SPI_SPI2_DMA_PRIORITY         1
+#define STM32_SPI_SPI3_DMA_PRIORITY         1
+#define STM32_SPI_SPI1_IRQ_PRIORITY         10
+#define STM32_SPI_SPI2_IRQ_PRIORITY         10
+#define STM32_SPI_SPI3_IRQ_PRIORITY         10
+#define STM32_SPI_DMA_ERROR_HOOK(spip)      chSysHalt()
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1               FALSE
+#define STM32_UART_USE_USART2               FALSE
+#define STM32_UART_USE_USART3               FALSE
+#define STM32_UART_USE_UART4                FALSE
+#define STM32_UART_USE_UART5                FALSE
+#define STM32_UART_USE_USART6               FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 1)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 2)
+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 4)
+#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 0)
+#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(1, 7)
+#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)
+#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART1_IRQ_PRIORITY      12
+#define STM32_UART_USART2_IRQ_PRIORITY      12
+#define STM32_UART_USART3_IRQ_PRIORITY      12
+#define STM32_UART_UART4_IRQ_PRIORITY       12
+#define STM32_UART_UART5_IRQ_PRIORITY       12
+#define STM32_UART_USART6_IRQ_PRIORITY      12
+#define STM32_UART_USART1_DMA_PRIORITY      0
+#define STM32_UART_USART2_DMA_PRIORITY      0
+#define STM32_UART_USART3_DMA_PRIORITY      0
+#define STM32_UART_UART4_DMA_PRIORITY       0
+#define STM32_UART_UART5_DMA_PRIORITY       0
+#define STM32_UART_USART6_DMA_PRIORITY      0
+#define STM32_UART_DMA_ERROR_HOOK(uartp)    chSysHalt()
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG1                  FALSE
+#define STM32_USB_USE_OTG2                  FALSE
+#define STM32_USB_OTG1_IRQ_PRIORITY         14
+#define STM32_USB_OTG2_IRQ_PRIORITY         14
+#define STM32_USB_OTG1_RX_FIFO_SIZE         512
+#define STM32_USB_OTG2_RX_FIFO_SIZE         1024
+#define STM32_USB_OTG_THREAD_PRIO           LOWPRIO
+#define STM32_USB_OTG_THREAD_STACK_SIZE     128
+#define STM32_USB_OTGFIFO_FILL_BASEPRI      0
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/example/openocd.cfg b/boards/base/Mikromedia-STM32-M4-ILI9341/example/openocd.cfg
new file mode 100644
index 00000000..f8b6a6f5
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/example/openocd.cfg
@@ -0,0 +1,81 @@
+# This is a script file for OpenOCD 0.7.0
+#
+# It is set up for the Mikromedia-STM32M4 board using the ST-Link JTAG adaptor.
+#
+# Assuming the current directory is your project directory containing this openocd.cfg file...
+#
+# To program your device:
+#
+#	openocd -f openocd.cfg -c "Burn yourfile.bin" -c shutdown
+#
+# To debug your device:
+#
+#	openocd
+#	(This will run openocd in gdb server debug mode. Leave it running in the background)
+#
+#	gdb yourfile.elf
+#	(To start gdb. Then run the following commands in gdb...)
+#
+#	target remote 127.0.0.1:3333
+#	monitor Debug
+#	stepi
+#	(This last stepi resynchronizes gdb).
+#
+# If you want to reprogram from within gdb:
+#
+#	monitor Burn yourfile.bin
+#
+
+echo ""
+echo "##### Loading debugger..."
+source [find interface/stlink-v2.cfg]
+
+echo ""
+echo "##### Loading CPU..."
+source [find target/stm32f4x_stlink.cfg]
+
+echo ""
+echo "##### Configuring..."
+reset_config srst_only srst_nogate
+#cortex_m maskisr (auto|on|off)
+#cortex_m vector_catch [all|none|list]
+#cortex_m reset_config (srst|sysresetreq|vectreset)
+#gdb_breakpoint_override hard
+
+proc Debug { } {
+	echo ""
+	echo "##### Debug Session Connected..."
+	reset init
+	echo "Ready..."
+}
+
+proc Burn {file} {
+	echo ""
+	echo "##### Burning $file to device..."
+	halt
+	# Due to an issue with the combination of the ST-Link adapters and OpenOCD
+	# applying the stm32f2x unlock 0 command actaully applies read protection - VERY BAD!
+	# If this happens to you - use the ST-Link utility to set the option byte back to normal.
+	# If you are using a different debugger eg a FT2232 based adapter you can uncomment the line below.
+	#stm32f2x unlock 0
+	flash protect 0 0 last off
+	reset init
+	flash write_image erase $file 0x08000000
+	verify_image $file 0x0
+	#flash protect 0 0 last on
+	reset
+	echo "Burning Complete!"
+}
+
+echo ""
+echo "##### Leaving Configuration Mode..."
+init
+reset init
+flash probe 0
+flash banks
+#flash info 0
+
+echo ""
+echo "##### Waiting for debug connections..."
+
+
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/ginput_lld_mouse_board.h b/boards/base/Mikromedia-STM32-M4-ILI9341/ginput_lld_mouse_board.h
new file mode 100644
index 00000000..373a2474
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/ginput_lld_mouse_board.h
@@ -0,0 +1,152 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    boards/base/Mikromedia-STM32-M4-ILI9341/ginput_lld_mouse_board.h
+ * @brief   GINPUT Touch low level driver source for the MCU.
+ */
+
+#ifndef _GINPUT_LLD_MOUSE_BOARD_H
+#define _GINPUT_LLD_MOUSE_BOARD_H
+
+/* read ADC if more than this many ticks since last read */
+#define ADC_UPDATE_INTERVAL 3
+
+#define ADC_NUM_CHANNELS   2
+#define ADC_BUF_DEPTH      1
+
+static const ADCConversionGroup adcgrpcfg = {
+  FALSE,
+  ADC_NUM_CHANNELS,
+  NULL,
+  NULL,
+  /* HW dependent part.*/
+  0,
+  ADC_CR2_SWSTART,
+  0,
+  0,
+  ADC_SQR1_NUM_CH(ADC_NUM_CHANNELS),
+  0,
+  ADC_SQR3_SQ2_N(ADC_CHANNEL_IN8) | ADC_SQR3_SQ1_N(ADC_CHANNEL_IN9)
+};
+
+static systime_t last_update;
+static volatile uint16_t tpx, tpy, detect;
+
+static inline void delay(uint16_t dly) {
+  static uint16_t i;
+  for(i = 0; i < dly; i++)
+    asm("nop");
+}
+
+
+void read_mikro_tp(void) {
+	systime_t now = chTimeNow();
+
+	adcsample_t samples[ADC_NUM_CHANNELS * ADC_BUF_DEPTH];
+	uint16_t _detect, _tpx, _tpy;
+
+	if(now < last_update || ((now - last_update) > ADC_UPDATE_INTERVAL)) {
+		// detect button press
+		// sample[0] will go from ~200 to ~4000 when pressed
+	    adcConvert(&ADCD1, &adcgrpcfg, samples, ADC_BUF_DEPTH);
+	    _detect = samples[0];
+
+	    // read x channel
+	   	palSetPad(GPIOB, GPIOB_DRIVEA);
+	    palClearPad(GPIOB, GPIOB_DRIVEB);
+	    chThdSleepMilliseconds(1);
+	    adcConvert(&ADCD1, &adcgrpcfg, samples, ADC_BUF_DEPTH);
+	    _tpx = samples[1];
+
+	    // read y channel (invert)
+	    palClearPad(GPIOB, GPIOB_DRIVEA);
+	    palSetPad(GPIOB, GPIOB_DRIVEB);
+	    chThdSleepMilliseconds(1);
+	    adcConvert(&ADCD1, &adcgrpcfg, samples, ADC_BUF_DEPTH);
+	    _tpy = samples[0];
+
+	    // ready for next read
+	    palClearPad(GPIOB, GPIOB_DRIVEA);
+	    palClearPad(GPIOB, GPIOB_DRIVEB);
+
+	    chSysLock();
+	   	tpx = _tpx;
+	   	tpy = _tpy;
+	   	detect = _detect;
+	    last_update = now;
+	    chSysUnlock();
+	}
+}
+
+/**
+ * @brief   Initialise the board for the touch.
+ *
+ * @notapi
+ */
+static inline void init_board(void) {
+	adcStart(&ADCD1, NULL);
+	last_update = chTimeNow();
+
+	// leave DRIVEA & DRIVEB ready for next read
+	palClearPad(GPIOB, GPIOB_DRIVEA);
+	palClearPad(GPIOB, GPIOB_DRIVEB);
+	chThdSleepMilliseconds(1);
+}
+
+/**
+ * @brief   Check whether the surface is currently touched
+ * @return	TRUE if the surface is currently touched
+ *
+ * @notapi
+ */
+static inline bool_t getpin_pressed(void) {
+	read_mikro_tp();
+	return (detect > 2000) ? true : false;
+}
+
+/**
+ * @brief   Aquire the bus ready for readings
+ *
+ * @notapi
+ */
+static inline void aquire_bus(void) {
+
+}
+
+/**
+ * @brief   Release the bus after readings
+ *
+ * @notapi
+ */
+static inline void release_bus(void) {
+
+}
+
+/**
+ * @brief   Read an x value from touch controller
+ * @return	The value read from the controller
+ *
+ * @notapi
+ */
+static inline uint16_t read_x_value(void) {
+	read_mikro_tp();
+	return tpx;
+}
+
+/**
+ * @brief   Read an y value from touch controller
+ * @return	The value read from the controller
+ *
+ * @notapi
+ */
+static inline uint16_t read_y_value(void) {
+	read_mikro_tp();
+	return tpy;
+}
+
+#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/ginput_lld_mouse_config.h b/boards/base/Mikromedia-STM32-M4-ILI9341/ginput_lld_mouse_config.h
new file mode 100644
index 00000000..0c0ff482
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/ginput_lld_mouse_config.h
@@ -0,0 +1,32 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    boards/base/Mikromedia-STM32-M4-ILI9341/ginput_lld_mouse_config.h
+ * @brief   GINPUT LLD header file for touch driver.
+ *
+ * @defgroup Mouse Mouse
+ * @ingroup GINPUT
+ *
+ * @{
+ */
+
+#ifndef _LLD_GINPUT_MOUSE_CONFIG_H
+#define _LLD_GINPUT_MOUSE_CONFIG_H
+
+#define GINPUT_MOUSE_EVENT_TYPE					GEVENT_TOUCH
+#define GINPUT_MOUSE_NEED_CALIBRATION			TRUE
+#define GINPUT_MOUSE_LLD_CALIBRATION_LOADSAVE	FALSE
+#define GINPUT_MOUSE_MAX_CALIBRATION_ERROR		12
+#define GINPUT_MOUSE_READ_CYCLES				4
+#define GINPUT_MOUSE_POLL_PERIOD				3
+#define GINPUT_MOUSE_MAX_CLICK_JITTER			2
+#define GINPUT_MOUSE_MAX_MOVE_JITTER			2
+#define GINPUT_MOUSE_CLICK_TIME					500
+
+#endif /* _LLD_GINPUT_MOUSE_CONFIG_H */
+/** @} */
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/readme.txt b/boards/base/Mikromedia-STM32-M4-ILI9341/readme.txt
new file mode 100644
index 00000000..961f9793
--- /dev/null
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/readme.txt
@@ -0,0 +1,14 @@
+This directory contains the interface for the MikroMedia STM32 M4 board
+running under ChibiOS with the ILI9341 display.
+
+On this board uGFX currently supports:
+	- GDISP via the ILI9341 display
+	- GINPUT-touch via the MCU driver 
+
+Note there are two variants of this board - one with the ILI9341 display
+	and an older one with a different display. This one is for the ILI9341 display.
+	
+As this is not a standard ChibiOS supported board the necessary board files have also
+been provided in the ChibiOS_Board directory.
+
+There is an example Makefile and project in the examples directory.
diff --git a/boards/base/Olimex-SAM7EX256-GE12/board.mk b/boards/base/Olimex-SAM7EX256-GE12/board.mk
new file mode 100644
index 00000000..662178a6
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE12/board.mk
@@ -0,0 +1,8 @@
+GFXINC  += $(GFXLIB)/boards/base/Olimex-SAM7EX256-GE12 $(GFXLIB)/boards/base/Olimex-SAM7EX256-GE8
+GFXSRC  +=
+GFXDEFS += -DGFX_USE_OS_CHIBIOS=TRUE
+include $(GFXLIB)/drivers/gdisp/Nokia6610GE12/gdisp_lld.mk
+include $(GFXLIB)/drivers/gadc/AT91SAM7/gadc_lld.mk
+include $(GFXLIB)/drivers/ginput/dial/GADC/ginput_lld.mk
+include $(GFXLIB)/drivers/ginput/toggle/Pal/ginput_lld.mk
+include $(GFXLIB)/drivers/gaudin/gadc/gaudin_lld.mk
diff --git a/boards/base/Olimex-SAM7EX256-GE12/board_Nokia6610GE12.h b/boards/base/Olimex-SAM7EX256-GE12/board_Nokia6610GE12.h
new file mode 100644
index 00000000..feb1887e
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE12/board_Nokia6610GE12.h
@@ -0,0 +1,195 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    boards/base/Olimex-SAM7EX256-GE12/board_Nokia6610GE12.h
+ * @brief   GDISP Graphic Driver subsystem board interface for the Olimex SAM7-EX256 board.
+ */
+
+#ifndef _GDISP_LLD_BOARD_H
+#define _GDISP_LLD_BOARD_H
+
+/*
+ * Set various display properties. These properties mostly depend on the exact controller chip you get.
+ * The defaults should work for most controllers.
+ */
+//#define GDISP_GE8_BROKEN_CONTROLLER		FALSE	// Uncomment this out if you have a controller thats not window wrap broken.
+//#define GDISP_SCREEN_HEIGHT				130		// The visible display height
+//#define GDISP_SCREEN_WIDTH				130		// The visible display width
+//#define GDISP_RAM_X_OFFSET				0		// The x offset of the visible area
+//#define GDISP_RAM_Y_OFFSET				2		// The y offset of the visible area
+//#define GDISP_SLEEP_SIZE					32		// The size of the sleep mode partial display
+//#define GDISP_SLEEP_POS					50		// The position of the sleep mode partial display
+//#define GDISP_INITIAL_CONTRAST			38		// The initial contrast percentage
+//#define GDISP_INITIAL_BACKLIGHT			100		// The initial backlight percentage
+
+// For a multiple display configuration we would put all this in a structure and then
+//	set g->board to that structure.
+
+// ******************************************************
+// Pointers to AT91SAM7X256 peripheral data structures
+// ******************************************************
+static volatile AT91PS_PIO pPIOA = AT91C_BASE_PIOA;
+static volatile AT91PS_PIO pPIOB = AT91C_BASE_PIOB;
+static volatile AT91PS_SPI pSPI = AT91C_BASE_SPI0;
+static volatile AT91PS_PMC pPMC = AT91C_BASE_PMC;
+static volatile AT91PS_PDC pPDC = AT91C_BASE_PDC_SPI0;
+
+/* The PWM backlight control is non-linear on this board.
+ * We pick values here that make it look a bit more linear.
+ */
+#define PWM_TOP_VALUE		500
+#define PWM_BOTTOM_VALUE	200
+
+#define PWM_VALUE(x)	(PWM_BOTTOM_VALUE+(PWM_TOP_VALUE-PWM_BOTTOM_VALUE)*(x)/100)
+
+/* PWM configuration structure. The LCD Backlight is on PWM1/PB20 ie PWM2/PIN1 in ChibiOS speak */
+static const PWMConfig pwmcfg = {
+  1000000,		/* 1 MHz PWM clock frequency. Ignored as we are using PWM_MCK_DIV_n */
+  1000,			/* PWM period is 1000 cycles. */
+  NULL,
+  {
+   {PWM_MCK_DIV_1 | PWM_OUTPUT_ACTIVE_HIGH | PWM_OUTPUT_PIN1 | PWM_DISABLEPULLUP_PIN1, NULL},
+  },
+};
+
+static bool_t pwmRunning = FALSE;
+
+/**
+ * @brief   Initialise the board for the display.
+ * @notes	Performs the following functions:
+ *			1. initialise the spi port used by your display
+ *			2. initialise the reset pin (initial state not-in-reset)
+ *			3. initialise the chip select pin (initial state not-active)
+ *			4. initialise the backlight pin (initial state back-light off)
+ *
+ * @notapi
+ */
+static inline void init_board(GDisplay *g) {
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		// *********************************************************************************************
+		// InitSpi( )
+		//
+		// Sets up SPI channel 0 for communications to Nokia 6610 LCD Display
+		//
+		// I/O ports used:	PA2  = LCD Reset (set to low to reset)
+		//					PA12 = LCD chip select (set to low to select the LCD chip)
+		//					PA16 = SPI0_MISO Master In - Slave Out (not used in LCD interface)
+		//					PA17 = SPI0_MOSI Master Out - Slave In pin (Serial Data to LCD slave)
+		//					PA18 = SPI0_SPCK Serial Clock (to LCD slave)
+		//					PB20 = backlight control (normally PWM control, 1 = full on)
+		//
+		// *********************************************************************************************}
+
+		/* This code should really use the ChibiOS driver for these functions */
+
+		// Pin for backlight
+		pPIOB->PIO_CODR   = PIOB_LCD_BL_MASK;    // Set PB20 to LOW
+		pPIOB->PIO_OER    = PIOB_LCD_BL_MASK;    // Configure PB20 as output
+
+		// Reset pin
+		pPIOA->PIO_SODR   = PIOA_LCD_RESET_MASK;     // Set PA2 to HIGH
+		pPIOA->PIO_OER    = PIOA_LCD_RESET_MASK;     // Configure PA2 as output
+
+		// CS pin - this seems to be ignored
+		// pPIOA->PIO_SODR   = 1<<12;     // Set PA2 to HIGH
+		// pPIOA->PIO_OER    = 1<<12;     // Configure PA2 as output
+
+		// Init SPI0
+		// Disable the following pins from PIO control (will be used instead by the SPI0 peripheral)
+		// BIT12 = PA12 -> SPI0_NPCS0 chip select
+		// BIT16 = PA16 -> SPI0_MISO Master In - Slave Out (not used in LCD interface)
+		// BIT17 = PA17 -> SPI0_MOSI Master Out - Slave In pin (Serial Data to LCD slave)
+		// BIT18 = PA18 -> SPI0_SPCK Serial Clock (to LCD slave)
+		pPIOA->PIO_PDR = (1<<12) | (1<<16) | (1<<17) | (1<<18);
+		pPIOA->PIO_ASR = (1<<12) | (1<<16) | (1<<17) | (1<<18);
+		pPIOA->PIO_BSR = 0;
+
+		//enable the clock of SPI
+		pPMC->PMC_PCER = 1 << AT91C_ID_SPI0;
+
+		// Fixed mode
+		pSPI->SPI_CR      = 0x81;               //SPI Enable, Software reset
+		pSPI->SPI_CR      = 0x01;               //SPI Enable
+		pSPI->SPI_MR      = 0xE0011;			//Master mode, fixed select, disable decoder, PCS=1110
+		pSPI->SPI_CSR[0]  = 0x01010311;			//9bit, CPOL=1, ClockPhase=0, SCLK = 48Mhz/3 = 16MHz
+
+		/* Display backlight control at 100% */
+		pwmRunning = FALSE;
+		palSetPad(IOPORT2, PIOB_LCD_BL);
+		break;
+	}
+}
+
+static inline void post_init_board(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	if (state)
+		palClearPad(IOPORT1, PIOA_LCD_RESET);
+	else
+		palSetPad(IOPORT1, PIOA_LCD_RESET);
+}
+
+static inline void set_backlight(GDisplay *g, uint8_t percent) {
+	(void) g;
+	if (percent == 100) {
+		/* Turn the pin on - No PWM */
+		if (pwmRunning) {
+			pwmStop(&PWMD2);
+			pwmRunning = FALSE;
+		}
+		palSetPad(IOPORT2, PIOB_LCD_BL);
+	} else if (percent == 0) {
+		/* Turn the pin off - No PWM */
+		if (pwmRunning) {
+			pwmStop(&PWMD2);
+			pwmRunning = FALSE;
+		}
+		palClearPad(IOPORT2, PIOB_LCD_BL);
+	} else {
+		/* Use the PWM */
+		if (!pwmRunning) {
+			pwmStart(&PWMD2, &pwmcfg);
+			pwmRunning = TRUE;
+		}
+		pwmEnableChannel(&PWMD2, 0, PWM_VALUE(percent));
+	}
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void write_index(GDisplay *g, uint16_t index) {
+	(void) g;
+	// wait for the previous transfer to complete
+	while((pSPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0);
+	// send the command
+	pSPI->SPI_TDR = index & 0xFF;
+}
+
+static inline void write_data(GDisplay *g, uint16_t data) {
+	(void) g;
+	// wait for the previous transfer to complete
+	while((pSPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0);
+	// send the data
+	pSPI->SPI_TDR = data | 0x0100;
+}
+
+#endif /* _GDISP_LLD_BOARD_H */
diff --git a/boards/base/Olimex-SAM7EX256-GE12/readme.txt b/boards/base/Olimex-SAM7EX256-GE12/readme.txt
new file mode 100644
index 00000000..ebf1497a
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE12/readme.txt
@@ -0,0 +1,15 @@
+This directory contains the interface for the Olimex SAM7EX256 board
+running under ChibiOS.
+
+On this board uGFX currently supports:
+	- GDISP via the Nokia6610GE12 display 
+	- GADC via the AT91SAM7 driver
+	- GINPUT-dials via the GADC driver
+	- GINPUT-toggles via the Pal driver
+	- GAUDIN via the GADC driver
+
+Note there are two variants of this board - one with the GE8 display
+	and one with the GE12 display. This one is for the GE12 display.
+
+See the Olimex-SAM7EX256-GE8 board file directory for example Makefiles etc.
+Don't forget to change the example Makefile to point the GFX board file to the GE12 instead of the GE8.
diff --git a/boards/base/Olimex-SAM7EX256-GE8/board.mk b/boards/base/Olimex-SAM7EX256-GE8/board.mk
new file mode 100644
index 00000000..6abd9a33
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE8/board.mk
@@ -0,0 +1,8 @@
+GFXINC  += $(GFXLIB)/boards/base/Olimex-SAM7EX256-GE8
+GFXSRC  +=
+GFXDEFS += -DGFX_USE_OS_CHIBIOS=TRUE
+include $(GFXLIB)/drivers/gdisp/Nokia6610GE8/gdisp_lld.mk
+include $(GFXLIB)/drivers/gadc/AT91SAM7/gadc_lld.mk
+include $(GFXLIB)/drivers/ginput/dial/GADC/ginput_lld.mk
+include $(GFXLIB)/drivers/ginput/toggle/Pal/ginput_lld.mk
+include $(GFXLIB)/drivers/gaudin/gadc/gaudin_lld.mk
diff --git a/boards/base/Olimex-SAM7EX256-GE8/board_Nokia6610GE8.h b/boards/base/Olimex-SAM7EX256-GE8/board_Nokia6610GE8.h
new file mode 100644
index 00000000..c88dbe74
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE8/board_Nokia6610GE8.h
@@ -0,0 +1,195 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    boards/base/Olimex-SAM7EX256-GE8/board_Nokia6610GE8.h
+ * @brief   GDISP Graphic Driver subsystem board interface for the Olimex SAM7-EX256 board.
+ */
+
+#ifndef _GDISP_LLD_BOARD_H
+#define _GDISP_LLD_BOARD_H
+
+/*
+ * Set various display properties. These properties mostly depend on the exact controller chip you get.
+ * The defaults should work for most controllers.
+ */
+//#define GDISP_GE8_BROKEN_CONTROLLER		FALSE	// Uncomment this out if you have a controller thats not window wrap broken.
+//#define GDISP_SCREEN_HEIGHT				130		// The visible display height
+//#define GDISP_SCREEN_WIDTH				130		// The visible display width
+//#define GDISP_RAM_X_OFFSET				0		// The x offset of the visible area
+//#define GDISP_RAM_Y_OFFSET				2		// The y offset of the visible area
+//#define GDISP_SLEEP_SIZE					32		// The size of the sleep mode partial display
+//#define GDISP_SLEEP_POS					50		// The position of the sleep mode partial display
+//#define GDISP_INITIAL_CONTRAST			38		// The initial contrast percentage
+//#define GDISP_INITIAL_BACKLIGHT			100		// The initial backlight percentage
+
+// For a multiple display configuration we would put all this in a structure and then
+//	set g->board to that structure.
+
+// ******************************************************
+// Pointers to AT91SAM7X256 peripheral data structures
+// ******************************************************
+static volatile AT91PS_PIO pPIOA = AT91C_BASE_PIOA;
+static volatile AT91PS_PIO pPIOB = AT91C_BASE_PIOB;
+static volatile AT91PS_SPI pSPI = AT91C_BASE_SPI0;
+static volatile AT91PS_PMC pPMC = AT91C_BASE_PMC;
+static volatile AT91PS_PDC pPDC = AT91C_BASE_PDC_SPI0;
+
+/* The PWM backlight control is non-linear on this board.
+ * We pick values here that make it look a bit more linear.
+ */
+#define PWM_TOP_VALUE		500
+#define PWM_BOTTOM_VALUE	200
+
+#define PWM_VALUE(x)	(PWM_BOTTOM_VALUE+(PWM_TOP_VALUE-PWM_BOTTOM_VALUE)*(x)/100)
+
+/* PWM configuration structure. The LCD Backlight is on PWM1/PB20 ie PWM2/PIN1 in ChibiOS speak */
+static const PWMConfig pwmcfg = {
+  1000000,		/* 1 MHz PWM clock frequency. Ignored as we are using PWM_MCK_DIV_n */
+  1000,			/* PWM period is 1000 cycles. */
+  NULL,
+  {
+   {PWM_MCK_DIV_1 | PWM_OUTPUT_ACTIVE_HIGH | PWM_OUTPUT_PIN1 | PWM_DISABLEPULLUP_PIN1, NULL},
+  },
+};
+
+static bool_t pwmRunning = FALSE;
+
+/**
+ * @brief   Initialise the board for the display.
+ * @notes	Performs the following functions:
+ *			1. initialise the spi port used by your display
+ *			2. initialise the reset pin (initial state not-in-reset)
+ *			3. initialise the chip select pin (initial state not-active)
+ *			4. initialise the backlight pin (initial state back-light off)
+ *
+ * @notapi
+ */
+static inline void init_board(GDisplay *g) {
+
+	// As we are not using multiple displays we set g->board to NULL as we don't use it.
+	g->board = 0;
+
+	switch(g->controllerdisplay) {
+	case 0:											// Set up for Display 0
+		// *********************************************************************************************
+		// InitSpi( )
+		//
+		// Sets up SPI channel 0 for communications to Nokia 6610 LCD Display
+		//
+		// I/O ports used:	PA2  = LCD Reset (set to low to reset)
+		//					PA12 = LCD chip select (set to low to select the LCD chip)
+		//					PA16 = SPI0_MISO Master In - Slave Out (not used in LCD interface)
+		//					PA17 = SPI0_MOSI Master Out - Slave In pin (Serial Data to LCD slave)
+		//					PA18 = SPI0_SPCK Serial Clock (to LCD slave)
+		//					PB20 = backlight control (normally PWM control, 1 = full on)
+		//
+		// *********************************************************************************************}
+
+		/* This code should really use the ChibiOS driver for these functions */
+
+		// Pin for backlight
+		pPIOB->PIO_CODR   = PIOB_LCD_BL_MASK;    // Set PB20 to LOW
+		pPIOB->PIO_OER    = PIOB_LCD_BL_MASK;    // Configure PB20 as output
+
+		// Reset pin
+		pPIOA->PIO_SODR   = PIOA_LCD_RESET_MASK;     // Set PA2 to HIGH
+		pPIOA->PIO_OER    = PIOA_LCD_RESET_MASK;     // Configure PA2 as output
+
+		// CS pin - this seems to be ignored
+		// pPIOA->PIO_SODR   = 1<<12;     // Set PA2 to HIGH
+		// pPIOA->PIO_OER    = 1<<12;     // Configure PA2 as output
+
+		// Init SPI0
+		// Disable the following pins from PIO control (will be used instead by the SPI0 peripheral)
+		// BIT12 = PA12 -> SPI0_NPCS0 chip select
+		// BIT16 = PA16 -> SPI0_MISO Master In - Slave Out (not used in LCD interface)
+		// BIT17 = PA17 -> SPI0_MOSI Master Out - Slave In pin (Serial Data to LCD slave)
+		// BIT18 = PA18 -> SPI0_SPCK Serial Clock (to LCD slave)
+		pPIOA->PIO_PDR = (1<<12) | (1<<16) | (1<<17) | (1<<18);
+		pPIOA->PIO_ASR = (1<<12) | (1<<16) | (1<<17) | (1<<18);
+		pPIOA->PIO_BSR = 0;
+
+		//enable the clock of SPI
+		pPMC->PMC_PCER = 1 << AT91C_ID_SPI0;
+
+		// Fixed mode
+		pSPI->SPI_CR      = 0x81;               //SPI Enable, Software reset
+		pSPI->SPI_CR      = 0x01;               //SPI Enable
+		pSPI->SPI_MR      = 0xE0011;			//Master mode, fixed select, disable decoder, PCS=1110
+		pSPI->SPI_CSR[0]  = 0x01010311;			//9bit, CPOL=1, ClockPhase=0, SCLK = 48Mhz/3 = 16MHz
+
+		/* Display backlight control at 100% */
+		pwmRunning = FALSE;
+		palSetPad(IOPORT2, PIOB_LCD_BL);
+		break;
+	}
+}
+
+static inline void post_init_board(GDisplay *g) {
+	(void) g;
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+	(void) g;
+	if (state)
+		palClearPad(IOPORT1, PIOA_LCD_RESET);
+	else
+		palSetPad(IOPORT1, PIOA_LCD_RESET);
+}
+
+static inline void set_backlight(GDisplay *g, uint8_t percent) {
+	(void) g;
+	if (percent == 100) {
+		/* Turn the pin on - No PWM */
+		if (pwmRunning) {
+			pwmStop(&PWMD2);
+			pwmRunning = FALSE;
+		}
+		palSetPad(IOPORT2, PIOB_LCD_BL);
+	} else if (percent == 0) {
+		/* Turn the pin off - No PWM */
+		if (pwmRunning) {
+			pwmStop(&PWMD2);
+			pwmRunning = FALSE;
+		}
+		palClearPad(IOPORT2, PIOB_LCD_BL);
+	} else {
+		/* Use the PWM */
+		if (!pwmRunning) {
+			pwmStart(&PWMD2, &pwmcfg);
+			pwmRunning = TRUE;
+		}
+		pwmEnableChannel(&PWMD2, 0, PWM_VALUE(percent));
+	}
+}
+
+static inline void acquire_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void release_bus(GDisplay *g) {
+	(void) g;
+}
+
+static inline void write_index(GDisplay *g, uint16_t index) {
+	(void) g;
+	// wait for the previous transfer to complete
+	while((pSPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0);
+	// send the command
+	pSPI->SPI_TDR = index & 0xFF;
+}
+
+static inline void write_data(GDisplay *g, uint16_t data) {
+	(void) g;
+	// wait for the previous transfer to complete
+	while((pSPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0);
+	// send the data
+	pSPI->SPI_TDR = data | 0x0100;
+}
+
+#endif /* _GDISP_LLD_BOARD_H */
diff --git a/boards/base/Olimex-SAM7EX256-GE8/example/Makefile b/boards/base/Olimex-SAM7EX256-GE8/example/Makefile
new file mode 100644
index 00000000..d6161d5e
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE8/example/Makefile
@@ -0,0 +1,201 @@
+##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+  # If you are using gcc V4.5.1 or older then replace -g with -ggdb -gstabs+
+  # For debugging you probably want -O0 rather than -O2
+  USE_OPT = -O0 -g -fomit-frame-pointer -mabi=apcs-gnu
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+  USE_COPT = 
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+  USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+  USE_LINK_GC = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+  USE_THUMB = no
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+  USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths for ChibiOS
+CHIBIOS = ../ChibiOS
+include $(CHIBIOS)/boards/OLIMEX_SAM7_EX256/board.mk
+include $(CHIBIOS)/os/hal/platforms/AT91SAM7/platform.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/ports/GCC/ARM/AT91SAM7/port.mk
+include $(CHIBIOS)/os/kernel/kernel.mk
+
+# We define a non standard linker script here just to give us some more stack space
+# LDSCRIPT= $(PORTLD)/AT91SAM7X256.ld
+LDSCRIPT= linker.ld
+
+# Imported source files and paths for uGFX
+GFXLIB = ../uGFX
+include $(GFXLIB)/gfx.mk
+include $(GFXLIB)/boards/base/Olimex-SAM7EX256-GE8/board.mk
+
+# Where is our source code - alter these for your project.
+MYFILES = $(GFXLIB)/demos/modules/gdisp/basics
+MYCSRC  = $(MYFILES)/main.c
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(PORTSRC) \
+       $(KERNSRC) \
+       $(TESTSRC) \
+       $(HALSRC) \
+       $(PLATFORMSRC) \
+       $(BOARDSRC) \
+       $(GFXSRC) \
+       $(MYCSRC)
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+#       option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+#       option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+#       option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+#       option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(PORTASM)
+
+INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
+         $(HALINC) $(PLATFORMINC) $(BOARDINC) \
+         $(GFXINC) \
+         $(MYFILES)
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU  = arm7tdmi
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC   = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+#       runtime support makes code size explode.
+# If you are using gcc V4.5.1 or older then add -ggdb -gstabs+ to the LD line
+LD   = $(TRGT)gcc
+#LD   = $(TRGT)g++
+CP   = $(TRGT)objcopy
+AS   = $(TRGT)gcc -x assembler-with-cpp
+OD   = $(TRGT)objdump
+HEX  = $(CP) -O ihex
+BIN  = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of default section
+#
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS = $(GFXDEFS)
+
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS =
+
+# List all default directories to look for include files here
+DINCDIR =
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS =
+
+#
+# End of default section
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk
diff --git a/boards/base/Olimex-SAM7EX256-GE8/example/chconf.h b/boards/base/Olimex-SAM7EX256-GE8/example/chconf.h
new file mode 100644
index 00000000..6d012c3e
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE8/example/chconf.h
@@ -0,0 +1,542 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+                                      ---
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes ChibiOS/RT, without being obliged to provide
+    the source code for any proprietary components. See the file exception.txt
+    for full details of how and when the exception can be applied.
+*/
+
+/**
+ * @file    templates/chconf.h
+ * @brief   Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ *          contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ *          setting also defines the system tick time unit.
+ */
+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
+#define CH_FREQUENCY                    1000
+#endif
+
+/**
+ * @brief   Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ *          threads before preemption occurs. Setting this value to zero
+ *          disables the preemption for threads with equal priority and the
+ *          round robin becomes cooperative. Note that higher priority
+ *          threads can still preempt, the kernel is always preemptive.
+ *
+ * @note    Disabling the round robin preemption makes the kernel more compact
+ *          and generally faster.
+ */
+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
+#define CH_TIME_QUANTUM                 20
+#endif
+
+/**
+ * @brief   Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ *          then the whole available RAM is used. The core memory is made
+ *          available to the heap allocator and/or can be used directly through
+ *          the simplified core memory allocator.
+ *
+ * @note    In order to let the OS manage the whole RAM the linker script must
+ *          provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note    Requires @p CH_USE_MEMCORE.
+ */
+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
+#define CH_MEMCORE_SIZE                 0
+#endif
+
+/**
+ * @brief   Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ *          does not spawn the idle thread automatically. The application has
+ *          then the responsibility to do one of the following:
+ *          - Spawn a custom idle thread at priority @p IDLEPRIO.
+ *          - Change the main() thread priority to @p IDLEPRIO then enter
+ *            an endless loop. In this scenario the @p main() thread acts as
+ *            the idle thread.
+ *          .
+ * @note    Unless an idle thread is spawned the @p main() thread must not
+ *          enter a sleep state.
+ */
+#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
+#define CH_NO_IDLE_THREAD               FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ *          is used when two possible implementations exist.
+ *
+ * @note    This is not related to the compiler optimization options.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
+#define CH_OPTIMIZE_SPEED               TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
+#define CH_USE_REGISTRY                 TRUE
+#endif
+
+/**
+ * @brief   Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ *          the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
+#define CH_USE_WAITEXIT                 TRUE
+#endif
+
+/**
+ * @brief   Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES               TRUE
+#endif
+
+/**
+ * @brief   Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ *          priority rather than in FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special requirements.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES_PRIORITY      FALSE
+#endif
+
+/**
+ * @brief   Atomic semaphore API.
+ * @details If enabled then the semaphores the @p chSemSignalWait() API
+ *          is included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
+#define CH_USE_SEMSW                    TRUE
+#endif
+
+/**
+ * @brief   Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
+#define CH_USE_MUTEXES                  TRUE
+#endif
+
+/**
+ * @brief   Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_MUTEXES.
+ */
+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS                 TRUE
+#endif
+
+/**
+ * @brief   Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ *          specification are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_CONDVARS.
+ */
+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS_TIMEOUT         TRUE
+#endif
+
+/**
+ * @brief   Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS                   TRUE
+#endif
+
+/**
+ * @brief   Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ *          are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_EVENTS.
+ */
+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS_TIMEOUT           TRUE
+#endif
+
+/**
+ * @brief   Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES                 TRUE
+#endif
+
+/**
+ * @brief   Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ *          FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special requirements.
+ * @note    Requires @p CH_USE_MESSAGES.
+ */
+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES_PRIORITY        FALSE
+#endif
+
+/**
+ * @brief   Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ *          included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
+#define CH_USE_MAILBOXES                TRUE
+#endif
+
+/**
+ * @brief   I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
+#define CH_USE_QUEUES                   TRUE
+#endif
+
+/**
+ * @brief   Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
+#define CH_USE_MEMCORE                  TRUE
+#endif
+
+/**
+ * @brief   Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
+ *          @p CH_USE_SEMAPHORES.
+ * @note    Mutexes are recommended.
+ */
+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_HEAP                     TRUE
+#endif
+
+/**
+ * @brief   C-runtime allocator.
+ * @details If enabled the the heap allocator APIs just wrap the C-runtime
+ *          @p malloc() and @p free() functions.
+ *
+ * @note    The default is @p FALSE.
+ * @note    Requires @p CH_USE_HEAP.
+ * @note    The C-runtime may or may not require @p CH_USE_MEMCORE, see the
+ *          appropriate documentation.
+ */
+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_MALLOC_HEAP              FALSE
+#endif
+
+/**
+ * @brief   Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
+#define CH_USE_MEMPOOLS                 TRUE
+#endif
+
+/**
+ * @brief   Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_WAITEXIT.
+ * @note    Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ */
+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
+#define CH_USE_DYNAMIC                  TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ *          at runtime.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_SYSTEM_STATE_CHECK       FALSE
+#endif
+
+/**
+ * @brief   Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ *          parameters are activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_CHECKS            FALSE
+#endif
+
+/**
+ * @brief   Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ *          activated. This includes consistency checks inside the kernel,
+ *          runtime anomalies and port-defined checks.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_ASSERTS           FALSE
+#endif
+
+/**
+ * @brief   Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ *          activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_TRACE             FALSE
+#endif
+
+/**
+ * @brief   Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note    The default is @p FALSE.
+ * @note    The stack check is performed in a architecture/port dependent way.
+ *          It may not be implemented or some ports.
+ * @note    The default failure mode is to halt the system with the global
+ *          @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_STACK_CHECK       FALSE
+#endif
+
+/**
+ * @brief   Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ *          value when a thread is created. This can be useful for the
+ *          runtime measurement of the used stack.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
+#define CH_DBG_FILL_THREADS             FALSE
+#endif
+
+/**
+ * @brief   Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p Thread structure that
+ *          counts the system ticks occurred while executing the thread.
+ *
+ * @note    The default is @p TRUE.
+ * @note    This debug option is defaulted to TRUE because it is required by
+ *          some test cases into the test suite.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
+#define CH_DBG_THREADS_PROFILING        TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Threads descriptor structure extension.
+ * @details User fields added to the end of the @p Thread structure.
+ */
+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define THREAD_EXT_FIELDS                                                   \
+  /* Add threads custom fields here.*/
+#endif
+
+/**
+ * @brief   Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note    It is invoked from within @p chThdInit() and implicitly from all
+ *          the threads creation APIs.
+ */
+#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_INIT_HOOK(tp) {                                          \
+  /* Add threads initialization code here.*/                                \
+}
+#endif
+
+/**
+ * @brief   Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note    It is inserted into lock zone.
+ * @note    It is also invoked when the threads simply return in order to
+ *          terminate.
+ */
+#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_EXIT_HOOK(tp) {                                          \
+  /* Add threads finalization code here.*/                                  \
+}
+#endif
+
+/**
+ * @brief   Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
+#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \
+  /* System halt code here.*/                                               \
+}
+#endif
+
+/**
+ * @brief   Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
+#define IDLE_LOOP_HOOK() {                                                  \
+  /* Idle loop code here.*/                                                 \
+}
+#endif
+
+/**
+ * @brief   System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ *          after processing the virtual timers queue.
+ */
+#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_TICK_EVENT_HOOK() {                                          \
+  /* System tick event code here.*/                                         \
+}
+#endif
+
+/**
+ * @brief   System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ *          the system is halted.
+ */
+#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_HALT_HOOK() {                                                \
+  /* System halt code here.*/                                               \
+}
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h).    */
+/*===========================================================================*/
+
+#endif  /* _CHCONF_H_ */
+
+/** @} */
diff --git a/boards/base/Olimex-SAM7EX256-GE8/example/halconf.h b/boards/base/Olimex-SAM7EX256-GE8/example/halconf.h
new file mode 100644
index 00000000..db88d41b
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE8/example/halconf.h
@@ -0,0 +1,360 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+                                      ---
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes ChibiOS/RT, without being obliged to provide
+    the source code for any proprietary components. See the file exception.txt
+    for full details of how and when the exception can be applied.
+*/
+
+/**
+ * @file    templates/halconf.h
+ * @brief   HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ *          various device drivers from your application. You may also use
+ *          this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief   Enables the TM subsystem.
+ */
+#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
+#define HAL_USE_TM                  FALSE
+#endif
+
+/**
+ * @brief   Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL                 TRUE
+#endif
+
+/**
+ * @brief   Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC                 TRUE
+#endif
+
+/**
+ * @brief   Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN                 FALSE
+#endif
+
+/**
+ * @brief   Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT                 FALSE
+#endif
+
+/**
+ * @brief   Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT                 FALSE
+#endif
+
+/**
+ * @brief   Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C                 FALSE
+#endif
+
+/**
+ * @brief   Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU                 FALSE
+#endif
+
+/**
+ * @brief   Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI             FALSE
+#endif
+
+/**
+ * @brief   Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM                 TRUE
+#define PWM_USE_PWM1				FALSE
+#define PWM_USE_PWM2				TRUE
+#define PWM_USE_PWM3				FALSE
+#define PWM_USE_PWM4				FALSE
+#endif
+
+/**
+ * @brief   Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL              FALSE
+#endif
+
+/**
+ * @brief   Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB          FALSE
+#endif
+
+/**
+ * @brief   Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI                 TRUE
+#endif
+
+/**
+ * @brief   Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART                FALSE
+#endif
+
+/**
+ * @brief   Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB                 FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables synchronous APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT                TRUE
+#endif
+
+/**
+ * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE          TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY           FALSE
+#endif
+
+/**
+ * @brief   Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS              TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings.                                          */
+/*===========================================================================*/
+
+/**
+ * @brief   Block size for MMC transfers.
+ */
+#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__)
+#define MMC_SECTOR_SIZE             512
+#endif
+
+/**
+ * @brief   Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ *          routines releasing some extra CPU time for the threads with
+ *          lower priority, this may slow down the driver a bit however.
+ *          This option is recommended also if the SPI driver does not
+ *          use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING            TRUE
+#endif
+
+/**
+ * @brief   Number of positive insertion queries before generating the
+ *          insertion event.
+ */
+#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__)
+#define MMC_POLLING_INTERVAL        10
+#endif
+
+/**
+ * @brief   Interval, in milliseconds, between insertion queries.
+ */
+#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__)
+#define MMC_POLLING_DELAY           10
+#endif
+
+/**
+ * @brief   Uses the SPI polled API for small data transfers.
+ * @details Polled transfers usually improve performance because it
+ *          saves two context switches and interrupt servicing. Note
+ *          that this option has no effect on large transfers which
+ *          are always performed using DMAs/IRQs.
+ */
+#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__)
+#define MMC_USE_SPI_POLLING         TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Number of initialization attempts before rejecting the card.
+ * @note    Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY              100
+#endif
+
+/**
+ * @brief   Include support for MMC cards.
+ * @note    MMC support is not yet implemented so this option must be kept
+ *          at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT             FALSE
+#endif
+
+/**
+ * @brief   Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ *          routines releasing some extra CPU time for the threads with
+ *          lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING            TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings.                                           */
+/*===========================================================================*/
+
+/**
+ * @brief   Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ *          default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE      38400
+#endif
+
+/**
+ * @brief   Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ *          buffers depending on the requirements of your application.
+ * @note    The default is 64 bytes for both the transmission and receive
+ *          buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE         16
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables synchronous APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT                TRUE
+#endif
+
+/**
+ * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/boards/base/Olimex-SAM7EX256-GE8/example/linker.ld b/boards/base/Olimex-SAM7EX256-GE8/example/linker.ld
new file mode 100644
index 00000000..c36a07a3
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE8/example/linker.ld
@@ -0,0 +1,105 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * AT91SAM7X256 memory setup.
+ */
+__und_stack_size__	= 0x0004;
+__abt_stack_size__	= 0x0004;
+__fiq_stack_size__	= 0x0010;
+__irq_stack_size__	= 0x0080;
+__svc_stack_size__	= 0x0004;
+__sys_stack_size__	= 0x0400;
+__stacks_total_size__	= __und_stack_size__ + __abt_stack_size__ + __fiq_stack_size__ + __irq_stack_size__ + __svc_stack_size__ + __sys_stack_size__;
+
+MEMORY
+{
+    flash : org = 0x100000, len = 256k
+    ram : org = 0x200020, len = 64k - 0x20
+}
+
+__ram_start__		= ORIGIN(ram);
+__ram_size__		= LENGTH(ram);
+__ram_end__		= __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+	. = 0;
+
+	.text : ALIGN(16) SUBALIGN(16)
+	{
+        _text = .;
+        KEEP(*(vectors))
+        *(.text)
+        *(.text.*)
+        *(.rodata)
+        *(.rodata.*)
+        *(.glue_7t)
+        *(.glue_7)
+        *(.gcc*)
+        *(.ctors)
+        *(.dtors)
+    } > flash
+
+    .ARM.extab : {*(.ARM.extab* .gnu.linkonce.armextab.*)}
+
+    __exidx_start = .;
+    .ARM.exidx : {*(.ARM.exidx* .gnu.linkonce.armexidx.*)} > flash
+    __exidx_end = .;
+
+    .eh_frame_hdr : {*(.eh_frame_hdr)}
+
+    .eh_frame : ONLY_IF_RO {*(.eh_frame)}
+
+    . = ALIGN(4);
+    _etext = .;
+    _textdata = _etext;
+
+    .data :
+    {
+        _data = .;
+        *(.data)
+        . = ALIGN(4);
+        *(.data.*)
+        . = ALIGN(4);
+        *(.ramtext)
+        . = ALIGN(4);
+        _edata = .;
+    } > ram AT > flash
+
+    .bss :
+    {
+        _bss_start = .;
+        *(.bss)
+        . = ALIGN(4);
+        *(.bss.*)
+        . = ALIGN(4);
+        *(COMMON)
+        . = ALIGN(4);
+        _bss_end = .;
+    } > ram    
+}
+
+PROVIDE(end = .);
+_end = .;
+
+__heap_base__              = _end;
+__heap_end__               = __ram_end__ - __stacks_total_size__;
+__main_thread_stack_base__ = __ram_end__ - __stacks_total_size__;
diff --git a/boards/base/Olimex-SAM7EX256-GE8/example/mcuconf.h b/boards/base/Olimex-SAM7EX256-GE8/example/mcuconf.h
new file mode 100644
index 00000000..a9a0fea7
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE8/example/mcuconf.h
@@ -0,0 +1,71 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+                                      ---
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes ChibiOS/RT, without being obliged to provide
+    the source code for any proprietary components. See the file exception.txt
+    for full details of how and when the exception can be applied.
+*/
+
+/*
+ * AT91SAM7 drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the driver
+ * is enabled in halconf.h.
+ */
+
+/*
+ * ADC driver system settings.
+ */
+
+/*
+ * CAN driver system settings.
+ */
+
+/*
+ * MAC driver system settings.
+ */
+#define MAC_TRANSMIT_BUFFERS        2
+#define MAC_RECEIVE_BUFFERS         2
+#define MAC_BUFFERS_SIZE            1518
+#define EMAC_INTERRUPT_PRIORITY     (AT91C_AIC_PRIOR_HIGHEST - 3)
+
+/*
+ * PWM driver system settings.
+ */
+
+/*
+ * SERIAL driver system settings.
+ */
+#define USE_SAM7_USART0             TRUE
+#define USE_SAM7_USART1             TRUE
+#define SAM7_USART0_PRIORITY        (AT91C_AIC_PRIOR_HIGHEST - 2)
+#define SAM7_USART1_PRIORITY        (AT91C_AIC_PRIOR_HIGHEST - 2)
+
+/*
+ * SPI driver system settings.
+ */
+#define USE_AT91SAM7_SPI            FALSE
+#define AT91SAM7_SPI_USE_SPI0       TRUE
+#define AT91SAM7_SPI_USE_SPI1       FALSE
+#define AT91SAM7_SPI0_PRIORITY      (AT91C_AIC_PRIOR_HIGHEST - 1)
+#define AT91SAM7_SPI1_PRIORITY      (AT91C_AIC_PRIOR_HIGHEST - 1)
diff --git a/boards/base/Olimex-SAM7EX256-GE8/example/openocd.cfg b/boards/base/Olimex-SAM7EX256-GE8/example/openocd.cfg
new file mode 100644
index 00000000..8c58e6f0
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE8/example/openocd.cfg
@@ -0,0 +1,75 @@
+# This is a script file for OpenOCD 0.7.0
+#
+# It is set up for the Olimex SAM7EX256 board using the Olimex Tiny-H JTAG adaptor.
+#
+# Assuming the current directory is your project directory containing this openocd.cfg file...
+#
+# To program your device:
+#
+#	openocd -f openocd.cfg -c "Burn yourfile.bin" -c shutdown
+#
+# To debug your device:
+#
+#	openocd
+#	(This will run openocd in gdb server debug mode. Leave it running in the background)
+#
+#	gdb yourfile.elf
+#	(To start gdb. Then run the following commands in gdb...)
+#
+#	target remote 127.0.0.1:3333
+#	monitor Debug
+#	stepi
+#	(This last stepi resynchronizes gdb).
+#
+# If you want to reprogram from within gdb:
+#
+#	monitor Burn yourfile.bin
+#
+
+echo ""
+echo "##### Loading debugger..."
+source [find interface/olimex-arm-usb-tiny-h.cfg]
+#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+
+echo ""
+echo "##### Loading CPU..."
+source [find target/at91sam7x256.cfg]
+
+echo ""
+echo "##### Configuring..."
+jtag_rclk 3000
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+# flash protect 0 0 1 off
+#gdb_breakpoint_override hard
+arm7_9 dbgrq enable
+
+proc Debug { } {
+	echo ""
+	echo "##### Debug Session Connected..."
+	soft_reset_halt
+	reg pc 0x00100000
+	echo "Ready..."
+}
+
+proc Burn {file} {
+	echo ""
+	echo "##### Burning $file to device..."
+	halt
+	flash write_image erase unlock $file 0x00100000
+	reset
+	echo "Burning Complete!"
+}
+
+echo ""
+echo "##### Leaving Configuration Mode..."
+init
+soft_reset_halt
+$_TARGETNAME invoke-event reset-init
+flash probe 0
+flash banks
+
+echo ""
+echo "##### Waiting for debug connections..."
+
+
diff --git a/boards/base/Olimex-SAM7EX256-GE8/example/readme.txt b/boards/base/Olimex-SAM7EX256-GE8/example/readme.txt
new file mode 100644
index 00000000..a357dc52
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE8/example/readme.txt
@@ -0,0 +1,3 @@
+Copy these files into your own project directory and alter them to suite.
+
+In particular look at the MYFILES definition and the MYCSRC definition.
\ No newline at end of file
diff --git a/boards/base/Olimex-SAM7EX256-GE8/gadc_lld_board.h b/boards/base/Olimex-SAM7EX256-GE8/gadc_lld_board.h
new file mode 100644
index 00000000..fef861e5
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE8/gadc_lld_board.h
@@ -0,0 +1,29 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    boards/base/Olimex-SAM7EX256-GE8/gadc_lld_board.h
+ * @brief   GADC Driver config file.
+ */
+
+#ifndef _GADC_LLD_BOARD_H
+#define _GADC_LLD_BOARD_H
+
+#if GFX_USE_GADC
+
+/*===========================================================================*/
+/* Analogue devices on this board                                            */
+/*===========================================================================*/
+
+#define GADC_PHYSDEV_MICROPHONE			0x00000080
+#define GADC_PHYSDEV_DIAL				0x00000040
+#define GADC_PHYSDEV_TEMPERATURE		0x00000020
+
+#endif	/* GFX_USE_GADC */
+
+#endif	/* _GADC_LLD_BOARD_H */
+
diff --git a/boards/base/Olimex-SAM7EX256-GE8/gaudin_lld_board.h b/boards/base/Olimex-SAM7EX256-GE8/gaudin_lld_board.h
new file mode 100644
index 00000000..632f0659
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE8/gaudin_lld_board.h
@@ -0,0 +1,33 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    boards/base/Olimex-SAM7EX256-GE8/gaudin_lld_board.h
+ * @brief   GAUDIN Driver board config file for the Olimex SAM7EX256 board
+ */
+
+#ifndef _GAUDIN_LLD_BOARD_H
+#define _GAUDIN_LLD_BOARD_H
+
+/*===========================================================================*/
+/* Audio inputs on this board                                                */
+/*===========================================================================*/
+
+#define GAUDIN_NUM_CHANNELS					1
+
+/**
+ * The list of audio channels and their uses
+ */
+#define	GAUDIN_MICROPHONE					0
+
+#ifdef GAUDIN_LLD_IMPLEMENTATION
+	static uint32_t gaudin_lld_physdevs[GAUDIN_NUM_CHANNELS] = {
+			GADC_PHYSDEV_MICROPHONE,
+			};
+#endif
+
+#endif	/* _GAUDIN_LLD_BOARD_H */
diff --git a/boards/base/Olimex-SAM7EX256-GE8/ginput_lld_dial_board.h b/boards/base/Olimex-SAM7EX256-GE8/ginput_lld_dial_board.h
new file mode 100644
index 00000000..c0d3ab3f
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE8/ginput_lld_dial_board.h
@@ -0,0 +1,30 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    boards/base/Olimex-SAM7EX256-GE8/ginput_lld_dial_board.h
+ * @brief   GINPUT Dial Driver config file.
+ */
+
+#ifndef _GINPUT_LLD_DIAL_BOARD_H
+#define _GINPUT_LLD_DIAL_BOARD_H
+
+#if GFX_USE_GINPUT && GINPUT_NEED_DIAL
+
+/*===========================================================================*/
+/* Analogue devices on this board                                            */
+/*===========================================================================*/
+
+#define GINPUT_DIAL_NUM_PORTS			1
+#define GINPUT_DIAL_DEVICE0				GADC_PHYSDEV_DIAL
+#define GINPUT_DIAL_POLL_PERIOD			200
+#define GINPUT_DIAL_CYCLE_POLL			FALSE
+
+#endif	/* GFX_USE_GINPUT && GINPUT_NEED_DIAL */
+
+#endif	/* _GINPUT_LLD_DIAL_BOARD_H */
+
diff --git a/boards/base/Olimex-SAM7EX256-GE8/ginput_lld_toggle_board.h b/boards/base/Olimex-SAM7EX256-GE8/ginput_lld_toggle_board.h
new file mode 100644
index 00000000..39e7837a
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE8/ginput_lld_toggle_board.h
@@ -0,0 +1,40 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/**
+ * @file    boards/base/Olimex-SAM7EX256-GE8/ginput_lld_toggle_board.h
+ * @brief   GINPUT Toggle low level driver source for the ChibiOS PAL hardware on the Olimex SAM7EX256 board.
+ */
+
+#ifndef _GDISP_LLD_TOGGLE_BOARD_H
+#define _GDISP_LLD_TOGGLE_BOARD_H
+
+#define GINPUT_TOGGLE_NUM_PORTS			7			// The total number of toggle inputs
+#define GINPUT_TOGGLE_CONFIG_ENTRIES	2			// The total number of GToggleConfig entries
+
+#define GINPUT_TOGGLE_SW1			0				// Switch 1
+#define GINPUT_TOGGLE_SW2			1				// Switch 2
+#define GINPUT_TOGGLE_LEFT			2				// Joystick Left
+#define GINPUT_TOGGLE_DOWN			3				// Joystick Down
+#define GINPUT_TOGGLE_UP			4				// Joystick Up
+#define GINPUT_TOGGLE_RIGHT			5				// Joystick Right
+#define GINPUT_TOGGLE_CENTER		6				// Joystick Center
+
+#define GINPUT_TOGGLE_DECLARE_STRUCTURE()											\
+	const GToggleConfig GInputToggleConfigTable[GINPUT_TOGGLE_CONFIG_ENTRIES] = {	\
+		{AT91C_BASE_PIOB,								/* Switch 1 and Switch 2 */	\
+			PIOB_SW1_MASK|PIOB_SW2_MASK,											\
+			PIOB_SW1_MASK|PIOB_SW2_MASK,											\
+			PAL_MODE_INPUT},														\
+		{AT91C_BASE_PIOA,								/* B1..4 Joystick */		\
+			PIOA_B1_MASK|PIOA_B2_MASK|PIOA_B3_MASK|PIOA_B4_MASK|PIOA_B5_MASK,		\
+			PIOA_B1_MASK|PIOA_B2_MASK|PIOA_B3_MASK|PIOA_B4_MASK|PIOA_B5_MASK,		\
+			PAL_MODE_INPUT},														\
+	}
+
+#endif /* _GDISP_LLD_TOGGLE_BOARD_H */
+
diff --git a/boards/base/Olimex-SAM7EX256-GE8/readme.txt b/boards/base/Olimex-SAM7EX256-GE8/readme.txt
new file mode 100644
index 00000000..01b3f8b4
--- /dev/null
+++ b/boards/base/Olimex-SAM7EX256-GE8/readme.txt
@@ -0,0 +1,14 @@
+This directory contains the interface for the Olimex SAM7EX256 board
+running under ChibiOS.
+
+On this board uGFX currently supports:
+	- GDISP via the Nokia6610GE8 display 
+	- GADC via the AT91SAM7 driver
+	- GINPUT-dials via the GADC driver
+	- GINPUT-toggles via the Pal driver
+	- GAUDIN via the GADC driver
+
+Note there are two variants of this board - one with the GE8 display
+	and one with the GE12 display. This one is for the GE8 display.
+	
+There is an example Makefile and project in the examples directory.
diff --git a/boards/base/Win32/board.mk b/boards/base/Win32/board.mk
new file mode 100644
index 00000000..be5740ef
--- /dev/null
+++ b/boards/base/Win32/board.mk
@@ -0,0 +1,3 @@
+GFXINC  += $(GFXLIB)/boards/base/Win32
+GFXSRC  +=
+include $(GFXLIB)/drivers/multiple/Win32/gdisp_lld.mk
diff --git a/boards/base/Win32/example/Makefile b/boards/base/Win32/example/Makefile
new file mode 100644
index 00000000..66d4b918
--- /dev/null
+++ b/boards/base/Win32/example/Makefile
@@ -0,0 +1,195 @@
+#
+#       !!!! Do NOT edit this makefile with an editor which replace tabs by spaces !!!!
+#
+##############################################################################################
+#
+# On command line:
+#
+# make all = Create project
+#
+# make clean = Clean project files.
+#
+# To rebuild project do "make clean" and "make all".
+#
+
+##############################################################################################
+# Start of default section
+#
+
+CC   = i686-pc-mingw32-gcc -g
+
+# Turn ChibiOS simimulator on or off - uGFX doesn't need it but you might for other purposes.
+USE_CHIBIOS=no
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS =
+
+# List all default directories to look for include files here
+DINCDIR =
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS = -lws2_32 -lgdi32
+
+# Make sure this empty for now
+SRC = 
+
+#
+# End of default section
+##############################################################################################
+
+##############################################################################################
+# Start of user section
+#
+
+# Define project name here
+PROJECT = uGFX
+
+# Imported source files and paths for uGFX
+GFXLIB = ../uGFX
+include $(GFXLIB)/gfx.mk
+include $(GFXLIB)/boards/base/Win32/board.mk
+
+# Imported source files and paths for ChibiOS
+ifeq ($(USE_CHIBIOS),yes)
+	CHIBIOS = ../ChibiOS
+	include $(CHIBIOS)/boards/simulator/board.mk
+	include ${CHIBIOS}/os/hal/hal.mk
+	include ${CHIBIOS}/os/hal/platforms/Win32/platform.mk
+	include ${CHIBIOS}/os/ports/GCC/SIMIA32/port.mk
+	include ${CHIBIOS}/os/kernel/kernel.mk
+	DDEFS += -DSIMULATOR -DSHELL_USE_IPRINTF=FALSE
+	UINCDIR += $(PORTINC) $(KERNINC) $(TESTINC) \
+	          $(HALINC) $(PLATFORMINC) $(BOARDINC)
+	#          ${CHIBIOS}/os/various
+	SRC  += ${PORTSRC} \
+	       ${KERNSRC} \
+	       ${TESTSRC} \
+	       ${HALSRC} \
+	       ${PLATFORMSRC} \
+	       $(BOARDSRC)
+	GFXDEFS += -DGFX_USE_OS_CHIBIOS=TRUE
+else
+	GFXDEFS += -DGFX_USE_OS_WIN32=TRUE
+endif
+
+# Where is our source code - alter these for your project.
+MYFILES = $(GFXLIB)/demos/modules/gdisp/basics
+MYCSRC  = $(MYFILES)/main.c
+
+# List C source files here
+SRC  += ${GFXSRC} \
+	   ${MYCSRC}
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS = ${GFXDEFS}
+
+# List all user directories here
+UINCDIR = ${GFXINC} \
+		  ${MYFILES}
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+# Define optimisation level here
+#OPT = -ggdb -O2 -fomit-frame-pointer
+OPT = -ggdb -O0 -fomit-frame-pointer
+
+#
+# End of user defines
+##############################################################################################
+
+
+# Output directory and files
+ifeq ($(BUILDDIR),)
+  BUILDDIR = .build
+endif
+ifeq ($(BUILDDIR),.)
+  BUILDDIR = .build
+endif
+
+OBJDIR    = $(BUILDDIR)/obj
+LSTDIR    = $(BUILDDIR)/lst
+MAPDIR    = $(BUILDDIR)/map
+
+INCDIR  = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR))
+LIBDIR  = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+DEFS    = $(DDEFS) $(UDEFS)
+ADEFS   = $(DADEFS) $(UADEFS)
+COBJ	= $(addprefix $(OBJDIR)/, $(SRC:.c=.o))
+AOBJ	= $(addprefix $(OBJDIR)/, $(ASRC:.s=.o))
+OBJS    = $(AOBJ) $(COBJ)
+LIBS    = $(DLIBS) $(ULIBS)
+
+LDFLAGS = -Wl,-Map=$(MAPDIR)/$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR)
+CPFLAGS = $(OPT) -Wall -Wextra -Wstrict-prototypes -fverbose-asm -Wa,-alms=$(LSTDIR)/$(<:.c=.lst) $(DEFS)
+
+# Generate dependency information
+CPFLAGS += -MD -MP -MF .dep/$(@F).d
+
+#
+# makefile rules
+#
+
+all: $(BUILDDIR) $(OBJS) $(BUILDDIR)/$(PROJECT).exe MAKE_ALL_RULE_HOOK
+
+MAKE_ALL_RULE_HOOK:
+
+$(BUILDDIR) $(OBJDIR) $(LSTDIR):
+	mkdir -p $(OBJDIR)
+	mkdir -p $(LSTDIR)
+	mkdir -p $(MAPDIR)
+ifneq ($(USE_VERBOSE_COMPILE),yes)
+	@echo Compiler Options - $(CC) -c $(CPFLAGS) -I. $(INCDIR) main.c -o $(OBJDIR)/main.o
+	@echo
+endif
+
+$(OBJDIR)/%.o : %.c
+	@mkdir -p $(dir $@)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(CC) -c $(CPFLAGS) -I. $(INCDIR) $< -o $@
+else
+	@echo Compiling $<
+	@$(CC) -c $(CPFLAGS) -I. $(INCDIR) $< -o $@
+endif
+
+$(OBJDIR)/%.o : %.s
+	@mkdir -p $(dir $@)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(AS) -c $(ASFLAGS) -I. $(INCDIR) $< -o $@
+else
+	@echo Compiling $<
+	@$(AS) -c $(ASFLAGS) -I. $(INCDIR) $< -o $@
+endif
+
+%.exe: $(OBJS)
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+	@echo
+	$(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+else
+	@echo Linking $@
+	@$(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+endif
+
+gcov:
+	-mkdir gcov
+	$(COV) -u $(subst /,\,$(SRC))
+	-mv *.gcov ./gcov
+
+clean:
+	-rm -fR .build
+	-rm -fR .dep
+
+#
+# Include the dependency files, should be the last of the makefile
+#
+-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
+
+# *** EOF ***
diff --git a/boards/base/Win32/example/chconf.h b/boards/base/Win32/example/chconf.h
new file mode 100644
index 00000000..759f6be8
--- /dev/null
+++ b/boards/base/Win32/example/chconf.h
@@ -0,0 +1,536 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    templates/chconf.h
+ * @brief   Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ *          contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ *          setting also defines the system tick time unit.
+ */
+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
+#define CH_FREQUENCY                    1000
+#endif
+
+/**
+ * @brief   Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ *          threads before preemption occurs. Setting this value to zero
+ *          disables the preemption for threads with equal priority and the
+ *          round robin becomes cooperative. Note that higher priority
+ *          threads can still preempt, the kernel is always preemptive.
+ *
+ * @note    Disabling the round robin preemption makes the kernel more compact
+ *          and generally faster.
+ */
+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
+#define CH_TIME_QUANTUM                 20
+#endif
+
+/**
+ * @brief   Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ *          then the whole available RAM is used. The core memory is made
+ *          available to the heap allocator and/or can be used directly through
+ *          the simplified core memory allocator.
+ *
+ * @note    In order to let the OS manage the whole RAM the linker script must
+ *          provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note    Requires @p CH_USE_MEMCORE.
+ */
+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
+#define CH_MEMCORE_SIZE                 0x20000
+#endif
+
+/**
+ * @brief   Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ *          does not spawn the idle thread automatically. The application has
+ *          then the responsibility to do one of the following:
+ *          - Spawn a custom idle thread at priority @p IDLEPRIO.
+ *          - Change the main() thread priority to @p IDLEPRIO then enter
+ *            an endless loop. In this scenario the @p main() thread acts as
+ *            the idle thread.
+ *          .
+ * @note    Unless an idle thread is spawned the @p main() thread must not
+ *          enter a sleep state.
+ */
+#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
+#define CH_NO_IDLE_THREAD               FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ *          is used when two possible implementations exist.
+ *
+ * @note    This is not related to the compiler optimization options.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
+#define CH_OPTIMIZE_SPEED               TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
+#define CH_USE_REGISTRY                 TRUE
+#endif
+
+/**
+ * @brief   Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ *          the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
+#define CH_USE_WAITEXIT                 TRUE
+#endif
+
+/**
+ * @brief   Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES               TRUE
+#endif
+
+/**
+ * @brief   Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ *          priority rather than in FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special requirements.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES_PRIORITY      FALSE
+#endif
+
+/**
+ * @brief   Atomic semaphore API.
+ * @details If enabled then the semaphores the @p chSemSignalWait() API
+ *          is included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
+#define CH_USE_SEMSW                    TRUE
+#endif
+
+/**
+ * @brief   Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
+#define CH_USE_MUTEXES                  TRUE
+#endif
+
+/**
+ * @brief   Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_MUTEXES.
+ */
+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS                 TRUE
+#endif
+
+/**
+ * @brief   Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ *          specification are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_CONDVARS.
+ */
+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS_TIMEOUT         TRUE
+#endif
+
+/**
+ * @brief   Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS                   TRUE
+#endif
+
+/**
+ * @brief   Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ *          are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_EVENTS.
+ */
+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS_TIMEOUT           TRUE
+#endif
+
+/**
+ * @brief   Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES                 TRUE
+#endif
+
+/**
+ * @brief   Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ *          FIFO order.
+ *
+ * @note    The default is @p FALSE. Enable this if you have special requirements.
+ * @note    Requires @p CH_USE_MESSAGES.
+ */
+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES_PRIORITY        FALSE
+#endif
+
+/**
+ * @brief   Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ *          included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
+#define CH_USE_MAILBOXES                TRUE
+#endif
+
+/**
+ * @brief   I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
+#define CH_USE_QUEUES                   TRUE
+#endif
+
+/**
+ * @brief   Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
+#define CH_USE_MEMCORE                  TRUE
+#endif
+
+/**
+ * @brief   Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
+ *          @p CH_USE_SEMAPHORES.
+ * @note    Mutexes are recommended.
+ */
+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_HEAP                     TRUE
+#endif
+
+/**
+ * @brief   C-runtime allocator.
+ * @details If enabled the the heap allocator APIs just wrap the C-runtime
+ *          @p malloc() and @p free() functions.
+ *
+ * @note    The default is @p FALSE.
+ * @note    Requires @p CH_USE_HEAP.
+ * @note    The C-runtime may or may not require @p CH_USE_MEMCORE, see the
+ *          appropriate documentation.
+ */
+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_MALLOC_HEAP              FALSE
+#endif
+
+/**
+ * @brief   Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
+#define CH_USE_MEMPOOLS                 TRUE
+#endif
+
+/**
+ * @brief   Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ *          in the kernel.
+ *
+ * @note    The default is @p TRUE.
+ * @note    Requires @p CH_USE_WAITEXIT.
+ * @note    Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ */
+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
+#define CH_USE_DYNAMIC                  TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ *          at runtime.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_SYSTEM_STATE_CHECK       FALSE
+#endif
+
+/**
+ * @brief   Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ *          parameters are activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_CHECKS            FALSE
+#endif
+
+/**
+ * @brief   Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ *          activated. This includes consistency checks inside the kernel,
+ *          runtime anomalies and port-defined checks.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_ASSERTS           FALSE
+#endif
+
+/**
+ * @brief   Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ *          activated.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_TRACE             FALSE
+#endif
+
+/**
+ * @brief   Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note    The default is @p FALSE.
+ * @note    The stack check is performed in a architecture/port dependent way.
+ *          It may not be implemented or some ports.
+ * @note    The default failure mode is to halt the system with the global
+ *          @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_STACK_CHECK       FALSE
+#endif
+
+/**
+ * @brief   Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ *          value when a thread is created. This can be useful for the
+ *          runtime measurement of the used stack.
+ *
+ * @note    The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
+#define CH_DBG_FILL_THREADS             FALSE
+#endif
+
+/**
+ * @brief   Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p Thread structure that
+ *          counts the system ticks occurred while executing the thread.
+ *
+ * @note    The default is @p TRUE.
+ * @note    This debug option is defaulted to TRUE because it is required by
+ *          some test cases into the test suite.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
+#define CH_DBG_THREADS_PROFILING        TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief   Threads descriptor structure extension.
+ * @details User fields added to the end of the @p Thread structure.
+ */
+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define THREAD_EXT_FIELDS                                                   \
+  /* Add threads custom fields here.*/
+#endif
+
+/**
+ * @brief   Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note    It is invoked from within @p chThdInit() and implicitly from all
+ *          the threads creation APIs.
+ */
+#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_INIT_HOOK(tp) {                                          \
+  /* Add threads initialization code here.*/                                \
+}
+#endif
+
+/**
+ * @brief   Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note    It is inserted into lock zone.
+ * @note    It is also invoked when the threads simply return in order to
+ *          terminate.
+ */
+#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_EXIT_HOOK(tp) {                                          \
+  /* Add threads finalization code here.*/                                  \
+}
+#endif
+
+/**
+ * @brief   Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
+#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \
+  /* System halt code here.*/                                               \
+}
+#endif
+
+/**
+ * @brief   Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
+#define IDLE_LOOP_HOOK() {                                                  \
+  /* Idle loop code here.*/                                                 \
+}
+#endif
+
+/**
+ * @brief   System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ *          after processing the virtual timers queue.
+ */
+#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_TICK_EVENT_HOOK() {                                          \
+  /* System tick event code here.*/                                         \
+}
+#endif
+
+
+/**
+ * @brief   System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ *          the system is halted.
+ */
+#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_HALT_HOOK() {                                                \
+  /* System halt code here.*/                                               \
+}
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h).    */
+/*===========================================================================*/
+
+#endif  /* _CHCONF_H_ */
+
+/** @} */
diff --git a/boards/base/Win32/example/halconf.h b/boards/base/Win32/example/halconf.h
new file mode 100644
index 00000000..81dc4dd2
--- /dev/null
+++ b/boards/base/Win32/example/halconf.h
@@ -0,0 +1,342 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    templates/halconf.h
+ * @brief   HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ *          various device drivers from your application. You may also use
+ *          this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+/*#include "mcuconf.h"*/
+
+/**
+ * @brief   Enables the TM subsystem.
+ */
+#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
+#define HAL_USE_TM                  FALSE
+#endif
+
+/**
+ * @brief   Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL                 TRUE
+#endif
+
+/**
+ * @brief   Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN                 FALSE
+#endif
+
+/**
+ * @brief   Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT                 FALSE
+#endif
+
+/**
+ * @brief   Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT                 FALSE
+#endif
+
+/**
+ * @brief   Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C                 FALSE
+#endif
+
+/**
+ * @brief   Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU                 FALSE
+#endif
+
+/**
+ * @brief   Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI             FALSE
+#endif
+
+/**
+ * @brief   Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM                 FALSE
+#endif
+
+/**
+ * @brief   Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC                 FALSE
+#endif
+
+/**
+ * @brief   Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL              TRUE
+#endif
+
+/**
+ * @brief   Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB          FALSE
+#endif
+
+/**
+ * @brief   Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI                 FALSE
+#endif
+
+/**
+ * @brief   Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART                FALSE
+#endif
+
+/**
+ * @brief   Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB                 FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables synchronous APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT                TRUE
+#endif
+
+/**
+ * @brief   Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE          TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS              TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings.                                          */
+/*===========================================================================*/
+
+/**
+ * @brief   Block size for MMC transfers.
+ */
+#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__)
+#define MMC_SECTOR_SIZE             512
+#endif
+
+/**
+ * @brief   Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ *          routines releasing some extra CPU time for the threads with
+ *          lower priority, this may slow down the driver a bit however.
+ *          This option is recommended also if the SPI driver does not
+ *          use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING            TRUE
+#endif
+
+/**
+ * @brief   Number of positive insertion queries before generating the
+ *          insertion event.
+ */
+#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__)
+#define MMC_POLLING_INTERVAL        10
+#endif
+
+/**
+ * @brief   Interval, in milliseconds, between insertion queries.
+ */
+#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__)
+#define MMC_POLLING_DELAY           10
+#endif
+
+/**
+ * @brief   Uses the SPI polled API for small data transfers.
+ * @details Polled transfers usually improve performance because it
+ *          saves two context switches and interrupt servicing. Note
+ *          that this option has no effect on large transfers which
+ *          are always performed using DMAs/IRQs.
+ */
+#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__)
+#define MMC_USE_SPI_POLLING         TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Number of initialization attempts before rejecting the card.
+ * @note    Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY              100
+#endif
+
+/**
+ * @brief   Include support for MMC cards.
+ * @note    MMC support is not yet implemented so this option must be kept
+ *          at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT             FALSE
+#endif
+
+/**
+ * @brief   Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ *          routines releasing some extra CPU time for the threads with
+ *          lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING            TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings.                                           */
+/*===========================================================================*/
+
+/**
+ * @brief   Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ *          default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE      38400
+#endif
+
+/**
+ * @brief   Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ *          buffers depending on the requirements of your application.
+ * @note    The default is 64 bytes for both the transmission and receive
+ *          buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE         16
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings.                                              */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables synchronous APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT                TRUE
+#endif
+
+/**
+ * @brief   Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note    Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION    TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/boards/base/Win32/example/readme.txt b/boards/base/Win32/example/readme.txt
new file mode 100644
index 00000000..78b8552b
--- /dev/null
+++ b/boards/base/Win32/example/readme.txt
@@ -0,0 +1,9 @@
+Copy these files into your own project directory and alter them to suite.
+
+Notes:
+
+1/ This makefile uses the MINGW compiler tool chain and was run using the cygwin make.
+2/ At the top of the Makefile is the define USE_CHIBIOS. Win32 can build uGFX for either
+	native Win32 (the default) or for the ChibiOS simulator.
+3/ The files chconf.h and halconf.h are only needed if compiling for the ChibiOS simulator.
+4/ Look at the MYFILES definition and the MYCSRC definition.
diff --git a/boards/base/Win32/readme.txt b/boards/base/Win32/readme.txt
new file mode 100644
index 00000000..031a7c6e
--- /dev/null
+++ b/boards/base/Win32/readme.txt
@@ -0,0 +1,9 @@
+This directory contains the interface for Win32
+running either native Win32 or under the ChibiOS simulator.
+
+On this board uGFX currently supports:
+	- GDISP via the Win32 driver 
+	- GINPUT-touch via the Win32 driver
+	- GINPUT-toggles via the Win32 driver
+
+There is an example Makefile and project in the examples directory.