Some more work on the F7 discovery

6 files changed, 39 insertions, 466 deletions

diff --git a/boards/base/STM32F746-Discovery/board.mk b/boards/base/STM32F746-Discovery/board.mk
index d43e1709..ce70ef15 100644
--- a/boards/base/STM32F746-Discovery/board.mk
+++ b/boards/base/STM32F746-Discovery/board.mk
@@ -1,5 +1,5 @@
 GFXINC  +=	$(GFXLIB)/boards/base/STM32F746-Discovery
-GFXSRC  +=	$(GFXLIB)/boards/base/STM32F746-Discovery/STM32F746_discovery_sdram.c \
-			$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f4xx_fmc.c
+GFXSRC  +=	$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c \
+			$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c
 
 include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk
\ No newline at end of file
diff --git a/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h b/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h
index 735cdbdb..33f6e2cb 100644
--- a/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h
+++ b/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h
@@ -8,8 +8,8 @@
 #ifndef _GDISP_LLD_BOARD_H
 #define _GDISP_LLD_BOARD_H
 
-#include "stm32f4xx_fmc.h"
-#include "stm32f429i_discovery_sdram.h"
+#include "stm32f7xx_ll_fmc.h"
+#include "stm32f746g_discovery_sdram.h"
 #include <string.h>
 
 static const ltdcConfig driverCfg = {
diff --git a/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.c b/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.c
deleted file mode 100644
index 3b467b4b..00000000
--- a/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.c
+++ /dev/null
@@ -1,333 +0,0 @@
-#include "ch.h"
-#include "hal.h"
-
-#include "stm32f429i_discovery_sdram.h"
-#include "stm32f4xx_fmc.h"
-
-/**
-  * @brief  Configures the FMC and GPIOs to interface with the SDRAM memory.
-  *         This function must be called before any read/write operation
-  *         on the SDRAM.
-  * @param  None
-  * @retval None
-  */
-void SDRAM_Init(void)
-{
-  FMC_SDRAMInitTypeDef  FMC_SDRAMInitStructure;
-  FMC_SDRAMTimingInitTypeDef  FMC_SDRAMTimingInitStructure; 
-  
-  /* Enable FMC clock */
-  rccEnableAHB3(RCC_AHB3ENR_FMCEN, FALSE);
- 
-/* FMC Configuration ---------------------------------------------------------*/
-/* FMC SDRAM Bank configuration */   
-  /* Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) */
-  /* TMRD: 2 Clock cycles */
-  FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;      
-  /* TXSR: min=70ns (6x11.90ns) */
-  FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7;
-  /* TRAS: min=42ns (4x11.90ns) max=120k (ns) */
-  FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
-  /* TRC:  min=63 (6x11.90ns) */        
-  FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7;         
-  /* TWR:  2 Clock cycles */
-  FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;      
-  /* TRP:  15ns => 2x11.90ns */
-  FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;                
-  /* TRCD: 15ns => 2x11.90ns */
-  FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
-
-/* FMC SDRAM control configuration */
-  FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM;
-  /* Row addressing: [7:0] */
-  FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
-  /* Column addressing: [11:0] */
-  FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b;
-  FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH;
-  FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
-  FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY; 
-  FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
-  FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD;  
-  FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST;
-  FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
-  FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
-  
-  /* FMC SDRAM bank initialization */
-  FMC_SDRAMInit(&FMC_SDRAMInitStructure); 
-  
-  /* FMC SDRAM device initialization sequence */
-  SDRAM_InitSequence(); 
-  
-}
-
-/*-- GPIOs Configuration -----------------------------------------------------*/
-/*
- +-------------------+--------------------+--------------------+--------------------+
- +                       SDRAM pins assignment                                      +
- +-------------------+--------------------+--------------------+--------------------+
- | PD0  <-> FMC_D2   | PE0  <-> FMC_NBL0  | PF0  <-> FMC_A0    | PG0  <-> FMC_A10   |
- | PD1  <-> FMC_D3   | PE1  <-> FMC_NBL1  | PF1  <-> FMC_A1    | PG1  <-> FMC_A11   |
- | PD8  <-> FMC_D13  | PE7  <-> FMC_D4    | PF2  <-> FMC_A2    | PG8  <-> FMC_SDCLK |
- | PD9  <-> FMC_D14  | PE8  <-> FMC_D5    | PF3  <-> FMC_A3    | PG15 <-> FMC_NCAS  |
- | PD10 <-> FMC_D15  | PE9  <-> FMC_D6    | PF4  <-> FMC_A4    |--------------------+ 
- | PD14 <-> FMC_D0   | PE10 <-> FMC_D7    | PF5  <-> FMC_A5    |   
- | PD15 <-> FMC_D1   | PE11 <-> FMC_D8    | PF11 <-> FMC_NRAS  | 
- +-------------------| PE12 <-> FMC_D9    | PF12 <-> FMC_A6    | 
-                     | PE13 <-> FMC_D10   | PF13 <-> FMC_A7    |    
-                     | PE14 <-> FMC_D11   | PF14 <-> FMC_A8    |
-                     | PE15 <-> FMC_D12   | PF15 <-> FMC_A9    |
- +-------------------+--------------------+--------------------+
- | PB5 <-> FMC_SDCKE1| 
- | PB6 <-> FMC_SDNE1 | 
- | PC0 <-> FMC_SDNWE |
- +-------------------+  
-  
-*/
-  
-//  /* Common GPIO configuration */
-//  GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AF;
-//  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-//  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-//  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;
-//
-//  /* GPIOB configuration */
-//  GPIO_PinAFConfig(GPIOB, GPIO_PinSource5 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOB, GPIO_PinSource6 , GPIO_AF_FMC);
-//
-//  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5  | GPIO_Pin_6;
-//
-//  GPIO_Init(GPIOB, &GPIO_InitStructure);
-//
-//  /* GPIOC configuration */
-//  GPIO_PinAFConfig(GPIOC, GPIO_PinSource0 , GPIO_AF_FMC);
-//
-//  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
-//
-//  GPIO_Init(GPIOC, &GPIO_InitStructure);
-//
-//  /* GPIOD configuration */
-//  GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC);
-//
-//  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1  | GPIO_Pin_8 |
-//                                GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 |
-//                                GPIO_Pin_15;
-//
-//  GPIO_Init(GPIOD, &GPIO_InitStructure);
-//
-//  /* GPIOE configuration */
-//  GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC);
-//
-//  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0  | GPIO_Pin_1  | GPIO_Pin_7 |
-//                                GPIO_Pin_8  | GPIO_Pin_9  | GPIO_Pin_10 |
-//                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
-//                                GPIO_Pin_14 | GPIO_Pin_15;
-//
-//  GPIO_Init(GPIOE, &GPIO_InitStructure);
-//
-//  /* GPIOF configuration */
-//  GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC);
-//
-//  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0  | GPIO_Pin_1 | GPIO_Pin_2 |
-//                                GPIO_Pin_3  | GPIO_Pin_4 | GPIO_Pin_5 |
-//                                GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
-//                                GPIO_Pin_14 | GPIO_Pin_15;
-//
-//  GPIO_Init(GPIOF, &GPIO_InitStructure);
-//
-//  /* GPIOG configuration */
-//  GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC);
-//  GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC);
-//
-//
-//  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 |
-//                                GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15;
-//
-//  GPIO_Init(GPIOG, &GPIO_InitStructure);
-
-/**
-  * @brief  Executes the SDRAM memory initialization sequence. 
-  * @param  None. 
-  * @retval None.
-  */
-void SDRAM_InitSequence(void)
-{
-  FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
-  uint32_t tmpr = 0;
-  
-/* Step 3 --------------------------------------------------------------------*/
-  /* Configure a clock configuration enable command */
-  FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled;
-  FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
-  FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
-  FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
-  /* Wait until the SDRAM controller is ready */ 
-  while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
-  {
-  }
-  /* Send the command */
-  FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);  
-  
-  //In the ST example, this is 100ms, but the 429 RM says 100us is typical, and
-  //the ISSI datasheet confirms this. 1ms seems plenty, and is much shorter than
-  //refresh interval, meaning we won't risk losing contents if the SDRAM is in self-refresh
-  //mode
-/* Step 4 --------------------------------------------------------------------*/
-  /* Insert 1 ms delay */
-  chThdSleepMilliseconds(1);
-    
-/* Step 5 --------------------------------------------------------------------*/
-  /* Configure a PALL (precharge all) command */ 
-  FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL;
-  FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
-  FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
-  FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
-  /* Wait until the SDRAM controller is ready */ 
-  while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
-  {
-  }
-  /* Send the command */
-  FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
-  
-/* Step 6 --------------------------------------------------------------------*/
-  /* Configure a Auto-Refresh command */ 
-  FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh;
-  FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
-  FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4;
-  FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
-  /* Wait until the SDRAM controller is ready */ 
-  while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
-  {
-  }
-  /* Send the  first command */
-  FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
-  
-  /* Wait until the SDRAM controller is ready */ 
-  while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
-  {
-  }
-  /* Send the second command */
-  FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
-  
-/* Step 7 --------------------------------------------------------------------*/
-  /* Program the external memory mode register */
-  tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2          |
-                   SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL   |
-                   SDRAM_MODEREG_CAS_LATENCY_3           |
-                   SDRAM_MODEREG_OPERATING_MODE_STANDARD |
-                   SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
-  
-  /* Configure a load Mode register command*/ 
-  FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode;
-  FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
-  FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
-  FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr;
-  /* Wait until the SDRAM controller is ready */ 
-  while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
-  {
-  }
-  /* Send the command */
-  FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
-  
-/* Step 8 --------------------------------------------------------------------*/
-
-  /* Set the refresh rate counter */
-  /* (7.81 us x Freq) - 20 */
-  /* Set the device refresh counter */
-  FMC_SetRefreshCount(683);
-  /* Wait until the SDRAM controller is ready */ 
-  while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
-  {
-  }
-}
-
-
-/**
-  * @brief  Writes a Entire-word buffer to the SDRAM memory. 
-  * @param  pBuffer: pointer to buffer. 
-  * @param  uwWriteAddress: SDRAM memory internal address from which the data will be 
-  *         written.
-  * @param  uwBufferSize: number of words to write. 
-  * @retval None.
-  */
-void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize)
-{
-  __IO uint32_t write_pointer = (uint32_t)uwWriteAddress;
-
-  /* Disable write protection */
-  FMC_SDRAMWriteProtectionConfig(FMC_Bank2_SDRAM, DISABLE);
-  
-  /* Wait until the SDRAM controller is ready */ 
-  while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
-  {
-  }
-
-  /* While there is data to write */
-  for (; uwBufferSize != 0; uwBufferSize--) 
-  {
-    /* Transfer data to the memory */
-    *(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++;
-
-    /* Increment the address*/
-    write_pointer += 4;
-  }
-    
-}
-
-/**
-  * @brief  Reads data buffer from the SDRAM memory. 
-  * @param  pBuffer: pointer to buffer. 
-  * @param  ReadAddress: SDRAM memory internal address from which the data will be 
-  *         read.
-  * @param  uwBufferSize: number of words to write. 
-  * @retval None.
-  */
-void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize)
-{
-  __IO uint32_t write_pointer = (uint32_t)uwReadAddress;
-  
-   
-  /* Wait until the SDRAM controller is ready */ 
-  while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
-  {
-  }
-  
-  /* Read data */
-  for(; uwBufferSize != 0x00; uwBufferSize--)
-  {
-   *pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer );
-    
-   /* Increment the address*/
-    write_pointer += 4;
-  } 
-}
-
diff --git a/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.h b/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.h
deleted file mode 100644
index fba5115d..00000000
--- a/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f429i_discovery_sdram.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    20-September-2013
-  * @brief   This file contains all the functions prototypes for the 
-  *          stm324x9i_disco_sdram.c driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */   
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32429I_DISCO_SDRAM_H
-#define __STM32429I_DISCO_SDRAM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-//FIXME this should not be needed
-#define STM32F429_439xx
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/**
-  * @brief  FMC SDRAM Bank address
-  */   
-#define SDRAM_BANK_ADDR     ((uint32_t)0xD0000000)
-  
-/**
-  * @brief  FMC SDRAM Memory Width
-  */  
-/* #define SDRAM_MEMORY_WIDTH   FMC_SDMemory_Width_8b  */
-#define SDRAM_MEMORY_WIDTH    FMC_SDMemory_Width_16b 
-
-/**
-  * @brief  FMC SDRAM CAS Latency
-  */  
-/* #define SDRAM_CAS_LATENCY   FMC_CAS_Latency_2  */
-#define SDRAM_CAS_LATENCY    FMC_CAS_Latency_3
-
-/**
-  * @brief  FMC SDRAM Memory clock period
-  */  
-#define SDCLOCK_PERIOD    FMC_SDClock_Period_2        /* Default configuration used with LCD */
-/* #define SDCLOCK_PERIOD    FMC_SDClock_Period_3 */
-
-/**
-  * @brief  FMC SDRAM Memory Read Burst feature
-  */  
-#define SDRAM_READBURST    FMC_Read_Burst_Disable    /* Default configuration used with LCD */
-/* #define SDRAM_READBURST    FMC_Read_Burst_Enable  */
-
-/**
-  * @brief  FMC SDRAM Mode definition register defines
-  */
-#define SDRAM_MODEREG_BURST_LENGTH_1             ((uint16_t)0x0000)
-#define SDRAM_MODEREG_BURST_LENGTH_2             ((uint16_t)0x0001)
-#define SDRAM_MODEREG_BURST_LENGTH_4             ((uint16_t)0x0002)
-#define SDRAM_MODEREG_BURST_LENGTH_8             ((uint16_t)0x0004)
-#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
-#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
-#define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
-#define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
-#define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
-#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) 
-#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)      
-
-void  SDRAM_Init(void);
-void  SDRAM_InitSequence(void);
-void  SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize);
-void  SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.c b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c
index d214b3f1..0ef2d634 100644
--- a/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.c
+++ b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c
@@ -76,7 +76,7 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32746g_discovery_sdram.h"
+#include "stm32f746g_discovery_sdram.h"
 
 /** @addtogroup BSP
   * @{
diff --git a/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.h b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h
index cafdce5c..56d7fd4b 100644
--- a/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.h
+++ b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h
@@ -34,44 +34,46 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32746G_DISCOVERY_SDRAM_H
-#define __STM32746G_DISCOVERY_SDRAM_H
+#ifndef __STM32F746G_DISCOVERY_SDRAM_H
+#define __STM32F746G_DISCOVERY_SDRAM_H
 
 #ifdef __cplusplus
  extern "C" {
-#endif 
+#endif
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
+#include "stm32f7xx_hal_sdram.h"
+#include "stm32f7xx_hal_dma.h"
+#include "stm32f7xx_ll_fmc.h"
 
 /** @addtogroup BSP
   * @{
-  */ 
+  */
 
 /** @addtogroup STM32746G_DISCOVERY
   * @{
   */
-    
+
 /** @addtogroup STM32746G_DISCOVERY_SDRAM
   * @{
-  */    
+  */
 
 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Types STM32746G_DISCOVERY_SDRAM Exported Types
   * @{
   */
 
-/** 
-  * @brief  SDRAM status structure definition  
-  */     
+/**
+  * @brief  SDRAM status structure definition
+  */
 #define   SDRAM_OK         ((uint8_t)0x00)
 #define   SDRAM_ERROR      ((uint8_t)0x01)
 
 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Constants STM32746G_DISCOVERY_SDRAM Exported Constants
   * @{
-  */ 
+  */
 #define SDRAM_DEVICE_ADDR  ((uint32_t)0xC0000000)
 #define SDRAM_DEVICE_SIZE  ((uint32_t)0x800000)  /* SDRAM device size in MBytes */
 
@@ -79,23 +81,23 @@
 #define SDRAM_MEMORY_WIDTH               FMC_SDRAM_MEM_BUS_WIDTH_16
 
 #define SDCLOCK_PERIOD                   FMC_SDRAM_CLOCK_PERIOD_2
-/* #define SDCLOCK_PERIOD                FMC_SDRAM_CLOCK_PERIOD_3 */   
+/* #define SDCLOCK_PERIOD                FMC_SDRAM_CLOCK_PERIOD_3 */
 
 #define REFRESH_COUNT                    ((uint32_t)0x0603)   /* SDRAM refresh counter (100Mhz SD clock) */
-   
+
 #define SDRAM_TIMEOUT                    ((uint32_t)0xFFFF)
 
 /* DMA definitions for SDRAM DMA transfer */
 #define __DMAx_CLK_ENABLE                 __HAL_RCC_DMA2_CLK_ENABLE
 #define __DMAx_CLK_DISABLE                __HAL_RCC_DMA2_CLK_DISABLE
 #define SDRAM_DMAx_CHANNEL                DMA_CHANNEL_0
-#define SDRAM_DMAx_STREAM                 DMA2_Stream0  
+#define SDRAM_DMAx_STREAM                 DMA2_Stream0
 #define SDRAM_DMAx_IRQn                   DMA2_Stream0_IRQn
-#define SDRAM_DMAx_IRQHandler             DMA2_Stream0_IRQHandler  
+#define SDRAM_DMAx_IRQHandler             DMA2_Stream0_IRQHandler
 /**
   * @}
-  */ 
-  
+  */
+
 /**
   * @brief  FMC SDRAM Mode definition register defines
   */
@@ -108,22 +110,22 @@
 #define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
 #define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
-#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) 
-#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200) 
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
 /**
   * @}
-  */ 
-  
+  */
+
 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Macro STM32746G_DISCOVERY_SDRAM Exported Macro
   * @{
-  */  
+  */
 /**
   * @}
-  */ 
-   
+  */
+
 /** @addtogroup STM32746G_DISCOVERY_SDRAM_Exported_Functions
   * @{
-  */  
+  */
 uint8_t BSP_SDRAM_Init(void);
 uint8_t BSP_SDRAM_DeInit(void);
 void    BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
@@ -132,8 +134,8 @@ uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_
 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
-void    BSP_SDRAM_DMA_IRQHandler(void);  
-   
+void    BSP_SDRAM_DMA_IRQHandler(void);
+
 /* These functions can be modified in case the current settings (e.g. DMA stream)
    need to be changed for specific application needs */
 void    BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram, void *Params);
@@ -142,19 +144,19 @@ void    BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef  *hsdram, void *Params);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }