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| author | inmarket <andrewh@inmarket.com.au> | 2015-02-23 18:17:26 +1000 |
|---|---|---|
| committer | inmarket <andrewh@inmarket.com.au> | 2015-02-23 18:17:26 +1000 |
| commit | 6c0409f25b996711bda0a185fffa6a99e58577b3 (patch) | |
| tree | b869cf955a77a18e440f79076a48f74d3218bcf7 /boards | |
| parent | 53aba6de891b0a3ba1f74cd224206ff18099a72d (diff) | |
| download | uGFX-6c0409f25b996711bda0a185fffa6a99e58577b3.tar.gz uGFX-6c0409f25b996711bda0a185fffa6a99e58577b3.tar.bz2 uGFX-6c0409f25b996711bda0a185fffa6a99e58577b3.zip | |
New Mikromedia-Plus-STM32-M4 board by lliypuk (with mods)
Diffstat (limited to 'boards')
21 files changed, 5838 insertions, 0 deletions
diff --git a/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/board.c b/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/board.c new file mode 100644 index 00000000..41c13fe9 --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/board.c @@ -0,0 +1,123 @@ +/* + ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +#endif +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + return !palReadPad(GPIOD, GPIOD_SD_CD); +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* Board has no write protection detection */ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/board.h b/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/board.h new file mode 100644 index 00000000..bfcde82a --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/board.h @@ -0,0 +1,1300 @@ +/* + ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for ST_MIKROMEDIA_PLUS_STM32 board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_MIKROMEDIA_PLUS_STM32 +#define BOARD_NAME "ST_MIKROMEDIA_PLUS_STM32" + +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ID MII_LAN8720_ID +#define BOARD_PHY_RMII + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768 +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 25000000 +#endif + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 330 + +/* + * MCU type as defined in the ST header. + */ +#define STM32F407xx + +/* + * IO pins assignments. + */ +#define GPIOA_TP_INT 0 +#define GPIOA_LAN_SCL 1 +#define GPIOA_LAN_MDIO 2 +#define GPIOA_HDR_UART1_RX 3 +#define GPIOA_HDR_AN0 4 +#define GPIOA_SPI1_SCK 5 +#define GPIOA_SPI1_MISO 6 +#define GPIOA_LAN_CRS_DV 7 +#define GPIOA_LAN_CLK 8 +#define GPIOA_USB_VBUS 9 +#define GPIOA_USB_ID 10 +#define GPIOA_USB_DN 11 +#define GPIOA_USB_DP 12 +#define GPIOA_SWDIO 13 +#define GPIOA_SWCLK 14 +#define GPIOA_HDR_SPI1_SS 15 + +#define GPIOB_HDR_AN1 0 +#define GPIOB_HDR_AN2 1 +#define GPIOB_GND 2 +#define GPIOB_LED_G 3 +#define GPIOB_LED_B 4 +#define GPIOB_SPI1_MOSI 5 +#define GPIOB_I2C1_SCL 6 +#define GPIOB_I2C1_SDA 7 +#define GPIOB_BUZZER 8 +#define GPIOB_ACCEL_INT 9 +#define GPIOB_RC5_TX 10 +#define GPIOB_FLASH_CS 11 +#define GPIOB_HDR_SPI2_SS 12 +#define GPIOB_SPI2_SCK 13 +#define GPIOB_SPI2_MISO 14 +#define GPIOB_SPI2_MOSI 15 + +#define GPIOC_HDR_AN3 0 +#define GPIOC_LAN_MDC 1 +#define GPIOC_HDR_AN4 2 +#define GPIOC_HDR_AN5 3 +#define GPIOC_LAN_RXD0 4 +#define GPIOC_LAN_RXD1 5 +#define GPIOC_HDR_UART2_TX 6 +#define GPIOC_HDR_UART2_RX 7 +#define GPIOC_SD_DAT0 8 +#define GPIOC_SD_DAT1 9 +#define GPIOC_SD_DAT2 10 +#define GPIOC_SD_DAT3 11 +#define GPIOC_SD_CLK 12 +#define GPIOC_HDR_GPIO2 13 +#define GPIOC_OSC32_IN 14 +#define GPIOC_OSC32_OUT 15 + +#define GPIOD_HDR_CAN_RX 0 +#define GPIOD_HDR_CAN_TX 1 +#define GPIOD_SD_CMD 2 +#define GPIOD_SD_CD 3 +#define GPIOD_TFT_TE 4 +#define GPIOD_HDR_UART1_TX 5 +#define GPIOD_USB_PSW 6 +#define GPIOD_USB_VBUS_ER 7 +#define GPIOD_MP3_RST 8 +#define GPIOD_MP3_DREQ 9 +#define GPIOD_MP3_DCS 10 +#define GPIOD_MP3_CS 11 +#define GPIOD_HDR_PWM0 12 +#define GPIOD_HDR_PWM1 13 +#define GPIOD_HDR_PWM2 14 +#define GPIOD_HDR_PWM3 15 + +#define GPIOE_HDR_INT0 0 +#define GPIOE_HDR_INT1 1 +#define GPIOE_HDR_INT2 2 +#define GPIOE_HDR_INT3 3 +#define GPIOE_HDR_GPIO1 4 +#define GPIOE_HDR_PWM4 5 +#define GPIOE_HDR_PWM5 6 +#define GPIOE_TFT_GPIO0 7 +#define GPIOE_TFT_D8 8 +#define GPIOE_TFT_D9 9 +#define GPIOE_TFT_D10 10 +#define GPIOE_TFT_D11 11 +#define GPIOE_TFT_D12 12 +#define GPIOE_TFT_D13 13 +#define GPIOE_TFT_D14 14 +#define GPIOE_TFT_D15 15 + +#define GPIOF_HDR_I2C2_SDA 0 +#define GPIOF_HDR_I2C2_SCL 1 +#define GPIOF_PIN2 2 +#define GPIOF_DC_VBUS 3 +#define GPIOF_BAT_STAT 4 +#define GPIOF_LAN_INT 5 +#define GPIOF_AN_BAT_VSENSE 6 +#define GPIOF_PIN7 7 +#define GPIOF_AN_TEMP 8 +#define GPIOF_AN_PD 9 +#define GPIOF_PIN10 10 +#define GPIOF_TFT_WR 11 +#define GPIOF_TFT_RD 12 +#define GPIOF_TFT_CS 13 +#define GPIOF_TFT_RST 14 +#define GPIOF_TFT_DC 15 + +#define GPIOG_TFT_D0 0 +#define GPIOG_TFT_D1 1 +#define GPIOG_TFT_D2 2 +#define GPIOG_TFT_D3 3 +#define GPIOG_TFT_D4 4 +#define GPIOG_TFT_D5 5 +#define GPIOG_TFT_D6 6 +#define GPIOG_TFT_D7 7 +#define GPIOG_LAN_RST 8 +#define GPIOG_RF_CS 9 +#define GPIOG_RF_INT 10 +#define GPIOG_LAN_TXEN 11 +#define GPIOG_RF_CE 12 +#define GPIOG_LAN_TXD0 13 +#define GPIOG_LAN_TXD1 14 +#define GPIOG_LED_R 15 + +#define GPIOH_OSC_IN 0 +#define GPIOH_OSC_OUT 1 +#define GPIOH_PIN2 2 +#define GPIOH_PIN3 3 +#define GPIOH_PIN4 4 +#define GPIOH_PIN5 5 +#define GPIOH_PIN6 6 +#define GPIOH_PIN7 7 +#define GPIOH_PIN8 8 +#define GPIOH_PIN9 9 +#define GPIOH_PIN10 10 +#define GPIOH_PIN11 11 +#define GPIOH_PIN12 12 +#define GPIOH_PIN13 13 +#define GPIOH_PIN14 14 +#define GPIOH_PIN15 15 + +#define GPIOI_PIN0 0 +#define GPIOI_PIN1 1 +#define GPIOI_PIN2 2 +#define GPIOI_PIN3 3 +#define GPIOI_PIN4 4 +#define GPIOI_PIN5 5 +#define GPIOI_PIN6 6 +#define GPIOI_PIN7 7 +#define GPIOI_PIN8 8 +#define GPIOI_PIN9 9 +#define GPIOI_PIN10 10 +#define GPIOI_PIN11 11 +#define GPIOI_PIN12 12 +#define GPIOI_PIN13 13 +#define GPIOI_PIN14 14 +#define GPIOI_PIN15 15 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) + +/* + * GPIOA setup: + * + * PA0 - TP_INT (input floating). + * PA1 - LAN_SCL (alternate 11). + * PA2 - LAN_MDIO (alternate 11). + * PA3 - HDR_UART1_RX (alternate 7). + * PA4 - HDR_AN0 (input pullup). + * PA5 - SPI1_SCK (alternate 5). + * PA6 - SPI1_MISO (alternate 5). + * PA7 - LAN_CRS_DV (alternate 11). + * PA8 - LAN_CLK (alternate 0). + * PA9 - USB_VBUS (input floating). + * PA10 - USB_ID (alternate 10). + * PA11 - USB_DN (alternate 10). + * PA12 - USB_DP (alternate 10). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - HDR_SPI1_SS (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_TP_INT) | \ + PIN_MODE_ALTERNATE(GPIOA_LAN_SCL) | \ + PIN_MODE_ALTERNATE(GPIOA_LAN_MDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_HDR_UART1_RX) |\ + PIN_MODE_INPUT(GPIOA_HDR_AN0) | \ + PIN_MODE_ALTERNATE(GPIOA_SPI1_SCK) | \ + PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \ + PIN_MODE_ALTERNATE(GPIOA_LAN_CRS_DV) | \ + PIN_MODE_ALTERNATE(GPIOA_LAN_CLK) | \ + PIN_MODE_INPUT(GPIOA_USB_VBUS) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DN) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_HDR_SPI1_SS)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_TP_INT) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LAN_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LAN_MDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_HDR_UART1_RX) |\ + PIN_OTYPE_PUSHPULL(GPIOA_HDR_AN0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LAN_CRS_DV) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LAN_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DN) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_HDR_SPI1_SS)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_TP_INT) | \ + PIN_OSPEED_100M(GPIOA_LAN_SCL) | \ + PIN_OSPEED_100M(GPIOA_LAN_MDIO) | \ + PIN_OSPEED_100M(GPIOA_HDR_UART1_RX) | \ + PIN_OSPEED_100M(GPIOA_HDR_AN0) | \ + PIN_OSPEED_50M(GPIOA_SPI1_SCK) | \ + PIN_OSPEED_50M(GPIOA_SPI1_MISO) | \ + PIN_OSPEED_50M(GPIOA_LAN_CRS_DV) | \ + PIN_OSPEED_100M(GPIOA_LAN_CLK) | \ + PIN_OSPEED_100M(GPIOA_USB_VBUS) | \ + PIN_OSPEED_100M(GPIOA_USB_ID) | \ + PIN_OSPEED_100M(GPIOA_USB_DN) | \ + PIN_OSPEED_100M(GPIOA_USB_DP) | \ + PIN_OSPEED_100M(GPIOA_SWDIO) | \ + PIN_OSPEED_100M(GPIOA_SWCLK) | \ + PIN_OSPEED_100M(GPIOA_HDR_SPI1_SS)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_TP_INT) | \ + PIN_PUPDR_FLOATING(GPIOA_LAN_SCL) | \ + PIN_PUPDR_PULLUP(GPIOA_LAN_MDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_HDR_UART1_RX) |\ + PIN_PUPDR_PULLUP(GPIOA_HDR_AN0) | \ + PIN_PUPDR_FLOATING(GPIOA_SPI1_SCK) | \ + PIN_PUPDR_FLOATING(GPIOA_SPI1_MISO) | \ + PIN_PUPDR_FLOATING(GPIOA_LAN_CRS_DV) | \ + PIN_PUPDR_FLOATING(GPIOA_LAN_CLK) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_ID) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DN) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_HDR_SPI1_SS)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_TP_INT) | \ + PIN_ODR_HIGH(GPIOA_LAN_SCL) | \ + PIN_ODR_HIGH(GPIOA_LAN_MDIO) | \ + PIN_ODR_HIGH(GPIOA_HDR_UART1_RX) | \ + PIN_ODR_HIGH(GPIOA_HDR_AN0) | \ + PIN_ODR_HIGH(GPIOA_SPI1_SCK) | \ + PIN_ODR_HIGH(GPIOA_SPI1_MISO) | \ + PIN_ODR_HIGH(GPIOA_LAN_CRS_DV) | \ + PIN_ODR_HIGH(GPIOA_LAN_CLK) | \ + PIN_ODR_HIGH(GPIOA_USB_VBUS) | \ + PIN_ODR_HIGH(GPIOA_USB_ID) | \ + PIN_ODR_HIGH(GPIOA_USB_DN) | \ + PIN_ODR_HIGH(GPIOA_USB_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_HDR_SPI1_SS)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_TP_INT, 0) | \ + PIN_AFIO_AF(GPIOA_LAN_SCL, 11) | \ + PIN_AFIO_AF(GPIOA_LAN_MDIO, 11) | \ + PIN_AFIO_AF(GPIOA_HDR_UART1_RX, 7) | \ + PIN_AFIO_AF(GPIOA_HDR_AN0, 0) | \ + PIN_AFIO_AF(GPIOA_SPI1_SCK, 5) | \ + PIN_AFIO_AF(GPIOA_SPI1_MISO, 5) | \ + PIN_AFIO_AF(GPIOA_LAN_CRS_DV, 11)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_LAN_CLK, 0) | \ + PIN_AFIO_AF(GPIOA_USB_VBUS, 0) | \ + PIN_AFIO_AF(GPIOA_USB_ID, 10) | \ + PIN_AFIO_AF(GPIOA_USB_DN, 10) | \ + PIN_AFIO_AF(GPIOA_USB_DP, 10) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0) | \ + PIN_AFIO_AF(GPIOA_HDR_SPI1_SS, 0)) + +/* + * GPIOB setup: + * + * PB0 - HDR_AN1 (input pullup). + * PB1 - HDR_AN2 (input pullup). + * PB2 - GND (input floating). + * PB3 - LED_G (output pushpull maximum). + * PB4 - LED_B (output pushpull maximum). + * PB5 - SPI1_MOSI (alternate 5). + * PB6 - I2C1_SCL (alternate 4). + * PB7 - I2C1_SDA (alternate 4). + * PB8 - BUZZER (output pushpull maximum). + * PB9 - ACCEL_INT (input floating). + * PB10 - RC5_TX (alternate 7). + * PB11 - FLASH_CS (output pushpull maximum). + * PB12 - HDR_SPI2_SS (alternate 5). + * PB13 - SPI2_SCK (alternate 5). + * PB14 - SPI2_MISO (alternate 5). + * PB15 - SPI2_MOSI (alternate 5). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_HDR_AN1) | \ + PIN_MODE_INPUT(GPIOB_HDR_AN2) | \ + PIN_MODE_INPUT(GPIOB_GND) | \ + PIN_MODE_OUTPUT(GPIOB_LED_G) | \ + PIN_MODE_OUTPUT(GPIOB_LED_B) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI1_MOSI) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ + PIN_MODE_OUTPUT(GPIOB_BUZZER) | \ + PIN_MODE_INPUT(GPIOB_ACCEL_INT) | \ + PIN_MODE_ALTERNATE(GPIOB_RC5_TX) | \ + PIN_MODE_OUTPUT(GPIOB_FLASH_CS) | \ + PIN_MODE_ALTERNATE(GPIOB_HDR_SPI2_SS) |\ + PIN_MODE_ALTERNATE(GPIOB_SPI2_SCK) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI2_MISO) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_HDR_AN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_HDR_AN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_GND) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LED_G) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LED_B) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI1_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOB_I2C1_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOB_I2C1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_BUZZER) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_ACCEL_INT) | \ + PIN_OTYPE_PUSHPULL(GPIOB_RC5_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOB_FLASH_CS) | \ + PIN_OTYPE_PUSHPULL(GPIOB_HDR_SPI2_SS) |\ + PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SCK) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_HDR_AN1) | \ + PIN_OSPEED_100M(GPIOB_HDR_AN2) | \ + PIN_OSPEED_100M(GPIOB_GND) | \ + PIN_OSPEED_100M(GPIOB_LED_G) | \ + PIN_OSPEED_100M(GPIOB_LED_B) | \ + PIN_OSPEED_100M(GPIOB_SPI1_MOSI) | \ + PIN_OSPEED_100M(GPIOB_I2C1_SCL) | \ + PIN_OSPEED_100M(GPIOB_I2C1_SDA) | \ + PIN_OSPEED_100M(GPIOB_BUZZER) | \ + PIN_OSPEED_100M(GPIOB_ACCEL_INT) | \ + PIN_OSPEED_100M(GPIOB_RC5_TX) | \ + PIN_OSPEED_100M(GPIOB_FLASH_CS) | \ + PIN_OSPEED_100M(GPIOB_HDR_SPI2_SS) | \ + PIN_OSPEED_100M(GPIOB_SPI2_SCK) | \ + PIN_OSPEED_100M(GPIOB_SPI2_MISO) | \ + PIN_OSPEED_100M(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_HDR_AN1) | \ + PIN_PUPDR_PULLUP(GPIOB_HDR_AN2) | \ + PIN_PUPDR_FLOATING(GPIOB_GND) | \ + PIN_PUPDR_FLOATING(GPIOB_LED_G) | \ + PIN_PUPDR_FLOATING(GPIOB_LED_B) | \ + PIN_PUPDR_PULLUP(GPIOB_SPI1_MOSI) | \ + PIN_PUPDR_PULLUP(GPIOB_I2C1_SCL) | \ + PIN_PUPDR_PULLUP(GPIOB_I2C1_SDA) | \ + PIN_PUPDR_FLOATING(GPIOB_BUZZER) | \ + PIN_PUPDR_FLOATING(GPIOB_ACCEL_INT) | \ + PIN_PUPDR_FLOATING(GPIOB_RC5_TX) | \ + PIN_PUPDR_FLOATING(GPIOB_FLASH_CS) | \ + PIN_PUPDR_PULLUP(GPIOB_HDR_SPI2_SS) | \ + PIN_PUPDR_PULLUP(GPIOB_SPI2_SCK) | \ + PIN_PUPDR_PULLUP(GPIOB_SPI2_MISO) | \ + PIN_PUPDR_PULLUP(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_HDR_AN1) | \ + PIN_ODR_HIGH(GPIOB_HDR_AN2) | \ + PIN_ODR_HIGH(GPIOB_GND) | \ + PIN_ODR_LOW(GPIOB_LED_G) | \ + PIN_ODR_LOW(GPIOB_LED_B) | \ + PIN_ODR_HIGH(GPIOB_SPI1_MOSI) | \ + PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ + PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ + PIN_ODR_HIGH(GPIOB_BUZZER) | \ + PIN_ODR_HIGH(GPIOB_ACCEL_INT) | \ + PIN_ODR_HIGH(GPIOB_RC5_TX) | \ + PIN_ODR_HIGH(GPIOB_FLASH_CS) | \ + PIN_ODR_HIGH(GPIOB_HDR_SPI2_SS) | \ + PIN_ODR_HIGH(GPIOB_SPI2_SCK) | \ + PIN_ODR_HIGH(GPIOB_SPI2_MISO) | \ + PIN_ODR_HIGH(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_HDR_AN1, 0) | \ + PIN_AFIO_AF(GPIOB_HDR_AN2, 0) | \ + PIN_AFIO_AF(GPIOB_GND, 0) | \ + PIN_AFIO_AF(GPIOB_LED_G, 0) | \ + PIN_AFIO_AF(GPIOB_LED_B, 0) | \ + PIN_AFIO_AF(GPIOB_SPI1_MOSI, 5) | \ + PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \ + PIN_AFIO_AF(GPIOB_I2C1_SDA, 4)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_BUZZER, 0) | \ + PIN_AFIO_AF(GPIOB_ACCEL_INT, 0) | \ + PIN_AFIO_AF(GPIOB_RC5_TX, 7) | \ + PIN_AFIO_AF(GPIOB_FLASH_CS, 0) | \ + PIN_AFIO_AF(GPIOB_HDR_SPI2_SS, 5) | \ + PIN_AFIO_AF(GPIOB_SPI2_SCK, 5) | \ + PIN_AFIO_AF(GPIOB_SPI2_MISO, 5) | \ + PIN_AFIO_AF(GPIOB_SPI2_MOSI, 5)) + +/* + * GPIOC setup: + * + * PC0 - HDR_AN3 (output pushpull maximum). + * PC1 - LAN_MDC (alternate 11). + * PC2 - HDR_AN4 (input pullup). + * PC3 - HDR_AN5 (input pullup). + * PC4 - LAN_RXD0 (alternate 11). + * PC5 - LAN_RXD1 (alternate 11). + * PC6 - HDR_UART2_TX (alternate 8). + * PC7 - HDR_UART2_RX (alternate 8). + * PC8 - SD_DAT0 (alternate 12). + * PC9 - SD_DAT1 (alternate 12). + * PC10 - SD_DAT2 (alternate 12). + * PC11 - SD_DAT3 (alternate 12). + * PC12 - SD_CLK (alternate 12). + * PC13 - HDR_GPIO2 (input pullup). + * PC14 - OSC32_IN (input pullup). + * PC15 - OSC32_OUT (input pullup). + */ +#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_HDR_AN3) | \ + PIN_MODE_ALTERNATE(GPIOC_LAN_MDC) | \ + PIN_MODE_INPUT(GPIOC_HDR_AN4) | \ + PIN_MODE_INPUT(GPIOC_HDR_AN5) | \ + PIN_MODE_ALTERNATE(GPIOC_LAN_RXD0) | \ + PIN_MODE_ALTERNATE(GPIOC_LAN_RXD1) | \ + PIN_MODE_ALTERNATE(GPIOC_HDR_UART2_TX) |\ + PIN_MODE_ALTERNATE(GPIOC_HDR_UART2_RX) |\ + PIN_MODE_ALTERNATE(GPIOC_SD_DAT0) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_DAT1) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_DAT2) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_DAT3) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_CLK) | \ + PIN_MODE_INPUT(GPIOC_HDR_GPIO2) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_HDR_AN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LAN_MDC) | \ + PIN_OTYPE_PUSHPULL(GPIOC_HDR_AN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_HDR_AN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LAN_RXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LAN_RXD1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_HDR_UART2_TX) |\ + PIN_OTYPE_PUSHPULL(GPIOC_HDR_UART2_RX) |\ + PIN_OTYPE_PUSHPULL(GPIOC_SD_DAT0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_DAT1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_DAT2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_DAT3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_HDR_GPIO2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_HDR_AN3) | \ + PIN_OSPEED_100M(GPIOC_LAN_MDC) | \ + PIN_OSPEED_100M(GPIOC_HDR_AN4) | \ + PIN_OSPEED_100M(GPIOC_HDR_AN5) | \ + PIN_OSPEED_100M(GPIOC_LAN_RXD0) | \ + PIN_OSPEED_100M(GPIOC_LAN_RXD1) | \ + PIN_OSPEED_100M(GPIOC_HDR_UART2_TX) | \ + PIN_OSPEED_100M(GPIOC_HDR_UART2_RX) | \ + PIN_OSPEED_100M(GPIOC_SD_DAT0) | \ + PIN_OSPEED_100M(GPIOC_SD_DAT1) | \ + PIN_OSPEED_100M(GPIOC_SD_DAT2) | \ + PIN_OSPEED_100M(GPIOC_SD_DAT3) | \ + PIN_OSPEED_100M(GPIOC_SD_CLK) | \ + PIN_OSPEED_100M(GPIOC_HDR_GPIO2) | \ + PIN_OSPEED_100M(GPIOC_OSC32_IN) | \ + PIN_OSPEED_100M(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLDOWN(GPIOC_HDR_AN3) | \ + PIN_PUPDR_FLOATING(GPIOC_LAN_MDC) | \ + PIN_PUPDR_PULLUP(GPIOC_HDR_AN4) | \ + PIN_PUPDR_PULLUP(GPIOC_HDR_AN5) | \ + PIN_PUPDR_FLOATING(GPIOC_LAN_RXD0) | \ + PIN_PUPDR_FLOATING(GPIOC_LAN_RXD1) | \ + PIN_PUPDR_FLOATING(GPIOC_HDR_UART2_TX) |\ + PIN_PUPDR_FLOATING(GPIOC_HDR_UART2_RX) |\ + PIN_PUPDR_FLOATING(GPIOC_SD_DAT0) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_DAT1) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_DAT2) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_DAT3) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_CLK) | \ + PIN_PUPDR_PULLUP(GPIOC_HDR_GPIO2) | \ + PIN_PUPDR_PULLUP(GPIOC_OSC32_IN) | \ + PIN_PUPDR_PULLUP(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_HDR_AN3) | \ + PIN_ODR_HIGH(GPIOC_LAN_MDC) | \ + PIN_ODR_HIGH(GPIOC_HDR_AN4) | \ + PIN_ODR_HIGH(GPIOC_HDR_AN5) | \ + PIN_ODR_HIGH(GPIOC_LAN_RXD0) | \ + PIN_ODR_HIGH(GPIOC_LAN_RXD1) | \ + PIN_ODR_HIGH(GPIOC_HDR_UART2_TX) | \ + PIN_ODR_HIGH(GPIOC_HDR_UART2_RX) | \ + PIN_ODR_HIGH(GPIOC_SD_DAT0) | \ + PIN_ODR_HIGH(GPIOC_SD_DAT1) | \ + PIN_ODR_HIGH(GPIOC_SD_DAT2) | \ + PIN_ODR_HIGH(GPIOC_SD_DAT3) | \ + PIN_ODR_HIGH(GPIOC_SD_CLK) | \ + PIN_ODR_HIGH(GPIOC_HDR_GPIO2) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_HDR_AN3, 0) | \ + PIN_AFIO_AF(GPIOC_LAN_MDC, 11) | \ + PIN_AFIO_AF(GPIOC_HDR_AN4, 0) | \ + PIN_AFIO_AF(GPIOC_HDR_AN5, 0) | \ + PIN_AFIO_AF(GPIOC_LAN_RXD0, 11) | \ + PIN_AFIO_AF(GPIOC_LAN_RXD1, 11) | \ + PIN_AFIO_AF(GPIOC_HDR_UART2_TX, 8) | \ + PIN_AFIO_AF(GPIOC_HDR_UART2_RX, 8)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SD_DAT0, 12) | \ + PIN_AFIO_AF(GPIOC_SD_DAT1, 12) | \ + PIN_AFIO_AF(GPIOC_SD_DAT2, 12) | \ + PIN_AFIO_AF(GPIOC_SD_DAT3, 12) | \ + PIN_AFIO_AF(GPIOC_SD_CLK, 12) | \ + PIN_AFIO_AF(GPIOC_HDR_GPIO2, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0)) + +/* + * GPIOD setup: + * + * PD0 - HDR_CAN_RX (alternate 9). + * PD1 - HDR_CAN_TX (alternate 9). + * PD2 - SD_CMD (alternate 12). + * PD3 - SD_CD (output pushpull maximum). + * PD4 - TFT_TE (input pullup). + * PD5 - HDR_UART1_TX (alternate 7). + * PD6 - USB_PSW (output opendrain maximum). + * PD7 - USB_VBUS_ER (input floating). + * PD8 - MP3_RST (output pushpull maximum). + * PD9 - MP3_DREQ (input pullup). + * PD10 - MP3_DCS (output pushpull maximum). + * PD11 - MP3_CS (output pushpull maximum). + * PD12 - HDR_PWM0 (alternate 2). + * PD13 - HDR_PWM1 (output pushpull maximum). + * PD14 - HDR_PWM2 (alternate 2). + * PD15 - HDR_PWM3 (output pushpull maximum). + */ +#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_HDR_CAN_RX) | \ + PIN_MODE_ALTERNATE(GPIOD_HDR_CAN_TX) | \ + PIN_MODE_ALTERNATE(GPIOD_SD_CMD) | \ + PIN_MODE_OUTPUT(GPIOD_SD_CD) | \ + PIN_MODE_INPUT(GPIOD_TFT_TE) | \ + PIN_MODE_ALTERNATE(GPIOD_HDR_UART1_TX) |\ + PIN_MODE_OUTPUT(GPIOD_USB_PSW) | \ + PIN_MODE_INPUT(GPIOD_USB_VBUS_ER) | \ + PIN_MODE_OUTPUT(GPIOD_MP3_RST) | \ + PIN_MODE_INPUT(GPIOD_MP3_DREQ) | \ + PIN_MODE_OUTPUT(GPIOD_MP3_DCS) | \ + PIN_MODE_OUTPUT(GPIOD_MP3_CS) | \ + PIN_MODE_ALTERNATE(GPIOD_HDR_PWM0) | \ + PIN_MODE_OUTPUT(GPIOD_HDR_PWM1) | \ + PIN_MODE_ALTERNATE(GPIOD_HDR_PWM2) | \ + PIN_MODE_OUTPUT(GPIOD_HDR_PWM3)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_HDR_CAN_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_HDR_CAN_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SD_CMD) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SD_CD) | \ + PIN_OTYPE_PUSHPULL(GPIOD_TFT_TE) | \ + PIN_OTYPE_PUSHPULL(GPIOD_HDR_UART1_TX) |\ + PIN_OTYPE_OPENDRAIN(GPIOD_USB_PSW) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USB_VBUS_ER) |\ + PIN_OTYPE_PUSHPULL(GPIOD_MP3_RST) | \ + PIN_OTYPE_PUSHPULL(GPIOD_MP3_DREQ) | \ + PIN_OTYPE_PUSHPULL(GPIOD_MP3_DCS) | \ + PIN_OTYPE_PUSHPULL(GPIOD_MP3_CS) | \ + PIN_OTYPE_PUSHPULL(GPIOD_HDR_PWM0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_HDR_PWM1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_HDR_PWM2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_HDR_PWM3)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_HDR_CAN_RX) | \ + PIN_OSPEED_100M(GPIOD_HDR_CAN_TX) | \ + PIN_OSPEED_100M(GPIOD_SD_CMD) | \ + PIN_OSPEED_100M(GPIOD_SD_CD) | \ + PIN_OSPEED_100M(GPIOD_TFT_TE) | \ + PIN_OSPEED_100M(GPIOD_HDR_UART1_TX) | \ + PIN_OSPEED_100M(GPIOD_USB_PSW) | \ + PIN_OSPEED_100M(GPIOD_USB_VBUS_ER) | \ + PIN_OSPEED_100M(GPIOD_MP3_RST) | \ + PIN_OSPEED_100M(GPIOD_MP3_DREQ) | \ + PIN_OSPEED_100M(GPIOD_MP3_DCS) | \ + PIN_OSPEED_100M(GPIOD_MP3_CS) | \ + PIN_OSPEED_100M(GPIOD_HDR_PWM0) | \ + PIN_OSPEED_100M(GPIOD_HDR_PWM1) | \ + PIN_OSPEED_100M(GPIOD_HDR_PWM2) | \ + PIN_OSPEED_100M(GPIOD_HDR_PWM3)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_HDR_CAN_RX) | \ + PIN_PUPDR_FLOATING(GPIOD_HDR_CAN_TX) | \ + PIN_PUPDR_FLOATING(GPIOD_SD_CMD) | \ + PIN_PUPDR_FLOATING(GPIOD_SD_CD) | \ + PIN_PUPDR_PULLUP(GPIOD_TFT_TE) | \ + PIN_PUPDR_FLOATING(GPIOD_HDR_UART1_TX) |\ + PIN_PUPDR_FLOATING(GPIOD_USB_PSW) | \ + PIN_PUPDR_FLOATING(GPIOD_USB_VBUS_ER) |\ + PIN_PUPDR_FLOATING(GPIOD_MP3_RST) | \ + PIN_PUPDR_PULLUP(GPIOD_MP3_DREQ) | \ + PIN_PUPDR_FLOATING(GPIOD_MP3_DCS) | \ + PIN_PUPDR_FLOATING(GPIOD_MP3_CS) | \ + PIN_PUPDR_FLOATING(GPIOD_HDR_PWM0) | \ + PIN_PUPDR_FLOATING(GPIOD_HDR_PWM1) | \ + PIN_PUPDR_FLOATING(GPIOD_HDR_PWM2) | \ + PIN_PUPDR_PULLDOWN(GPIOD_HDR_PWM3)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_HDR_CAN_RX) | \ + PIN_ODR_HIGH(GPIOD_HDR_CAN_TX) | \ + PIN_ODR_HIGH(GPIOD_SD_CMD) | \ + PIN_ODR_HIGH(GPIOD_SD_CD) | \ + PIN_ODR_HIGH(GPIOD_TFT_TE) | \ + PIN_ODR_HIGH(GPIOD_HDR_UART1_TX) | \ + PIN_ODR_HIGH(GPIOD_USB_PSW) | \ + PIN_ODR_HIGH(GPIOD_USB_VBUS_ER) | \ + PIN_ODR_LOW(GPIOD_MP3_RST) | \ + PIN_ODR_HIGH(GPIOD_MP3_DREQ) | \ + PIN_ODR_LOW(GPIOD_MP3_DCS) | \ + PIN_ODR_HIGH(GPIOD_MP3_CS) | \ + PIN_ODR_LOW(GPIOD_HDR_PWM0) | \ + PIN_ODR_LOW(GPIOD_HDR_PWM1) | \ + PIN_ODR_LOW(GPIOD_HDR_PWM2) | \ + PIN_ODR_HIGH(GPIOD_HDR_PWM3)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_HDR_CAN_RX, 9) | \ + PIN_AFIO_AF(GPIOD_HDR_CAN_TX, 9) | \ + PIN_AFIO_AF(GPIOD_SD_CMD, 12) | \ + PIN_AFIO_AF(GPIOD_SD_CD, 0) | \ + PIN_AFIO_AF(GPIOD_TFT_TE, 0) | \ + PIN_AFIO_AF(GPIOD_HDR_UART1_TX, 7) | \ + PIN_AFIO_AF(GPIOD_USB_PSW, 0) | \ + PIN_AFIO_AF(GPIOD_USB_VBUS_ER, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_MP3_RST, 0) | \ + PIN_AFIO_AF(GPIOD_MP3_DREQ, 0) | \ + PIN_AFIO_AF(GPIOD_MP3_DCS, 0) | \ + PIN_AFIO_AF(GPIOD_MP3_CS, 0) | \ + PIN_AFIO_AF(GPIOD_HDR_PWM0, 2) | \ + PIN_AFIO_AF(GPIOD_HDR_PWM1, 0) | \ + PIN_AFIO_AF(GPIOD_HDR_PWM2, 2) | \ + PIN_AFIO_AF(GPIOD_HDR_PWM3, 2)) + +/* + * GPIOE setup: + * + * PE0 - HDR_INT0 (input pullup). + * PE1 - HDR_INT1 (input pullup). + * PE2 - HDR_INT2 (input pullup). + * PE3 - HDR_INT3 (output pushpull maximum). + * PE4 - HDR_GPIO1 (input pullup). + * PE5 - HDR_PWM4 (alternate 3). + * PE6 - HDR_PWM5 (alternate 3). + * PE7 - TFT_GPIO0 (input floating). + * PE8 - TFT_D8 (input floating). + * PE9 - TFT_D9 (input floating). + * PE10 - TFT_D10 (input floating). + * PE11 - TFT_D11 (input floating). + * PE12 - TFT_D12 (input floating). + * PE13 - TFT_D13 (input floating). + * PE14 - TFT_D14 (input floating). + * PE15 - TFT_D15 (input floating). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_HDR_INT0) | \ + PIN_MODE_INPUT(GPIOE_HDR_INT1) | \ + PIN_MODE_INPUT(GPIOE_HDR_INT2) | \ + PIN_MODE_OUTPUT(GPIOE_HDR_INT3) | \ + PIN_MODE_INPUT(GPIOE_HDR_GPIO1) | \ + PIN_MODE_ALTERNATE(GPIOE_HDR_PWM4) | \ + PIN_MODE_ALTERNATE(GPIOE_HDR_PWM5) | \ + PIN_MODE_INPUT(GPIOE_TFT_GPIO0) | \ + PIN_MODE_INPUT(GPIOE_TFT_D8) | \ + PIN_MODE_INPUT(GPIOE_TFT_D9) | \ + PIN_MODE_INPUT(GPIOE_TFT_D10) | \ + PIN_MODE_INPUT(GPIOE_TFT_D11) | \ + PIN_MODE_INPUT(GPIOE_TFT_D12) | \ + PIN_MODE_INPUT(GPIOE_TFT_D13) | \ + PIN_MODE_INPUT(GPIOE_TFT_D14) | \ + PIN_MODE_INPUT(GPIOE_TFT_D15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_HDR_INT0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_HDR_INT1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_HDR_INT2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_HDR_INT3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_HDR_GPIO1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_HDR_PWM4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_HDR_PWM5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_TFT_GPIO0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_TFT_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_TFT_D9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_TFT_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_TFT_D11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_TFT_D12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_TFT_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_TFT_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_TFT_D15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_HDR_INT0) | \ + PIN_OSPEED_100M(GPIOE_HDR_INT1) | \ + PIN_OSPEED_100M(GPIOE_HDR_INT2) | \ + PIN_OSPEED_100M(GPIOE_HDR_INT3) | \ + PIN_OSPEED_100M(GPIOE_HDR_GPIO1) | \ + PIN_OSPEED_100M(GPIOE_HDR_PWM4) | \ + PIN_OSPEED_100M(GPIOE_HDR_PWM5) | \ + PIN_OSPEED_100M(GPIOE_TFT_GPIO0) | \ + PIN_OSPEED_100M(GPIOE_TFT_D8) | \ + PIN_OSPEED_100M(GPIOE_TFT_D9) | \ + PIN_OSPEED_100M(GPIOE_TFT_D10) | \ + PIN_OSPEED_100M(GPIOE_TFT_D11) | \ + PIN_OSPEED_100M(GPIOE_TFT_D12) | \ + PIN_OSPEED_100M(GPIOE_TFT_D13) | \ + PIN_OSPEED_100M(GPIOE_TFT_D14) | \ + PIN_OSPEED_100M(GPIOE_TFT_D15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_HDR_INT0) | \ + PIN_PUPDR_PULLUP(GPIOE_HDR_INT1) | \ + PIN_PUPDR_PULLUP(GPIOE_HDR_INT2) | \ + PIN_PUPDR_PULLDOWN(GPIOE_HDR_INT3) | \ + PIN_PUPDR_PULLUP(GPIOE_HDR_GPIO1) | \ + PIN_PUPDR_FLOATING(GPIOE_HDR_PWM4) | \ + PIN_PUPDR_FLOATING(GPIOE_HDR_PWM5) | \ + PIN_PUPDR_FLOATING(GPIOE_TFT_GPIO0) | \ + PIN_PUPDR_FLOATING(GPIOE_TFT_D8) | \ + PIN_PUPDR_FLOATING(GPIOE_TFT_D9) | \ + PIN_PUPDR_FLOATING(GPIOE_TFT_D10) | \ + PIN_PUPDR_FLOATING(GPIOE_TFT_D11) | \ + PIN_PUPDR_FLOATING(GPIOE_TFT_D12) | \ + PIN_PUPDR_FLOATING(GPIOE_TFT_D13) | \ + PIN_PUPDR_FLOATING(GPIOE_TFT_D14) | \ + PIN_PUPDR_FLOATING(GPIOE_TFT_D15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_HDR_INT0) | \ + PIN_ODR_HIGH(GPIOE_HDR_INT1) | \ + PIN_ODR_HIGH(GPIOE_HDR_INT2) | \ + PIN_ODR_HIGH(GPIOE_HDR_INT3) | \ + PIN_ODR_HIGH(GPIOE_HDR_GPIO1) | \ + PIN_ODR_HIGH(GPIOE_HDR_PWM4) | \ + PIN_ODR_HIGH(GPIOE_HDR_PWM5) | \ + PIN_ODR_HIGH(GPIOE_TFT_GPIO0) | \ + PIN_ODR_HIGH(GPIOE_TFT_D8) | \ + PIN_ODR_HIGH(GPIOE_TFT_D9) | \ + PIN_ODR_HIGH(GPIOE_TFT_D10) | \ + PIN_ODR_HIGH(GPIOE_TFT_D11) | \ + PIN_ODR_HIGH(GPIOE_TFT_D12) | \ + PIN_ODR_HIGH(GPIOE_TFT_D13) | \ + PIN_ODR_HIGH(GPIOE_TFT_D14) | \ + PIN_ODR_HIGH(GPIOE_TFT_D15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_HDR_INT0, 0) | \ + PIN_AFIO_AF(GPIOE_HDR_INT1, 0) | \ + PIN_AFIO_AF(GPIOE_HDR_INT2, 0) | \ + PIN_AFIO_AF(GPIOE_HDR_INT3, 0) | \ + PIN_AFIO_AF(GPIOE_HDR_GPIO1, 0) | \ + PIN_AFIO_AF(GPIOE_HDR_PWM4, 3) | \ + PIN_AFIO_AF(GPIOE_HDR_PWM5, 3) | \ + PIN_AFIO_AF(GPIOE_TFT_GPIO0, 0)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_TFT_D8, 0) | \ + PIN_AFIO_AF(GPIOE_TFT_D9, 0) | \ + PIN_AFIO_AF(GPIOE_TFT_D10, 0) | \ + PIN_AFIO_AF(GPIOE_TFT_D11, 0) | \ + PIN_AFIO_AF(GPIOE_TFT_D12, 0) | \ + PIN_AFIO_AF(GPIOE_TFT_D13, 0) | \ + PIN_AFIO_AF(GPIOE_TFT_D14, 0) | \ + PIN_AFIO_AF(GPIOE_TFT_D15, 0)) + +/* + * GPIOF setup: + * + * PF0 - HDR_I2C2_SDA (alternate 4). + * PF1 - HDR_I2C2_SCL (alternate 4). + * PF2 - PIN2 (input floating). + * PF3 - DC_VBUS (input floating). + * PF4 - BAT_STAT (input floating). + * PF5 - LAN_INT (input pullup). + * PF6 - AN_BAT_VSENSE (analog). + * PF7 - PIN7 (input floating). + * PF8 - AN_TEMP (analog). + * PF9 - AN_PD (analog). + * PF10 - PIN10 (input floating). + * PF11 - TFT_WR (output pushpull maximum). + * PF12 - TFT_RD (output pushpull maximum). + * PF13 - TFT_CS (output pushpull maximum). + * PF14 - TFT_RST (output pushpull maximum). + * PF15 - TFT_DC (output pushpull maximum). + */ +#define VAL_GPIOF_MODER (PIN_MODE_ALTERNATE(GPIOF_HDR_I2C2_SDA) |\ + PIN_MODE_ALTERNATE(GPIOF_HDR_I2C2_SCL) |\ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_DC_VBUS) | \ + PIN_MODE_INPUT(GPIOF_BAT_STAT) | \ + PIN_MODE_INPUT(GPIOF_LAN_INT) | \ + PIN_MODE_ANALOG(GPIOF_AN_BAT_VSENSE) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_ANALOG(GPIOF_AN_TEMP) | \ + PIN_MODE_ANALOG(GPIOF_AN_PD) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_OUTPUT(GPIOF_TFT_WR) | \ + PIN_MODE_OUTPUT(GPIOF_TFT_RD) | \ + PIN_MODE_OUTPUT(GPIOF_TFT_CS) | \ + PIN_MODE_OUTPUT(GPIOF_TFT_RST) | \ + PIN_MODE_OUTPUT(GPIOF_TFT_DC)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_HDR_I2C2_SDA) |\ + PIN_OTYPE_PUSHPULL(GPIOF_HDR_I2C2_SCL) |\ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_DC_VBUS) | \ + PIN_OTYPE_PUSHPULL(GPIOF_BAT_STAT) | \ + PIN_OTYPE_PUSHPULL(GPIOF_LAN_INT) | \ + PIN_OTYPE_PUSHPULL(GPIOF_AN_BAT_VSENSE) |\ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_AN_TEMP) | \ + PIN_OTYPE_PUSHPULL(GPIOF_AN_PD) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_TFT_WR) | \ + PIN_OTYPE_PUSHPULL(GPIOF_TFT_RD) | \ + PIN_OTYPE_PUSHPULL(GPIOF_TFT_CS) | \ + PIN_OTYPE_PUSHPULL(GPIOF_TFT_RST) | \ + PIN_OTYPE_PUSHPULL(GPIOF_TFT_DC)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_HDR_I2C2_SDA) | \ + PIN_OSPEED_100M(GPIOF_HDR_I2C2_SCL) | \ + PIN_OSPEED_100M(GPIOF_PIN2) | \ + PIN_OSPEED_100M(GPIOF_DC_VBUS) | \ + PIN_OSPEED_100M(GPIOF_BAT_STAT) | \ + PIN_OSPEED_100M(GPIOF_LAN_INT) | \ + PIN_OSPEED_100M(GPIOF_AN_BAT_VSENSE) | \ + PIN_OSPEED_100M(GPIOF_PIN7) | \ + PIN_OSPEED_100M(GPIOF_AN_TEMP) | \ + PIN_OSPEED_100M(GPIOF_AN_PD) | \ + PIN_OSPEED_100M(GPIOF_PIN10) | \ + PIN_OSPEED_100M(GPIOF_TFT_WR) | \ + PIN_OSPEED_100M(GPIOF_TFT_RD) | \ + PIN_OSPEED_100M(GPIOF_TFT_CS) | \ + PIN_OSPEED_100M(GPIOF_TFT_RST) | \ + PIN_OSPEED_100M(GPIOF_TFT_DC)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_HDR_I2C2_SDA) | \ + PIN_PUPDR_PULLUP(GPIOF_HDR_I2C2_SCL) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOF_DC_VBUS) | \ + PIN_PUPDR_FLOATING(GPIOF_BAT_STAT) | \ + PIN_PUPDR_PULLUP(GPIOF_LAN_INT) | \ + PIN_PUPDR_FLOATING(GPIOF_AN_BAT_VSENSE) |\ + PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOF_AN_TEMP) | \ + PIN_PUPDR_FLOATING(GPIOF_AN_PD) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOF_TFT_WR) | \ + PIN_PUPDR_FLOATING(GPIOF_TFT_RD) | \ + PIN_PUPDR_FLOATING(GPIOF_TFT_CS) | \ + PIN_PUPDR_FLOATING(GPIOF_TFT_RST) | \ + PIN_PUPDR_FLOATING(GPIOF_TFT_DC)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_HDR_I2C2_SDA) | \ + PIN_ODR_HIGH(GPIOF_HDR_I2C2_SCL) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_DC_VBUS) | \ + PIN_ODR_HIGH(GPIOF_BAT_STAT) | \ + PIN_ODR_HIGH(GPIOF_LAN_INT) | \ + PIN_ODR_HIGH(GPIOF_AN_BAT_VSENSE) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_AN_TEMP) | \ + PIN_ODR_HIGH(GPIOF_AN_PD) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_TFT_WR) | \ + PIN_ODR_HIGH(GPIOF_TFT_RD) | \ + PIN_ODR_HIGH(GPIOF_TFT_CS) | \ + PIN_ODR_LOW(GPIOF_TFT_RST) | \ + PIN_ODR_HIGH(GPIOF_TFT_DC)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_HDR_I2C2_SDA, 4) | \ + PIN_AFIO_AF(GPIOF_HDR_I2C2_SCL, 4) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0) | \ + PIN_AFIO_AF(GPIOF_DC_VBUS, 0) | \ + PIN_AFIO_AF(GPIOF_BAT_STAT, 0) | \ + PIN_AFIO_AF(GPIOF_LAN_INT, 0) | \ + PIN_AFIO_AF(GPIOF_AN_BAT_VSENSE, 0) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_AN_TEMP, 0) | \ + PIN_AFIO_AF(GPIOF_AN_PD, 0) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0) | \ + PIN_AFIO_AF(GPIOF_TFT_WR, 0) | \ + PIN_AFIO_AF(GPIOF_TFT_RD, 0) | \ + PIN_AFIO_AF(GPIOF_TFT_CS, 0) | \ + PIN_AFIO_AF(GPIOF_TFT_RST, 0) | \ + PIN_AFIO_AF(GPIOF_TFT_DC, 0)) + +/* + * GPIOG setup: + * + * PG0 - TFT_D0 (input floating). + * PG1 - TFT_D1 (input floating). + * PG2 - TFT_D2 (input floating). + * PG3 - TFT_D3 (input floating). + * PG4 - TFT_D4 (input floating). + * PG5 - TFT_D5 (input floating). + * PG6 - TFT_D6 (input floating). + * PG7 - TFT_D7 (input floating). + * PG8 - LAN_RST (output pushpull maximum). + * PG9 - RF_CS (output pushpull maximum). + * PG10 - RF_INT (input pullup). + * PG11 - LAN_TXEN (alternate 11). + * PG12 - RF_CE (output pushpull maximum). + * PG13 - LAN_TXD0 (alternate 11). + * PG14 - LAN_TXD1 (alternate 11). + * PG15 - LED_R (output pushpull maximum). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_TFT_D0) | \ + PIN_MODE_INPUT(GPIOG_TFT_D1) | \ + PIN_MODE_INPUT(GPIOG_TFT_D2) | \ + PIN_MODE_INPUT(GPIOG_TFT_D3) | \ + PIN_MODE_INPUT(GPIOG_TFT_D4) | \ + PIN_MODE_INPUT(GPIOG_TFT_D5) | \ + PIN_MODE_INPUT(GPIOG_TFT_D6) | \ + PIN_MODE_INPUT(GPIOG_TFT_D7) | \ + PIN_MODE_OUTPUT(GPIOG_LAN_RST) | \ + PIN_MODE_OUTPUT(GPIOG_RF_CS) | \ + PIN_MODE_INPUT(GPIOG_RF_INT) | \ + PIN_MODE_ALTERNATE(GPIOG_LAN_TXEN) | \ + PIN_MODE_OUTPUT(GPIOG_RF_CE) | \ + PIN_MODE_ALTERNATE(GPIOG_LAN_TXD0) | \ + PIN_MODE_ALTERNATE(GPIOG_LAN_TXD1) | \ + PIN_MODE_OUTPUT(GPIOG_LED_R)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_TFT_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_TFT_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_TFT_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_TFT_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_TFT_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_TFT_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_TFT_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOG_TFT_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LAN_RST) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RF_CS) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RF_INT) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LAN_TXEN) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RF_CE) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LAN_TXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LAN_TXD1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LED_R)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_TFT_D0) | \ + PIN_OSPEED_100M(GPIOG_TFT_D1) | \ + PIN_OSPEED_100M(GPIOG_TFT_D2) | \ + PIN_OSPEED_100M(GPIOG_TFT_D3) | \ + PIN_OSPEED_100M(GPIOG_TFT_D4) | \ + PIN_OSPEED_100M(GPIOG_TFT_D5) | \ + PIN_OSPEED_100M(GPIOG_TFT_D6) | \ + PIN_OSPEED_100M(GPIOG_TFT_D7) | \ + PIN_OSPEED_100M(GPIOG_LAN_RST) | \ + PIN_OSPEED_100M(GPIOG_RF_CS) | \ + PIN_OSPEED_100M(GPIOG_RF_INT) | \ + PIN_OSPEED_100M(GPIOG_LAN_TXEN) | \ + PIN_OSPEED_100M(GPIOG_RF_CE) | \ + PIN_OSPEED_100M(GPIOG_LAN_TXD0) | \ + PIN_OSPEED_100M(GPIOG_LAN_TXD1) | \ + PIN_OSPEED_100M(GPIOG_LED_R)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_TFT_D0) | \ + PIN_PUPDR_FLOATING(GPIOG_TFT_D1) | \ + PIN_PUPDR_FLOATING(GPIOG_TFT_D2) | \ + PIN_PUPDR_FLOATING(GPIOG_TFT_D3) | \ + PIN_PUPDR_FLOATING(GPIOG_TFT_D4) | \ + PIN_PUPDR_FLOATING(GPIOG_TFT_D5) | \ + PIN_PUPDR_FLOATING(GPIOG_TFT_D6) | \ + PIN_PUPDR_FLOATING(GPIOG_TFT_D7) | \ + PIN_PUPDR_FLOATING(GPIOG_LAN_RST) | \ + PIN_PUPDR_FLOATING(GPIOG_RF_CS) | \ + PIN_PUPDR_PULLUP(GPIOG_RF_INT) | \ + PIN_PUPDR_FLOATING(GPIOG_LAN_TXEN) | \ + PIN_PUPDR_FLOATING(GPIOG_RF_CE) | \ + PIN_PUPDR_FLOATING(GPIOG_LAN_TXD0) | \ + PIN_PUPDR_FLOATING(GPIOG_LAN_TXD1) | \ + PIN_PUPDR_FLOATING(GPIOG_LED_R)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_TFT_D0) | \ + PIN_ODR_HIGH(GPIOG_TFT_D1) | \ + PIN_ODR_HIGH(GPIOG_TFT_D2) | \ + PIN_ODR_HIGH(GPIOG_TFT_D3) | \ + PIN_ODR_HIGH(GPIOG_TFT_D4) | \ + PIN_ODR_HIGH(GPIOG_TFT_D5) | \ + PIN_ODR_HIGH(GPIOG_TFT_D6) | \ + PIN_ODR_HIGH(GPIOG_TFT_D7) | \ + PIN_ODR_HIGH(GPIOG_LAN_RST) | \ + PIN_ODR_HIGH(GPIOG_RF_CS) | \ + PIN_ODR_HIGH(GPIOG_RF_INT) | \ + PIN_ODR_HIGH(GPIOG_LAN_TXEN) | \ + PIN_ODR_LOW(GPIOG_RF_CE) | \ + PIN_ODR_HIGH(GPIOG_LAN_TXD0) | \ + PIN_ODR_HIGH(GPIOG_LAN_TXD1) | \ + PIN_ODR_LOW(GPIOG_LED_R)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_TFT_D0, 0) | \ + PIN_AFIO_AF(GPIOG_TFT_D1, 0) | \ + PIN_AFIO_AF(GPIOG_TFT_D2, 0) | \ + PIN_AFIO_AF(GPIOG_TFT_D3, 0) | \ + PIN_AFIO_AF(GPIOG_TFT_D4, 0) | \ + PIN_AFIO_AF(GPIOG_TFT_D5, 0) | \ + PIN_AFIO_AF(GPIOG_TFT_D6, 0) | \ + PIN_AFIO_AF(GPIOG_TFT_D7, 0)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_LAN_RST, 11) | \ + PIN_AFIO_AF(GPIOG_RF_CS, 0) | \ + PIN_AFIO_AF(GPIOG_RF_INT, 0) | \ + PIN_AFIO_AF(GPIOG_LAN_TXEN, 11) | \ + PIN_AFIO_AF(GPIOG_RF_CE, 0) | \ + PIN_AFIO_AF(GPIOG_LAN_TXD0, 11) | \ + PIN_AFIO_AF(GPIOG_LAN_TXD1, 11) | \ + PIN_AFIO_AF(GPIOG_LED_R, 0)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input floating). + * PH3 - PIN3 (input floating). + * PH4 - PIN4 (input floating). + * PH5 - PIN5 (input floating). + * PH6 - PIN6 (input floating). + * PH7 - PIN7 (input floating). + * PH8 - PIN8 (input floating). + * PH9 - PIN9 (input floating). + * PH10 - PIN10 (input floating). + * PH11 - PIN11 (input floating). + * PH12 - PIN12 (input floating). + * PH13 - PIN13 (input floating). + * PH14 - PIN14 (input floating). + * PH15 - PIN15 (input floating). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \ + PIN_OSPEED_100M(GPIOH_OSC_OUT) | \ + PIN_OSPEED_100M(GPIOH_PIN2) | \ + PIN_OSPEED_100M(GPIOH_PIN3) | \ + PIN_OSPEED_100M(GPIOH_PIN4) | \ + PIN_OSPEED_100M(GPIOH_PIN5) | \ + PIN_OSPEED_100M(GPIOH_PIN6) | \ + PIN_OSPEED_100M(GPIOH_PIN7) | \ + PIN_OSPEED_100M(GPIOH_PIN8) | \ + PIN_OSPEED_100M(GPIOH_PIN9) | \ + PIN_OSPEED_100M(GPIOH_PIN10) | \ + PIN_OSPEED_100M(GPIOH_PIN11) | \ + PIN_OSPEED_100M(GPIOH_PIN12) | \ + PIN_OSPEED_100M(GPIOH_PIN13) | \ + PIN_OSPEED_100M(GPIOH_PIN14) | \ + PIN_OSPEED_100M(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input floating). + * PI1 - PIN1 (input floating). + * PI2 - PIN2 (input floating). + * PI3 - PIN3 (input floating). + * PI4 - PIN4 (input floating). + * PI5 - PIN5 (input floating). + * PI6 - PIN6 (input floating). + * PI7 - PIN7 (input floating). + * PI8 - PIN8 (input floating). + * PI9 - PIN9 (input floating). + * PI10 - PIN10 (input floating). + * PI11 - PIN11 (input floating). + * PI12 - PIN12 (input floating). + * PI13 - PIN13 (input floating). + * PI14 - PIN14 (input floating). + * PI15 - PIN15 (input floating). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \ + PIN_OSPEED_100M(GPIOI_PIN1) | \ + PIN_OSPEED_100M(GPIOI_PIN2) | \ + PIN_OSPEED_100M(GPIOI_PIN3) | \ + PIN_OSPEED_100M(GPIOI_PIN4) | \ + PIN_OSPEED_100M(GPIOI_PIN5) | \ + PIN_OSPEED_100M(GPIOI_PIN6) | \ + PIN_OSPEED_100M(GPIOI_PIN7) | \ + PIN_OSPEED_100M(GPIOI_PIN8) | \ + PIN_OSPEED_100M(GPIOI_PIN9) | \ + PIN_OSPEED_100M(GPIOI_PIN10) | \ + PIN_OSPEED_100M(GPIOI_PIN11) | \ + PIN_OSPEED_100M(GPIOI_PIN12) | \ + PIN_OSPEED_100M(GPIOI_PIN13) | \ + PIN_OSPEED_100M(GPIOI_PIN14) | \ + PIN_OSPEED_100M(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/board.mk b/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/board.mk new file mode 100644 index 00000000..c47cf5a2 --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/board.mk @@ -0,0 +1,6 @@ +# Required include directories +BOARDINC = $(GFXLIB)/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board + +# List of all the board related files. +BOARDSRC = $(BOARDINC)/board.c +# $(BOARDINC)/flash_memory.c - To be tested before it is added as standard
\ No newline at end of file diff --git a/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/cfg/board.chcfg b/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/cfg/board.chcfg new file mode 100644 index 00000000..8e30a5a3 --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/cfg/board.chcfg @@ -0,0 +1,1197 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- STM32F4xx board Template --> +<board + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" + xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f4xx_board.xsd"> + <configuration_settings> + <templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path> + <output_path>..</output_path> + <hal_version>3.0.x</hal_version> + </configuration_settings> + <board_name>ST_MIKROMEDIA_PLUS_STM32</board_name> + <board_id>ST_MIKROMEDIA_PLUS_STM32</board_id> + <board_functions></board_functions> + <ethernet_phy> + <identifier>MII_LAN8720_ID</identifier> + <bus_type>RMII</bus_type> + </ethernet_phy> + <subtype>STM32F407xx</subtype> + <clocks + HSEFrequency="25000000" + HSEBypass="false" + LSEFrequency="32768" + LSEBypass="false" + VDD="330" ></clocks> + <ports> + <GPIOA> + <pin0 + ID="TP_INT" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin1 + ID="LAN_SCL" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="11" /> + <pin2 + ID="LAN_MDIO" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="11" /> + <pin3 + ID="HDR_UART1_RX" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="7" /> + <pin4 + ID="HDR_AN0" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="SPI1_SCK" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="5" /> + <pin6 + ID="SPI1_MISO" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="5" /> + <pin7 + ID="LAN_CRS_DV" + Type="PushPull" + Level="High" + Speed="High" + Resistor="Floating" + Mode="Alternate" + Alternate="11" /> + <pin8 + ID="LAN_CLK" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="0" ></pin8> + <pin9 + ID="USB_VBUS" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin10 + ID="USB_ID" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="10" /> + <pin11 + ID="USB_DN" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="10" /> + <pin12 + ID="USB_DP" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="10" /> + <pin13 + ID="SWDIO" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="0" /> + <pin14 + ID="SWCLK" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="0" /> + <pin15 + ID="HDR_SPI1_SS" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + </GPIOA> + <GPIOB> + <pin0 + ID="HDR_AN1" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="HDR_AN2" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="GND" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin3 + ID="LED_G" + Type="PushPull" + Level="Low" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" ></pin3> + <pin4 + ID="LED_B" + Type="PushPull" + Level="Low" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" ></pin4> + <pin5 + ID="SPI1_MOSI" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="5" /> + <pin6 + ID="I2C1_SCL" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="4" /> + <pin7 + ID="I2C1_SDA" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="4" /> + <pin8 + ID="BUZZER" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" ></pin8> + <pin9 + ID="ACCEL_INT" + Type="OpenDrain" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" ></pin9> + <pin10 + ID="RC5_TX" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="7" /> + <pin11 + ID="FLASH_CS" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin12 + ID="HDR_SPI2_SS" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="5" /> + <pin13 + ID="SPI2_SCK" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="5" /> + <pin14 + ID="SPI2_MISO" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="5" /> + <pin15 + ID="SPI2_MOSI" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="5" /> + </GPIOB> + <GPIOC> + <pin0 + ID="HDR_AN3" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullDown" + Mode="Output" + Alternate="0" ></pin0> + <pin1 + ID="LAN_MDC" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="11" /> + <pin2 + ID="HDR_AN4" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin3 + ID="HDR_AN5" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" ></pin3> + <pin4 + ID="LAN_RXD0" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="11" /> + <pin5 + ID="LAN_RXD1" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="11" /> + <pin6 + ID="HDR_UART2_TX" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="8" /> + <pin7 + ID="HDR_UART2_RX" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="8" /> + <pin8 + ID="SD_DAT0" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="12" /> + <pin9 + ID="SD_DAT1" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="12" /> + <pin10 + ID="SD_DAT2" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="12" /> + <pin11 + ID="SD_DAT3" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="12" /> + <pin12 + ID="SD_CLK" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="12" /> + <pin13 + ID="HDR_GPIO2" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin14 + ID="OSC32_IN" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin15 + ID="OSC32_OUT" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" ></pin15> + </GPIOC> + <GPIOD> + <pin0 + ID="HDR_CAN_RX" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="9" /> + <pin1 + ID="HDR_CAN_TX" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="9" /> + <pin2 + ID="SD_CMD" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="12" /> + <pin3 + ID="SD_CD" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin4 + ID="TFT_TE" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="HDR_UART1_TX" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="7" ></pin5> + <pin6 + ID="USB_PSW" + Type="OpenDrain" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin7 + ID="USB_VBUS_ER" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin8 + ID="MP3_RST" + Type="PushPull" + Level="Low" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin9 + ID="MP3_DREQ" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin10 + ID="MP3_DCS" + Type="PushPull" + Level="Low" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin11 + ID="MP3_CS" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin12 + ID="HDR_PWM0" + Type="PushPull" + Level="Low" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="2" ></pin12> + <pin13 + ID="HDR_PWM1" + Type="PushPull" + Level="Low" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin14 + ID="HDR_PWM2" + Type="PushPull" + Level="Low" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="2" ></pin14> + <pin15 + ID="HDR_PWM3" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullDown" + Mode="Output" + Alternate="2" /> + </GPIOD> + <GPIOE> + <pin0 + ID="HDR_INT0" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin1 + ID="HDR_INT1" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin2 + ID="HDR_INT2" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin3 + ID="HDR_INT3" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullDown" + Mode="Output" + Alternate="0" /> + <pin4 + ID="HDR_GPIO1" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin5 + ID="HDR_PWM4" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="3" /> + <pin6 + ID="HDR_PWM5" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="3" /> + <pin7 + ID="TFT_GPIO0" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin8 + ID="TFT_D8" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin9 + ID="TFT_D9" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin10 + ID="TFT_D10" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin11 + ID="TFT_D11" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin12 + ID="TFT_D12" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin13 + ID="TFT_D13" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin14 + ID="TFT_D14" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin15 + ID="TFT_D15" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + </GPIOE> + <GPIOF> + <pin0 + ID="HDR_I2C2_SDA" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="4" /> + <pin1 + ID="HDR_I2C2_SCL" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Alternate" + Alternate="4" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin3 + ID="DC_VBUS" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin4 + ID="BAT_STAT" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin5 + ID="LAN_INT" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin6 + ID="AN_BAT_VSENSE" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin8 + ID="AN_TEMP" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" /> + <pin9 + ID="AN_PD" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Analog" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin11 + ID="TFT_WR" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin12 + ID="TFT_RD" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin13 + ID="TFT_CS" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin14 + ID="TFT_RST" + Type="PushPull" + Level="Low" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin15 + ID="TFT_DC" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + </GPIOF> + <GPIOG> + <pin0 + ID="TFT_D0" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin1 + ID="TFT_D1" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin2 + ID="TFT_D2" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin3 + ID="TFT_D3" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin4 + ID="TFT_D4" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin5 + ID="TFT_D5" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin6 + ID="TFT_D6" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin7 + ID="TFT_D7" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin8 + ID="LAN_RST" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="11" /> + <pin9 + ID="RF_CS" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" ></pin9> + <pin10 + ID="RF_INT" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="PullUp" + Mode="Input" + Alternate="0" /> + <pin11 + ID="LAN_TXEN" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="11" /> + <pin12 + ID="RF_CE" + Type="PushPull" + Level="Low" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + <pin13 + ID="LAN_TXD0" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="11" /> + <pin14 + ID="LAN_TXD1" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Alternate" + Alternate="11" /> + <pin15 + ID="LED_R" + Type="PushPull" + Level="Low" + Speed="Maximum" + Resistor="Floating" + Mode="Output" + Alternate="0" /> + </GPIOG> + <GPIOH> + <pin0 + ID="OSC_IN" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin1 + ID="OSC_OUT" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" ></pin2> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + </GPIOH> + <GPIOI> + <pin0 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin1 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin2 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin3 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin4 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin5 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin6 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin7 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin8 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin9 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin10 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin11 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin12 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin13 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin14 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + <pin15 + ID="" + Type="PushPull" + Level="High" + Speed="Maximum" + Resistor="Floating" + Mode="Input" + Alternate="0" /> + </GPIOI> + </ports> +</board> diff --git a/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/flash_memory.c b/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/flash_memory.c new file mode 100644 index 00000000..ccd3ab9f --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/flash_memory.c @@ -0,0 +1,127 @@ +#include "hal.h" +#include "flash_memory.h" + +static const unsigned short _SERIAL_FLASH_CMD_RDID = 0x9F; // 25P80 +static const unsigned short _SERIAL_FLASH_CMD_READ = 0x03; +static const unsigned short _SERIAL_FLASH_CMD_WRITE = 0x02; +static const unsigned short _SERIAL_FLASH_CMD_WREN = 0x06; +static const unsigned short _SERIAL_FLASH_CMD_RDSR = 0x05; +static const unsigned short _SERIAL_FLASH_CMD_ERASE = 0xC7; // 25P80 +static const unsigned short _SERIAL_FLASH_CMD_EWSR = 0x06; // 25P80 +static const unsigned short _SERIAL_FLASH_CMD_WRSR = 0x01; +static const unsigned short _SERIAL_FLASH_CMD_SER = 0xD8; //25P80 + +static const SPIConfig flash_spicfg = { + 0, + GPIOD, + GPIOD_FLASH_CS, + 0 +}; + +bool flash_is_write_busy(void) { + static uint8_t is_write_busy_cmd[1]; + is_write_busy_cmd[0] = _SERIAL_FLASH_CMD_RDSR; + + uint8_t result[1]; + + spiAcquireBus(&SPID3); + spiStart(&SPID3, &flash_spicfg); + spiSelect(&SPID3); + spiSend(&SPID3, sizeof(is_write_busy_cmd), is_write_busy_cmd); + spiReceive(&SPID3, sizeof(result), result); + spiUnselect(&SPID3); + spiReleaseBus(&SPID3); + + return result[0]&0x01; +} + +void flash_write_enable(void) { + spiAcquireBus(&SPID3); + spiStart(&SPID3, &flash_spicfg); + spiSelect(&SPID3); + spiSend(&SPID3, 1, &_SERIAL_FLASH_CMD_WREN); + spiUnselect(&SPID3); + spiReleaseBus(&SPID3); +} + +void flash_sector_erase(uint32_t sector) { + flash_write_enable(); + static uint8_t sector_erase_cmd[4]; + sector_erase_cmd[0] = _SERIAL_FLASH_CMD_SER; + sector_erase_cmd[1] = (sector >> 16) & 0xFF; + sector_erase_cmd[2] = (sector >> 8) & 0xFF; + sector_erase_cmd[3] = sector & 0xFF; + + + spiAcquireBus(&SPID3); + spiStart(&SPID3, &flash_spicfg); + spiSelect(&SPID3); + spiSend(&SPID3, sizeof(sector_erase_cmd), sector_erase_cmd); + spiUnselect(&SPID3); + spiReleaseBus(&SPID3); + + /* wait for complete */ + while(flash_is_write_busy()); +} + +void flash_read(uint32_t address, size_t bytes, uint8_t *out) { + static uint8_t sector_read_cmd[4]; + sector_read_cmd[0] = _SERIAL_FLASH_CMD_READ; + sector_read_cmd[1] = (address >> 16) & 0xFF; + sector_read_cmd[2] = (address >> 8) & 0xFF; + sector_read_cmd[3] = address & 0xFF; + + spiAcquireBus(&SPID3); + spiStart(&SPID3, &flash_spicfg); + spiSelect(&SPID3); + spiSend(&SPID3, sizeof(sector_read_cmd), sector_read_cmd); + spiReceive(&SPID3, bytes, out); + spiUnselect(&SPID3); + spiReleaseBus(&SPID3); +} + +void flash_write(uint32_t address, size_t bytes, const uint8_t *data) { + static uint8_t flash_write_cmd[4]; + + flash_write_enable(); + + flash_write_cmd[0] = _SERIAL_FLASH_CMD_WRITE; + flash_write_cmd[1] = (address >> 16) & 0xFF; + flash_write_cmd[2] = (address >> 8) & 0xFF; + flash_write_cmd[3] = address & 0xFF; + + spiAcquireBus(&SPID3); + spiStart(&SPID3, &flash_spicfg); + spiSelect(&SPID3); + spiSend(&SPID3, sizeof(flash_write_cmd), flash_write_cmd); + spiSend(&SPID3, bytes, data); + spiUnselect(&SPID3); + spiReleaseBus(&SPID3); + + /* wait for complete */ + while(flash_is_write_busy()); +} + +bool flash_tp_calibrated(void) { + uint8_t out[1]; + flash_read(0x0F0000, 1, out); + + return (out[0] == 0x01); +} + +void flash_tp_calibration_save(uint16_t instance, const uint8_t *calbuf, size_t sz) { + if (instance) return; + flash_sector_erase(0x0F0000); + uint8_t calibrated = 0x01; + flash_write(0x0F0000, 1, &calibrated); + flash_write(0x0F0001, sz, calbuf); +} +const char *flash_tp_calibration_load(uint16_t instance) { + static uint8_t foo[24]; + + if (instance) return 0; + if (!flash_tp_calibrated()) return 0; + flash_read(0x0F0001, 24, foo); + + return (char *)foo; +} diff --git a/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/flash_memory.h b/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/flash_memory.h new file mode 100644 index 00000000..2dcc9206 --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/flash_memory.h @@ -0,0 +1,6 @@ +void flash_sector_erase(uint32_t sector); +void flash_read(uint32_t address, size_t bytes, uint8_t *out); +void flash_write(uint32_t address, size_t bytes, const uint8_t *data); +bool flash_tp_calibrated(void); +void flash_tp_calibration_save(uint16_t instance, const uint8_t *calbuf, size_t sz); +const char *flash_tp_calibration_load(uint16_t instance); diff --git a/boards/base/Mikromedia-Plus-STM32-M4/board.mk b/boards/base/Mikromedia-Plus-STM32-M4/board.mk new file mode 100644 index 00000000..61a87888 --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/board.mk @@ -0,0 +1,6 @@ +GFXINC += $(GFXLIB)/boards/base/Mikromedia-Plus-STM32-M4 +GFXSRC += +GFXDEFS += -DGFX_USE_OS_CHIBIOS=TRUE +include $(GFXLIB)/drivers/gdisp/SSD1963/driver.mk +include $(GFXLIB)/drivers/ginput/touch/STMPE610/driver.mk +include $(GFXLIB)/drivers/gaudio/vs1053/driver.mk diff --git a/boards/base/Mikromedia-Plus-STM32-M4/board_SSD1963.h b/boards/base/Mikromedia-Plus-STM32-M4/board_SSD1963.h new file mode 100644 index 00000000..b0114ca9 --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/board_SSD1963.h @@ -0,0 +1,134 @@ +/* + * This file is subject to the terms of the GFX License. If a copy of + * the license was not distributed with this file, you can obtain one at: + * + * http://ugfx.org/license.html + */ + +#ifndef _GDISP_LLD_BOARD_H +#define _GDISP_LLD_BOARD_H + +//#define SSD1963_INIT_METHOD_2 TRUE + +static const LCD_Parameters DisplayTimings[] = { + // You need one of these array elements per display + { + 480, 272, // Panel width and height + 2, 2, 41, // Horizontal Timings (back porch, front porch, pulse) + CALC_PERIOD(480,2,2,41), // Total Horizontal Period (calculated from above line) + 2, 2, 10, // Vertical Timings (back porch, front porch, pulse) + CALC_PERIOD(272,2,2,10), // Total Vertical Period (calculated from above line) + CALC_FPR(480,272,2,2,41,2,2,10,73ULL), // FPR - the 60ULL is the frames per second. Note the ULL! + LCD_PANEL_DATA_WIDTH_24BIT | LCD_PANEL_ENABLE_DITHERING + }, +}; + +/* GPIO Pin Config */ +#define GDISP_CMD_PORT GPIOF +#define GDISP_DATA_LO_PORT GPIOG +#define GDISP_DATA_HI_PORT GPIOE + +#define GDISP_WR 11 +#define GDISP_RD 12 +#define GDISP_CS 13 +#define GDISP_RST 14 +#define GDISP_DC 15 + +#define SET_CS palSetPad(GDISP_CMD_PORT, GDISP_CS); +#define CLR_CS palClearPad(GDISP_CMD_PORT, GDISP_CS); +#define SET_RST palSetPad(GDISP_CMD_PORT, GDISP_RST); +#define CLR_RST palClearPad(GDISP_CMD_PORT, GDISP_RST); +#define SET_WR palSetPad(GDISP_CMD_PORT, GDISP_WR); +#define CLR_WR palClearPad(GDISP_CMD_PORT, GDISP_WR); +#define SET_RD palSetPad(GDISP_CMD_PORT, GDISP_RD); +#define CLR_RD palClearPad(GDISP_CMD_PORT, GDISP_RD); +#define SET_DC palSetPad(GDISP_CMD_PORT, GDISP_DC); +#define CLR_DC palClearPad(GDISP_CMD_PORT, GDISP_DC); + +#define writeStrobe { CLR_WR; asm volatile ("nop;"); SET_WR; } + +IOBus busCMD = { GDISP_CMD_PORT, (1 << GDISP_CS) | (1 << GDISP_RST) | (1 << GDISP_WR) | (1 << GDISP_RD) | (1 << GDISP_DC), 11 }; +IOBus busDataLo = { GDISP_DATA_LO_PORT, 0xFF, 0 }; +IOBus busDataHi = { GDISP_DATA_HI_PORT, 0xFF, 8 }; + + +static inline void init_board(GDisplay *g) { + g->board = 0; + switch(g->controllerdisplay) { + case 0: + { + palSetBusMode(&busCMD, PAL_MODE_OUTPUT_PUSHPULL); + palSetBusMode(&busDataLo, PAL_MODE_OUTPUT_PUSHPULL); + palSetBusMode(&busDataHi, PAL_MODE_OUTPUT_PUSHPULL); + SET_CS; SET_WR; SET_RD; SET_DC; SET_RST; + break; + } + default: + break; + } +} + +static inline void post_init_board(GDisplay *g) { + (void) g; +} + +static inline void setpin_reset(GDisplay *g, bool_t state) { + (void) g; + if (state) { + CLR_RST; + } else { + SET_RST; + } +} + +static inline void acquire_bus(GDisplay *g) { + (void) g; + CLR_CS; +} + +static inline void release_bus(GDisplay *g) { + (void) g; + SET_CS; +} + +static inline void write_index(GDisplay *g, uint16_t index) { + (void) g; + + CLR_DC; + palWriteBus(&busDataLo, (index & 0xFF)); + palWriteBus(&busDataHi, (index >> 8)); + writeStrobe; + SET_DC; +} + +static inline void write_data(GDisplay *g, uint16_t data) { + (void) g; + + palWriteBus(&busDataLo, (data & 0xFF)); + palWriteBus(&busDataHi, (data >> 8)); + writeStrobe; +} + +static inline void setreadmode(GDisplay *g) { + (void) g; + palSetBusMode(&busDataLo, PAL_MODE_INPUT_PULLUP); + palSetBusMode(&busDataHi, PAL_MODE_INPUT_PULLUP); +} + +static inline void setwritemode(GDisplay *g) { + (void) g; + palSetBusMode(&busDataLo, PAL_MODE_OUTPUT_PUSHPULL); + palSetBusMode(&busDataHi, PAL_MODE_OUTPUT_PUSHPULL); +} + +static inline uint16_t read_data(GDisplay *g) { + (void) g; + + uint16_t data; + CLR_RD; + data = (palReadBus(&busDataHi) << 8) | palReadBus(&busDataLo); + SET_RD; + return data; +} + +#endif /* _GDISP_LLD_BOARD_H */ diff --git a/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_2.x/Makefile b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_2.x/Makefile new file mode 100644 index 00000000..f163dad2 --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_2.x/Makefile @@ -0,0 +1,58 @@ +# Possible Targets: all clean Debug cleanDebug Release cleanRelease + +############################################################################################## +# Settings +# + +# General settings + # See $(GFXLIB)/tools/gmake_scripts/readme.txt for the list of variables + OPT_OS = chibios + OPT_THUMB = yes + OPT_LINK_OPTIMIZE = yes + OPT_CPU = stm32m4 + +# uGFX settings + # See $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk for the list of variables + GFXLIB = ../uGFX + GFXBOARD = Mikromedia-Plus-STM32-M4 + GFXDEMO = modules/gdisp/basics + +# ChibiOS settings +ifeq ($(OPT_OS),chibios) + # See $(GFXLIB)/tools/gmake_scripts/os_chibios.mk for the list of variables + CHIBIOS = ../ChibiOS + CHIBIOS_BOARD = + CHIBIOS_PLATFORM = STM32F4xx + CHIBIOS_PORT = GCC/ARMCMx/STM32F4xx + CHIBIOS_LDSCRIPT = STM32F407xG.ld + # We define a non standard board script as this is not a standard ChibiOS supported board + include $(GFXLIB)/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/board.mk +endif + +############################################################################################## +# Set these for your project +# + +ARCH = arm-none-eabi- +SRCFLAGS = -ggdb -O0 +CFLAGS = +CXXFLAGS = -fno-rtti +ASFLAGS = +LDFLAGS = + +SRC = +OBJS = +DEFS = +LIBS = +INCPATH = +LIBPATH = +LDSCRIPT = + +############################################################################################## +# These should be at the end +# + +include $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk +include $(GFXLIB)/tools/gmake_scripts/os_$(OPT_OS).mk +include $(GFXLIB)/tools/gmake_scripts/compiler_gcc.mk +# *** EOF *** diff --git a/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_2.x/chconf.h b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_2.x/chconf.h new file mode 100644 index 00000000..f4682cb9 --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_2.x/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_2.x/halconf.h b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_2.x/halconf.h new file mode 100644 index 00000000..6585fb3e --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_2.x/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI TRUE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_2.x/mcuconf.h b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_2.x/mcuconf.h new file mode 100644 index 00000000..29457298 --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_2.x/mcuconf.h @@ -0,0 +1,293 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F40_41xxx + +// Define this if you are using an older ChibiOS version +//#define STM32_VOS STM32_VOS_HIGH + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED FALSE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLM_VALUE 16 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define HAL_USE_I2C TRUE +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() +#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt() + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_2.x/openocd.cfg b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_2.x/openocd.cfg new file mode 100644 index 00000000..f8b6a6f5 --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_2.x/openocd.cfg @@ -0,0 +1,81 @@ +# This is a script file for OpenOCD 0.7.0 +# +# It is set up for the Mikromedia-STM32M4 board using the ST-Link JTAG adaptor. +# +# Assuming the current directory is your project directory containing this openocd.cfg file... +# +# To program your device: +# +# openocd -f openocd.cfg -c "Burn yourfile.bin" -c shutdown +# +# To debug your device: +# +# openocd +# (This will run openocd in gdb server debug mode. Leave it running in the background) +# +# gdb yourfile.elf +# (To start gdb. Then run the following commands in gdb...) +# +# target remote 127.0.0.1:3333 +# monitor Debug +# stepi +# (This last stepi resynchronizes gdb). +# +# If you want to reprogram from within gdb: +# +# monitor Burn yourfile.bin +# + +echo "" +echo "##### Loading debugger..." +source [find interface/stlink-v2.cfg] + +echo "" +echo "##### Loading CPU..." +source [find target/stm32f4x_stlink.cfg] + +echo "" +echo "##### Configuring..." +reset_config srst_only srst_nogate +#cortex_m maskisr (auto|on|off) +#cortex_m vector_catch [all|none|list] +#cortex_m reset_config (srst|sysresetreq|vectreset) +#gdb_breakpoint_override hard + +proc Debug { } { + echo "" + echo "##### Debug Session Connected..." + reset init + echo "Ready..." +} + +proc Burn {file} { + echo "" + echo "##### Burning $file to device..." + halt + # Due to an issue with the combination of the ST-Link adapters and OpenOCD + # applying the stm32f2x unlock 0 command actaully applies read protection - VERY BAD! + # If this happens to you - use the ST-Link utility to set the option byte back to normal. + # If you are using a different debugger eg a FT2232 based adapter you can uncomment the line below. + #stm32f2x unlock 0 + flash protect 0 0 last off + reset init + flash write_image erase $file 0x08000000 + verify_image $file 0x0 + #flash protect 0 0 last on + reset + echo "Burning Complete!" +} + +echo "" +echo "##### Leaving Configuration Mode..." +init +reset init +flash probe 0 +flash banks +#flash info 0 + +echo "" +echo "##### Waiting for debug connections..." + + diff --git a/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_3.x/Makefile b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_3.x/Makefile new file mode 100644 index 00000000..7f274b95 --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_3.x/Makefile @@ -0,0 +1,241 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + # Replace -O0 with -O2 for a production build. -O2 just messes with the debugger. + USE_OPT = -O0 -g -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + ### disable as can cause segfault + USE_LTO = no +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif +# +# Build global options +############################################################################## + +############################################################################### +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU on Cortex-M4 (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +SW = .. + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../ChibiOS +#include $(CHIBIOS)/boards/MIKROMEDIA_STM32_M4/board.mk # Not a standard ChibiOS supported board +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f4xx.mk +LDSCRIPT= $(PORTLD)/STM32F407xG.ld + +# Imported source files and paths for uGFX +GFXLIB = ../ugfx +include $(GFXLIB)/boards/base/Mikromedia-Plus-STM32-M4/board.mk +include $(GFXLIB)/boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/board.mk # The replacement ChibiOS board files +include $(GFXLIB)/gfx.mk + +# Where is our source code - alter these for your project. +# Either just include the demo makefile or add your own definitions +include $(GFXLIB)/demos/modules/gdisp/basics/demo.mk +#MYFILES = my-project-directory +#MYCSRC = $(MYFILES)/main.c +#MYDEFS = + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(GFXSRC) \ + $(MYCSRC) + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ + $(GFXINC) \ + $(MYFILES) + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = $(GFXDEFS) + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + + +RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk
\ No newline at end of file diff --git a/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_3.x/chconf.h b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_3.x/chconf.h new file mode 100644 index 00000000..150bd73c --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_3.x/chconf.h @@ -0,0 +1,498 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_QUEUES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_TRACE FALSE + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_3.x/halconf.h b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_3.x/halconf.h new file mode 100644 index 00000000..40c57eeb --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_3.x/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_3.x/mcuconf.h b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_3.x/mcuconf.h new file mode 100644 index 00000000..9037b61a --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_3.x/mcuconf.h @@ -0,0 +1,304 @@ +/* + ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 16 +#define STM32_PLLN_VALUE 192 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 6 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_PLL +#define STM32_MCO1PRE STM32_MCO1PRE_DIV3 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE FALSE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 TRUE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 diff --git a/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_3.x/openocd.cfg b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_3.x/openocd.cfg new file mode 100644 index 00000000..f8b6a6f5 --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/example_chibios_3.x/openocd.cfg @@ -0,0 +1,81 @@ +# This is a script file for OpenOCD 0.7.0 +# +# It is set up for the Mikromedia-STM32M4 board using the ST-Link JTAG adaptor. +# +# Assuming the current directory is your project directory containing this openocd.cfg file... +# +# To program your device: +# +# openocd -f openocd.cfg -c "Burn yourfile.bin" -c shutdown +# +# To debug your device: +# +# openocd +# (This will run openocd in gdb server debug mode. Leave it running in the background) +# +# gdb yourfile.elf +# (To start gdb. Then run the following commands in gdb...) +# +# target remote 127.0.0.1:3333 +# monitor Debug +# stepi +# (This last stepi resynchronizes gdb). +# +# If you want to reprogram from within gdb: +# +# monitor Burn yourfile.bin +# + +echo "" +echo "##### Loading debugger..." +source [find interface/stlink-v2.cfg] + +echo "" +echo "##### Loading CPU..." +source [find target/stm32f4x_stlink.cfg] + +echo "" +echo "##### Configuring..." +reset_config srst_only srst_nogate +#cortex_m maskisr (auto|on|off) +#cortex_m vector_catch [all|none|list] +#cortex_m reset_config (srst|sysresetreq|vectreset) +#gdb_breakpoint_override hard + +proc Debug { } { + echo "" + echo "##### Debug Session Connected..." + reset init + echo "Ready..." +} + +proc Burn {file} { + echo "" + echo "##### Burning $file to device..." + halt + # Due to an issue with the combination of the ST-Link adapters and OpenOCD + # applying the stm32f2x unlock 0 command actaully applies read protection - VERY BAD! + # If this happens to you - use the ST-Link utility to set the option byte back to normal. + # If you are using a different debugger eg a FT2232 based adapter you can uncomment the line below. + #stm32f2x unlock 0 + flash protect 0 0 last off + reset init + flash write_image erase $file 0x08000000 + verify_image $file 0x0 + #flash protect 0 0 last on + reset + echo "Burning Complete!" +} + +echo "" +echo "##### Leaving Configuration Mode..." +init +reset init +flash probe 0 +flash banks +#flash info 0 + +echo "" +echo "##### Waiting for debug connections..." + + diff --git a/boards/base/Mikromedia-Plus-STM32-M4/gaudio_play_board.h b/boards/base/Mikromedia-Plus-STM32-M4/gaudio_play_board.h new file mode 100644 index 00000000..3efd162f --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/gaudio_play_board.h @@ -0,0 +1,97 @@ +/* + * This file is subject to the terms of the GFX License. If a copy of + * the license was not distributed with this file, you can obtain one at: + * + * http://ugfx.org/license.html + */ + +#ifndef GAUDIO_PLAY_BOARD_H +#define GAUDIO_PLAY_BOARD_H + +#define SET_CS palSetPad(GPIOD, GPIOD_MP3_CS) +#define CLR_CS palClearPad(GPIOD, GPIOD_MP3_CS) +#define SET_RST palSetPad(GPIOD, GPIOD_MP3_RST) +#define CLR_RST palClearPad(GPIOD, GPIOD_MP3_RST) +#define SET_DCS palSetPad(GPIOD, GPIOD_MP3_DCS) +#define CLR_DCS palClearPad(GPIOD, GPIOD_MP3_DCS) +#define GET_DREQ palReadPad(GPIOD, GPIOD_MP3_DREQ) +#define SPI_PORT &SPID2 + +static const SPIConfig spicfg_init = { + 0, + GPIOD, + GPIOD_MP3_CS, + SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0, +}; + +static const SPIConfig spicfg = { + 0, + GPIOD, + GPIOD_MP3_CS, + SPI_CR1_BR_0, +}; + +// Initialise the board +static inline void board_init(void) { + palSetPadMode(GPIOD, GPIOD_MP3_CS, PAL_MODE_OUTPUT_PUSHPULL); + palSetPadMode(GPIOD, GPIOD_MP3_RST, PAL_MODE_OUTPUT_PUSHPULL); + palSetPadMode(GPIOD, GPIOD_MP3_DCS, PAL_MODE_OUTPUT_PUSHPULL); + palSetPadMode(GPIOD, GPIOD_MP3_DREQ, PAL_MODE_INPUT); + SET_CS; SET_RST; SET_DCS; + spiStart(SPI_PORT, &spicfg_init); +} + +// Chip is initialised enough so we can talk fast to it +#define board_init_end() spiStart(SPI_PORT, &spicfg) + +// Reset the board +#define board_reset() { CLR_RST; gfxSleepMilliseconds(1); SET_RST; } + +// Returns the state of the dreq pin +#define board_dreq() GET_DREQ + +// Start a command write +static inline void board_startcmdwrite(void) { + #if SPI_USE_MUTUAL_EXCLUSION + spiAcquireBus(SPI_PORT); + #endif + CLR_CS; +} + +// End a command write +static inline void board_endcmdwrite(void) { + SET_CS; + #if SPI_USE_MUTUAL_EXCLUSION + spiReleaseBus(SPI_PORT); + #endif +} + +// Start a command read +#define board_startcmdread() board_startcmdwrite() + +// End a command read +#define board_endcmdread() board_endcmdwrite() + +// Start a data write +static inline void board_startdatawrite(void) { + #if SPI_USE_MUTUAL_EXCLUSION + spiAcquireBus(SPI_PORT); + #endif + CLR_DCS; +} + +// End a data write +static inline void board_enddatawrite(void) { + #if SPI_USE_MUTUAL_EXCLUSION + spiReleaseBus(SPI_PORT); + #endif + SET_DCS; +} + +// Write data to the SPI port +#define board_spiwrite(buf, len) spiSend(SPI_PORT, len, buf) + +// Read data from the SPI port +#define board_spiread(buf, len) spiReceive(SPI_PORT, len, buf) + +#endif /* GAUDIO_PLAY_BOARD_H */ diff --git a/boards/base/Mikromedia-Plus-STM32-M4/gmouse_lld_STMPE610_board.h b/boards/base/Mikromedia-Plus-STM32-M4/gmouse_lld_STMPE610_board.h new file mode 100644 index 00000000..1acec78a --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/gmouse_lld_STMPE610_board.h @@ -0,0 +1,119 @@ +/* + * This file is subject to the terms of the GFX License. If a copy of + * the license was not distributed with this file, you can obtain one at: + * + * http://ugfx.org/license.html + */ + +#ifndef _GINPUT_LLD_MOUSE_BOARD_H +#define _GINPUT_LLD_MOUSE_BOARD_H + +// Resolution and Accuracy Settings +#define GMOUSE_STMPE610_PEN_CALIBRATE_ERROR 8 +#define GMOUSE_STMPE610_PEN_CLICK_ERROR 6 +#define GMOUSE_STMPE610_PEN_MOVE_ERROR 4 +#define GMOUSE_STMPE610_FINGER_CALIBRATE_ERROR 14 +#define GMOUSE_STMPE610_FINGER_CLICK_ERROR 18 +#define GMOUSE_STMPE610_FINGER_MOVE_ERROR 14 + +// How much extra data to allocate at the end of the GMouse structure for the board's use +#define GMOUSE_STMPE610_BOARD_DATA_SIZE 0 + +// Options - Leave these commented to make it user configurable in the gfxconf.h +//#define GMOUSE_STMPE610_READ_PRESSURE FALSE +//#define GMOUSE_STMPE610_SELF_CALIBRATE FALSE +//#define GMOUSE_STMPE610_TEST_MODE FALSE + +// If TRUE this board has the STMPE610 IRQ pin connected to a GPIO. +// Note: Although this board has such a pin its reliability has not been tested on this board!!!!! +#define GMOUSE_STMPE610_GPIO_IRQPIN FALSE + +// If TRUE this is a really slow CPU and we should always clear the FIFO between reads. +#define GMOUSE_STMPE610_SLOW_CPU FALSE + +// Slave address +#define STMPE610_ADDR (0x88 >> 1) + +// Maximum timeout +#define STMPE610_TIMEOUT 0x3000 + +static const I2CConfig i2ccfg = { + OPMODE_I2C, + 390625, // Conservative please + FAST_DUTY_CYCLE_2, +}; + +static bool_t init_board(GMouse* m, unsigned driverinstance) { + (void) m; + + // This board only supports one touch panel + if (driverinstance) + return FALSE; + + palSetPadMode(GPIOA, 0, PAL_MODE_INPUT | PAL_STM32_PUDR_FLOATING); /* TP IRQ */ + palSetPadMode(GPIOB, 6, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN); /* SCL */ + palSetPadMode(GPIOB, 7, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN); /* SDA */ + + i2cStart(&I2CD1, &i2ccfg); + + return TRUE; +} + +#if GMOUSE_STMPE610_GPIO_IRQPIN + static bool_t getpin_irq(GMouse* m) { + (void) m; + + return !palReadPad(GPIOA, 0); + } +#endif + +static inline void aquire_bus(GMouse* m) { + (void) m; + +} + +static inline void release_bus(GMouse* m) { + (void) m; + +} + +static void write_reg(GMouse* m, uint8_t reg, uint8_t val) { + uint8_t txbuf[2]; + (void) m; + + txbuf[0] = reg; + txbuf[1] = val; + + i2cAcquireBus(&I2CD1); + i2cMasterTransmitTimeout(&I2CD1, STMPE610_ADDR, txbuf, 2, 0, 0, MS2ST(STMPE610_TIMEOUT)); + i2cReleaseBus(&I2CD1); +} + +static uint8_t read_byte(GMouse* m, uint8_t reg) { + uint8_t rxbuf[1]; + (void) m; + + rxbuf[0] = 0; + + i2cAcquireBus(&I2CD1); + i2cMasterTransmitTimeout(&I2CD1, STMPE610_ADDR, ®, 1, rxbuf, 1, MS2ST(STMPE610_TIMEOUT)); + i2cReleaseBus(&I2CD1); + + return rxbuf[0]; +} + +static uint16_t read_word(GMouse* m, uint8_t reg) { + uint8_t rxbuf[2]; + (void) m; + + rxbuf[0] = 0; + rxbuf[1] = 0; + + i2cAcquireBus(&I2CD1); + i2cMasterTransmitTimeout(&I2CD1, STMPE610_ADDR, ®, 1, rxbuf, 2, MS2ST(STMPE610_TIMEOUT)); + i2cReleaseBus(&I2CD1); + + return (((uint16_t)rxbuf[0]) << 8) | rxbuf[1]; +} + +#endif /* _GINPUT_LLD_MOUSE_BOARD_H */ diff --git a/boards/base/Mikromedia-Plus-STM32-M4/readme.txt b/boards/base/Mikromedia-Plus-STM32-M4/readme.txt new file mode 100644 index 00000000..5ac696b5 --- /dev/null +++ b/boards/base/Mikromedia-Plus-STM32-M4/readme.txt @@ -0,0 +1,12 @@ +This directory contains the interface for the MikroMedia Plus STM32 M4 board +running under ChibiOS. + +On this board uGFX currently supports: + - GDISP via the SSD1963 display + - GINPUT-touch via the STMPE610 driver + - GAUDIO via the vs1053 driver + +As this is not a standard ChibiOS supported board the necessary board files have also +been provided in the ChibiOS_Board directory. + +There are two examples, one for ChibiOS/RT 2.x and one for ChibiOS/RT 3.x available. |