Adding HY-MiniSTM32V board support

7 files changed, 672 insertions, 0 deletions

diff --git a/boards/base/HY-MiniSTM32V/board.mk b/boards/base/HY-MiniSTM32V/board.mk
new file mode 100644
index 00000000..eddf09e3
--- /dev/null
+++ b/boards/base/HY-MiniSTM32V/board.mk
@@ -0,0 +1,8 @@
+GFXINC	+= $(GFXLIB)/boards/base/HY-MiniSTM32V
+GFXSRC	+=
+GFXDEFS += -DGFX_USE_CHIBIOS=TRUE
+
+include $(GFXLIB)/boards/base/HY-MiniSTM32V/chibios_board/board.mk
+include $(GFXLIB)/drivers/gdisp/SSD1289/driver.mk
+include $(GFXLIB)/drivers/ginput/touch/ADS7843/driver.mk
+
diff --git a/boards/base/HY-MiniSTM32V/board_SSD1289.h b/boards/base/HY-MiniSTM32V/board_SSD1289.h
new file mode 100644
index 00000000..415dffe9
--- /dev/null
+++ b/boards/base/HY-MiniSTM32V/board_SSD1289.h
@@ -0,0 +1,199 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+#ifndef GDISP_LLD_BOARD_H
+#define GDISP_LLD_BOARD_H
+
+/*
+ * Board file for HY-MiniSTM32V board from HAOYU (China).
+ * www.powermcu.com or www.hotmcu.com.
+ */
+
+/*
+ * NOTE: In order to make this work you need to set:
+ *   STM32_PWM_USE_TIM3     TRUE    in mcuconf.h
+ *   HAL_USE_PWM            TRUE    in halconf.h
+ */
+
+/*
+ * TM3 ch2 is connected to LCD BL_CNT (PB5)
+ */
+static const PWMConfig pwmcfg =
+{
+ 100000,   // frequency
+ 100,      // period
+ NULL,     // callback
+ {
+  {PWM_OUTPUT_DISABLED, 0},
+  {PWM_OUTPUT_ACTIVE_HIGH, 0},
+  {PWM_OUTPUT_DISABLED, 0},
+  {PWM_OUTPUT_DISABLED, 0}
+ },
+ 0,        // cr2
+ 0,        // dier
+};
+
+/*
+ * LCD_RS is on A16 (PD11)
+ */
+#define GDISP_REG   (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
+#define GDISP_RAM   (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
+/*
+ * STM32_DMA1_STREAM7
+ * NOTE: conflicts w/ USART2_TX, TIM2_CH2, TIM2_CH4, TIM4_UP, I2C1_RX in case
+ */
+#define GDISP_DMA_STREAM        STM32_DMA1_STREAM7
+#define FSMC_BANK               0
+
+static inline void init_board(GDisplay *g) {
+  /*
+   * As we are not using multiple displays we set g->board to NULL as we don't
+   * use it.
+   */
+  g->board = 0;
+
+  switch(g->controllerdisplay) {
+  /*
+   * Set up for Display 0
+   */
+  case 0:
+    /* FSMC setup for F1 */
+    rccEnableAHB(RCC_AHBENR_FSMCEN, 0);
+
+    /* Group pins for FSMC setup as alternate function */
+    IOBus busD = { GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) |          \
+                   (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) |    \
+                   (1 << 14) | (1 << 15), 0 };
+
+    IOBus busE = { GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) |         \
+                   (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |             \
+                   (1 << 15), 0 };
+
+    /* FSMC sa alternate function */
+    palSetBusMode(&busD, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
+    palSetBusMode(&busE, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
+
+    /*
+     * NOTE: stm32F10x.h is FAULTY on FSMC
+     * NOTE: Used hardcore bit shifting below
+     * NOTE: All timings for 72MHz HCLK - should be revised for lower HCLK
+     */
+
+    /* FSMC timing - Read: DATAST = 0x20; all the rest = 0.
+     * 100ns cycle time for SSD1289 as per DataSheet
+     */
+    FSMC_Bank1->BTCR[FSMC_BANK+1] = (0x20 << 8);
+
+    /* FSMC timing - Write: DATAST = 0x01, ADDSET = 0x01 all the rest = 0.
+     * 1000ns cycle time for SSD1289 as per DataSheet
+     */
+    FSMC_Bank1E->BWTR[FSMC_BANK] = (0x1 << 8) | (0x01 << 0);
+
+    /* Bank1 NOR/SRAM control register configuration
+     * Note: different read and write cycle timing
+     */
+    FSMC_Bank1->BTCR[FSMC_BANK] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN |          \
+        FSMC_BCR1_MBKEN | FSMC_BCR1_EXTMOD;
+
+    /* DMA Setup. */
+#if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
+    if (dmaStreamAllocate(GDISP_DMA_STREAM, 0, 0, 0))
+      gfxExit();
+
+    dmaStreamSetMemory0(GDISP_DMA_STREAM, &GDISP_RAM);
+    dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) |                    \
+                     STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD |     \
+                     STM32_DMA_CR_DIR_M2M);
+#endif
+
+    /* Display backlight control */
+    /* TIM3 ch2 (PB5) connected to LCD BL_CNT */
+    pwmStart(&PWMD3, &pwmcfg);
+    palSetPadMode(GPIOB, 5, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
+    pwmEnableChannel(&PWMD3, 1, 100);
+
+    break;
+  }
+}
+
+static inline void post_init_board(GDisplay *g) {
+  (void) g;
+}
+
+static inline void setpin_reset(GDisplay *g, bool_t state) {
+  (void) g;
+
+  if(state) {}
+  else {}
+}
+
+static inline void set_backlight(GDisplay *g, uint8_t percent) {
+  (void) g;
+  if (percent > 100) { percent = 100; }
+  pwmEnableChannel(&PWMD3, 1, percent);
+}
+
+static inline void acquire_bus(GDisplay *g) {
+  (void) g;
+}
+
+static inline void release_bus(GDisplay *g) {
+  (void) g;
+}
+
+static inline void write_index(GDisplay *g, uint16_t index) {
+  (void) g;
+  GDISP_REG = index;
+}
+
+static inline void write_data(GDisplay *g, uint16_t data) {
+  (void) g;
+  GDISP_RAM = data;
+}
+
+static inline void setreadmode(GDisplay *g) {
+  (void) g;
+}
+
+static inline void setwritemode(GDisplay *g) {
+  (void) g;
+}
+
+static inline uint16_t read_data(GDisplay *g) {
+  (void) g;
+  return GDISP_RAM;
+}
+
+#if defined(GDISP_USE_DMA) || defined(__DOXYGEN__)
+static inline void dma_with_noinc(GDisplay *g, color_t *buffer, int area) {
+  (void) g;
+  dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer);
+  dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) |                      \
+                   STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD |       \
+                   STM32_DMA_CR_DIR_M2M);
+  for (; area > 0; area -= 65535) {
+    dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area > 65535 ? 65535 : area);
+    dmaStreamEnable(GDISP_DMA_STREAM);
+    dmaWaitCompletion(GDISP_DMA_STREAM);
+  }
+}
+
+static inline void dma_with_inc(GDisplay *g, color_t *buffer, int area) {
+  (void) g;
+  dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer);
+  dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PINC |  \
+                   STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD |       \
+                   STM32_DMA_CR_DIR_M2M);
+  for (; area > 0; area -= 65535) {
+    dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area > 65535 ? 65535 : area);
+    dmaStreamEnable(GDISP_DMA_STREAM);
+    dmaWaitCompletion(GDISP_DMA_STREAM);
+  }
+}
+#endif
+
+#endif /* GDISP_LLD_BOARD_H */
diff --git a/boards/base/HY-MiniSTM32V/chibios_board/board.c b/boards/base/HY-MiniSTM32V/chibios_board/board.c
new file mode 100644
index 00000000..699ffc2b
--- /dev/null
+++ b/boards/base/HY-MiniSTM32V/chibios_board/board.c
@@ -0,0 +1,81 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/*
+ * Board file for HY-MiniSTM32V board from HAOYU (China).
+ * www.powermcu.com or www.hotmcu.com.
+ */
+
+
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+  {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+  {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+  {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+  {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+  {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},
+  {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+  stm32_clock_init();
+}
+
+#if HAL_USE_MMC_SPI
+/*
+ * Board-related functions related to the MMC_SPI driver.
+ * Inserted when PD3 is low.
+ */
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  return !palReadPad(GPIOD, GPIOD_SD_CD);
+}
+
+/*
+ * No wp information available. Assume not protected
+ */
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  return false;
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /* TIM3 partial remap for display BL_CNT on ch 2 (PB5). */
+  AFIO->MAPR |= AFIO_MAPR_TIM3_REMAP_1;
+}
diff --git a/boards/base/HY-MiniSTM32V/chibios_board/board.h b/boards/base/HY-MiniSTM32V/chibios_board/board.h
new file mode 100644
index 00000000..37a4c3c4
--- /dev/null
+++ b/boards/base/HY-MiniSTM32V/chibios_board/board.h
@@ -0,0 +1,277 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2015 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Board file for HY-MiniSTM32V board from HAOYU (China).
+ * www.powermcu.com or www.hotmcu.com.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_HY_MINI_STM32V
+#define BOARD_NAME              "HY-MiniSTM32V"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK            32768
+#define STM32_HSECLK            8000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_HD
+
+/*
+ * IO pins assignments.
+ */
+ 
+#define GPIOA_PIN0 			0
+#define GPIOA_PIN1			1
+#define GPIOA_PIN2			2
+#define GPIOA_PIN3			3
+#define GPIOA_TP_CS			4
+#define GPIOA_SPI_SCK 		5
+#define GPIOA_SPI_MISO		6 
+#define GPIOA_SPI_MOSI		7
+#define GPIOA_PIN8			8
+#define GPIOA_USART1_TX		9
+#define GPIOA_USART1_RX		10
+#define GPIOA_USB_DM 		11
+#define GPIOA_USB_DP		12 
+#define GPIOA_PIN13			13
+#define GPIOA_PIN14			14
+#define GPIOA_PIN15			15
+
+#define GPIOB_LED1			0
+#define GPIOB_LED2			1
+#define GPIOB_USER_KEYB		2
+#define GPIOB_PIN3			3
+#define GPIOB_PIN4			4
+#define GPIOB_BL_CNT		5
+#define GPIOB_TP_IRQ		6
+#define GPIOB_USB_EN		7
+#define GPIOB_PIN8			8
+#define GPIOB_PIN9			9
+#define GPIOB_PIN10			10
+#define GPIOB_PIN11			11
+#define GPIOB_PIN12			12
+#define GPIOB_PIN13			13
+#define GPIOB_PIN14			14
+#define GPIOB_PIN15			15
+
+#define GPIOC_PIN0			0
+#define GPIOC_PIN1			1
+#define GPIOC_PIN2			2
+#define GPIOC_PIN3			3
+#define GPIOC_PIN4			4
+#define GPIOC_PIN5			5
+#define GPIOC_PIN6			6
+#define GPIOC_PIN7			7
+#define GPIOC_SDIO_D0		8
+#define GPIOC_SDIO_D1		9
+#define GPIOC_SDIO_D2		10
+#define GPIOC_SDIO_D3		11
+#define GPIOC_SDIO_CK		12
+#define GPIOC_USER_KEYA		13
+#define GPIOC_PIN14			14
+#define GPIOC_PIN15			15
+
+#define GPIOD_FSMC_D2		0
+#define GPIOD_FSMC_D3		1
+#define GPIOD_SDIO_CMD		2
+#define GPIOD_SD_CD			3
+#define GPIOD_LCD_RD		4
+#define GPIOD_LCD_WR		5
+#define GPIOD_PIN6			6
+#define GPIOD_LCD_CS		7
+#define GPIOD_FSMC_D13		8
+#define GPIOD_FSMC_D14		9
+#define GPIOD_FSMC_D15		10
+#define GPIOD_LCD_RS		11
+#define GPIOD_PIN12			12
+#define GPIOD_PIN13			13
+#define GPIOD_FSMC_D0		14
+#define GPIOD_FSMC_D1		15
+
+#define GPIOE_PIN0			0
+#define GPIOE_PIN1			1
+#define GPIOE_PIN2			2
+#define GPIOE_PIN3			3
+#define GPIOE_PIN4			4
+#define GPIOE_PIN5			5
+#define GPIOE_PIN6			6
+#define GPIOE_FSMC_D4		7
+#define GPIOE_FSMC_D5		8
+#define GPIOE_FSMC_D6		9
+#define GPIOE_FSMC_D7		10
+#define GPIOE_FSMC_D8		11
+#define GPIOE_FSMC_D9		12
+#define GPIOE_FSMC_D10		13
+#define GPIOE_FSMC_D11		14
+#define GPIOE_FSMC_D12		15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ *   0 - Analog input.
+ *   1 - Push Pull output 10MHz.
+ *   2 - Push Pull output 2MHz.
+ *   3 - Push Pull output 50MHz.
+ *   4 - Digital input.
+ *   5 - Open Drain output 10MHz.
+ *   6 - Open Drain output 2MHz.
+ *   7 - Open Drain output 50MHz.
+ *   8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ *   9 - Alternate Push Pull output 10MHz.
+ *   A - Alternate Push Pull output 2MHz.
+ *   B - Alternate Push Pull output 50MHz.
+ *   C - Reserved.
+ *   D - Alternate Open Drain output 10MHz.
+ *   E - Alternate Open Drain output 2MHz.
+ *   F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA4  - Push Pull output 50MHz 			(TP_CS)
+ * PA5  - Alternate Push Pull output 50MHz	(SPI_SCK)
+ * PA6  - Digital input						(SPI_MISO) 
+ * PA7  - Alternate Push Pull output 50MHz	(SPI_MOSI)
+ * PA9  - Alternate Push Pull output 50MHz	(USART1_TX)
+ * PA10  - Digital input					(USART1_RX)
+ * PA11  - Digital input					(USB_DM)
+ */
+#define VAL_GPIOACRL            0xB4B38888      /*  PA7...PA0 */
+#define VAL_GPIOACRH            0x888844B8      /* PA15...PA8 */
+#define VAL_GPIOAODR            0xFFFFFFFF
+
+/*
+ * Port B setup.
+ * Everything input with pull-up except:
+ * PB0 - Push Pull output 50MHz 			(LED1)
+ * PB1 - Push Pull output 50MHz 			(LED2)
+ * PB2 - Digital input						(USER_KEYB)
+ * PB5 - Alternate Push Pull output 50MHz	(BL_CNT)
+ * PB6 - Digital input					    (TP_IRQ)
+ * PB7 - Push Pull output 50MHz (init low)  (USB_EN)
+ */
+
+#define VAL_GPIOBCRL            0x34B88433      /*  PB7...PB0 */
+#define VAL_GPIOBCRH            0x88888888      /* PB15...PB8 */
+#define VAL_GPIOBODR            0xFFFF7FFC
+
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ * PC8 - Digital input						(SDIO_D0)
+ * PC9 - Digital input						(SDIO_D1)
+ * PC10 - Digital input						(SDIO_D2)
+ * PC11 - Digital input						(SDIO_D3)
+ * PC12 - Digital input						(SDIO_CK)
+ * PC13 - Digital input						(GPIOC_USER_KEYA)
+ */
+#define VAL_GPIOCCRL            0x88888888      /*  PC7...PC0 */
+#define VAL_GPIOCCRH            0x88444444      /* PC15...PC8 */
+#define VAL_GPIOCODR            0xFFFFFFFF
+
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD0 - Alternate Push Pull output 50MHz	(FSMC_D2)
+ * PD1 - Alternate Push Pull output 50MHz	(FSMC_D1)
+ * PD2 - Digital input						(SDIO_CMD)
+ * PD3 - Digital input						(SD_CD)
+ * PD4 - Alternate Push Pull output 50MHz	(LCD_RD)
+ * PD5 - Alternate Push Pull output 50MHz	(LCD_WR)
+ * PD7 - Alternate Push Pull output 50MHz	(LCD_CS)
+ * PD8 - Alternate Push Pull output 50MHz	(FSMC_D13)
+ * PD9 - Alternate Push Pull output 50MHz	(FSMC_D14)
+ * PD10 - Alternate Push Pull output 50MHz	(FSMC_D15)
+ * PD11 - Alternate Push Pull output 50MHz	(LCD_RS)
+ * PD14 - Alternate Push Pull output 50MHz	(FSMC_D0)
+ * PD15 - Alternate Push Pull output 50MHz	(FSMC_D1)
+ */
+
+#define VAL_GPIODCRL            0xB8BB44BB      /*  PD7...PD0 */
+#define VAL_GPIODCRH            0xBB88BBBB      /* PD15...PD8 */
+#define VAL_GPIODODR            0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ * PE7 - Alternate Push Pull output 50MHz	(FSMC_D4)
+ * PE8 - Alternate Push Pull output 50MHz	(FSMC_D5)
+ * PE9 - Alternate Push Pull output 50MHz	(FSMC_D6)
+ * PE10 - Alternate Push Pull output 50MHz	(FSMC_D7)
+ * PE11 - Alternate Push Pull output 50MHz	(FSMC_D8)
+ * PE12 - Alternate Push Pull output 50MHz	(FSMC_D9)
+ * PE13 - Alternate Push Pull output 50MHz	(FSMC_D10)
+ * PE14 - Alternate Push Pull output 50MHz	(FSMC_D11)
+ * PE15 - Alternate Push Pull output 50MHz	(FSMC_D12)
+ */
+
+#define VAL_GPIOECRL            0xB8888888      /*  PE7...PE0 */
+#define VAL_GPIOECRH            0xBBBBBBBB      /* PE15...PE8 */
+#define VAL_GPIOEODR            0xFFFFFFFF
+
+/*
+ * Port F setup.
+ * Everything input with pull-up
+ */
+
+#define VAL_GPIOFCRL            0x88888888      /*  PF7...PE0 */
+#define VAL_GPIOFCRH            0x88888888      /* PF15...PE8 */
+#define VAL_GPIOFODR            0xFFFFFFFF
+
+/*
+ * Port G setup.
+ * Everything input with pull-up
+ */
+
+#define VAL_GPIOGCRL            0x88888888      /*  PG7...PE0 */
+#define VAL_GPIOGCRH            0x88888888      /* PG15...PE8 */
+#define VAL_GPIOGODR            0xFFFFFFFF
+
+/*
+ * USB bus activation macro, required by the USB driver.
+ */
+#define usb_lld_connect_bus(usbp) palClearPad(GPIOB, GPIOB_USB_EN)
+
+/*
+ * USB bus de-activation macro, required by the USB driver.
+ */
+#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOB, GPIOB_USB_EN)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/base/HY-MiniSTM32V/chibios_board/board.mk b/boards/base/HY-MiniSTM32V/chibios_board/board.mk
new file mode 100644
index 00000000..814add28
--- /dev/null
+++ b/boards/base/HY-MiniSTM32V/chibios_board/board.mk
@@ -0,0 +1,3 @@
+BOARDINC = $(GFXLIB)/boards/base/HY-MiniSTM32V/chibios_board
+BOARDSRC = $(BOARDINC)/board.c \
+
diff --git a/boards/base/HY-MiniSTM32V/gmouse_lld_ADS7843_board.h b/boards/base/HY-MiniSTM32V/gmouse_lld_ADS7843_board.h
new file mode 100644
index 00000000..840692d2
--- /dev/null
+++ b/boards/base/HY-MiniSTM32V/gmouse_lld_ADS7843_board.h
@@ -0,0 +1,98 @@
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ *              http://ugfx.org/license.html
+ */
+
+/*
+ * Board file for HY-MiniSTM32V board from HAOYU (China).
+ * www.powermcu.com or www.hotmcu.com.
+ */
+
+/*
+ * NOTE: In order to make this work you need to set:
+ *   STM32_SPI_USE_SPI1     TRUE    in mcuconf.h
+ *   HAL_USE_SPI            TRUE    in halconf.h
+ */
+
+#ifndef _GINPUT_LLD_MOUSE_BOARD_H
+#define _GINPUT_LLD_MOUSE_BOARD_H
+
+// Resolution and Accuracy Settings
+#define GMOUSE_ADS7843_PEN_CALIBRATE_ERROR		8
+#define GMOUSE_ADS7843_PEN_CLICK_ERROR			6
+#define GMOUSE_ADS7843_PEN_MOVE_ERROR			4
+#define GMOUSE_ADS7843_FINGER_CALIBRATE_ERROR	14
+#define GMOUSE_ADS7843_FINGER_CLICK_ERROR		18
+#define GMOUSE_ADS7843_FINGER_MOVE_ERROR		14
+
+// How much extra data to allocate at the end of the GMouse structure for the board's use
+#define BOARD_DATA_SIZE			0
+
+static const SPIConfig spicfg = {
+  0,
+  GPIOA,
+  GPIOA_TP_CS,
+  SPI_CR1_BR_1 | SPI_CR1_BR_0,  /* Might be tweaked for faster transfer. */
+};
+
+/*
+ * ADS7843 (clone chip) is connected to SPI1 w/o remap
+ * TP_CS         PA4
+ * SPI_SCK      PA5
+ * SPI_MISO     PA6
+ * SPI_MOSI     PA7
+ * TP_IRQ       PB6
+ */
+
+static bool_t init_board(GMouse* m, unsigned driverinstance) {
+  (void) m;
+  (void) driverinstance;
+
+  palSetPadMode(GPIOA, 4, PAL_MODE_OUTPUT_PUSHPULL);
+  palSetPadMode(GPIOA, 5, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
+  palSetPadMode(GPIOA, 6, PAL_MODE_INPUT_PULLUP);
+  palSetPadMode(GPIOA, 7, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
+  palSetPadMode(GPIOB, 6, PAL_MODE_INPUT);
+
+  spiStart(&SPID1, &spicfg);
+  return true;
+}
+
+/*
+ * PB6 is connected to TP_IRQ (low active).
+ */
+static inline bool_t getpin_pressed(GMouse* m) {
+  (void)m;
+  return (!palReadPad(GPIOB, 6));
+}
+
+/*
+ * PA4 is connected to TP_CS (low active):
+ */
+static inline void aquire_bus(GMouse* m) {
+  (void)m;
+  spiAcquireBus(&SPID1);
+  palClearPad(GPIOA, 4);
+}
+
+static inline void release_bus(GMouse* m) {
+  (void)m;
+  palSetPad(GPIOA, 4);
+  spiReleaseBus(&SPID1);
+}
+
+static inline uint16_t read_value(GMouse* m, uint16_t port) {
+  (void)m;
+  static uint8_t txbuf[3] = {0};
+  static uint8_t rxbuf[3] = {0};
+  uint16_t ret;
+
+  txbuf[0] = port;
+  spiExchange(&SPID1, 3, txbuf, rxbuf);
+  ret = (rxbuf[1] << 5) | (rxbuf[2] >> 3);
+  return ret;
+}
+
+#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
diff --git a/boards/base/HY-MiniSTM32V/readme.txt b/boards/base/HY-MiniSTM32V/readme.txt
new file mode 100644
index 00000000..80927c14
--- /dev/null
+++ b/boards/base/HY-MiniSTM32V/readme.txt
@@ -0,0 +1,6 @@
+This directory contains the interface for the HY-MiniSTM32V board
+running ChibiOS/RT.
+
+As this is not a standard ChibiOS/RT supported board, the necessary board files have
+also been provided in the chibios_board directory
+