Working STM32F746G-Discovery board + example for raw32

Working STM32LTDC video driver

1 files changed, 122 insertions, 0 deletions

diff --git a/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c b/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c
new file mode 100644
index 00000000..3d493e5c
--- /dev/null
+++ b/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c
@@ -0,0 +1,122 @@
+#include "gfx.h"
+#include "stm32f7xx_hal.h"
+
+systemticks_t gfxSystemTicks(void)
+{
+	return HAL_GetTick();
+}
+
+systemticks_t gfxMillisecondsToTicks(delaytime_t ms)
+{
+	return ms;
+}
+
+static void SystemClock_Config(void);
+static void CPU_CACHE_Enable(void);
+static void LCD_Config(void);
+
+void Raw32OSInit(void) {
+    RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
+
+    /* Enable the CPU Cache */
+    CPU_CACHE_Enable();
+
+    /* STM32F7xx HAL library initialization:
+         - Configure the Flash ART accelerator on ITCM interface
+         - Configure the Systick to generate an interrupt each 1 msec
+         - Set NVIC Group Priority to 4
+         - Global MSP (MCU Support Package) initialization
+       */
+    HAL_Init();
+
+    /* Configure the system clock to 216 MHz */
+    SystemClock_Config();
+
+    // LED - for testing
+	GPIO_InitTypeDef  GPIO_InitStruct;
+	GPIO_InitStruct.Pin = GPIO_PIN_1;
+	GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+	GPIO_InitStruct.Pull = GPIO_NOPULL;
+	GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
+    __GPIOI_CLK_ENABLE();
+	HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
+
+}
+
+/**
+  * @brief  System Clock Configuration
+  *         The system Clock is configured as follow :
+  *            System Clock source            = PLL (HSE)
+  *            SYSCLK(Hz)                     = 200000000	/ 216000000
+  *            HCLK(Hz)                       = 200000000	/ 216000000
+  *            AHB Prescaler                  = 1
+  *            APB1 Prescaler                 = 4
+  *            APB2 Prescaler                 = 2
+  *            HSE Frequency(Hz)              = 25000000
+  *            PLL_M                          = 25
+  *            PLL_N                          = 400			/ 432
+  *            PLL_P                          = 2
+  *            PLL_Q                          = 8			/ 9
+  *            VDD(V)                         = 3.3
+  *            Main regulator output voltage  = Scale1 mode
+  *            Flash Latency(WS)              = 6			/ 7
+  * @param  None
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  HAL_StatusTypeDef ret = HAL_OK;
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 25;
+  RCC_OscInitStruct.PLL.PLLN = 400;		// 432
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 8;		// 9
+
+  ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
+  if(ret != HAL_OK)
+  {
+    while(1) { ; }
+  }
+
+  /* Activate the OverDrive to reach the 200/216 MHz Frequency */
+  ret = HAL_PWREx_EnableOverDrive();
+  if(ret != HAL_OK)
+  {
+    while(1) { ; }
+  }
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+  ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6);	// FLASH_LATENCY_7
+  if(ret != HAL_OK)
+  {
+    while(1) { ; }
+  }
+}
+
+/**
+  * @brief  CPU L1-Cache enable.
+  * @param  None
+  * @retval None
+  */
+static void CPU_CACHE_Enable(void)
+{
+  /* Enable I-Cache */
+  SCB_EnableICache();
+
+  /* Enable D-Cache */
+  SCB_EnableDCache();
+}
+